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Precisely specify bus frequencies

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This commit is contained in:
Jerry Zhao
2023-10-31 14:25:16 -07:00
parent 59fd67df57
commit a8766ea8fc
8 changed files with 24 additions and 5 deletions
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2
generators/chipyard/src/main/scala/Subsystem.scala
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@@ -29,7 +29,7 @@ import testchipip.{CanHavePeripheryTLSerial, SerialTLKey}
trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr
if (this match {
case _: CanHavePeripheryTLSerial if (!p(SerialTLKey).isEmpty) => true
case _: CanHavePeripheryTLSerial if (p(SerialTLKey).size != 0) => true
case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true
case _ => false
}) {

3
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -85,6 +85,9 @@ class ChipBringupHostConfig extends Config(
new chipyard.config.WithFrontBusFrequency(75.0) ++ // run all buses of this system at 75 MHz
new chipyard.config.WithMemoryBusFrequency(75.0) ++
new chipyard.config.WithPeripheryBusFrequency(75.0) ++
new chipyard.config.WithSystemBusFrequency(75.0) ++
new chipyard.config.WithControlBusFrequency(75.0) ++
new chipyard.config.WithOffchipBusFrequency(75.0) ++
// Base is the no-cores config
new chipyard.NoCoresConfig)