Updated VCU118 | Bumped naming on Arty

fpga/src/main/scala/arty/HarnessBinders.scala

@@ -58,7 +58,6 @@ class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
     //     IOBUF(th.jd_1, j.TRSTn)
     //     PULLUP(th.jd_1)
     // }
-    Nil
   }
 })
 
@@ -68,6 +67,5 @@ class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
     // UARTAdapter.connect(ports)(system.p)
     // IOBUF(th.ck_io(2),  ports.txd)
     // IOBUF(th.ck_io(3),  ports.rxd)
-    Nil
   }
 })

fpga/src/main/scala/arty/TestHarness.scala

@@ -7,11 +7,12 @@ import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.config.{Field, Parameters}
 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
 import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions}
+import chipyard.iobinders.{HasIOBinders}
 import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
 
 class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
 
-  val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
+  val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
 
   // turn IO clock into Reset type
   val hReset = Wire(Reset())
@@ -19,17 +20,20 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
 
   // default to 32MHz clock
   withClockAndReset(clock_32MHz, hReset) {
-    val dut = Module(ldut.module)
+    val dut = Module(lazyDut.module)
   }
 
   val harnessClock = clock_32MHz
   val harnessReset = hReset
   val success = false.B
+
   val dutReset = reset_core
 
-  // must be after HasHarnessSignalReferences assignments
+  lazyDut match { case d: HasTestHarnessFunctions =>
-  ldut match { case d: HasTestHarnessFunctions =>
     d.harnessFunctions.foreach(_(this))
-    ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap)
   }
+  lazyDut match { case d: HasIOBinders =>
+    ApplyHarnessBinders(this, d.lazySystem, d.portMap)
+  }
+
 }

fpga/src/main/scala/vcu118/Configs.scala

@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118
 
 import sys.process._
 
-import freechips.rocketchip.config.{Config}
+import freechips.rocketchip.config.{Config, Parameters}
 import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
 import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
@@ -15,6 +15,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
 
+import chipyard.{BuildSystem}
+
 class WithDefaultPeripherals extends Config((site, here, up) => {
   case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))
   case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L)))
@@ -22,6 +24,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
 })
 
 class WithSystemModifications extends Config((site, here, up) => {
+  case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top
   case DebugModuleKey => None // disable debug module
   case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS
   case SystemBusKey => up(SystemBusKey).copy(

fpga/src/main/scala/vcu118/DigitalTop.scala

@@ -0,0 +1,62 @@
+package chipyard.fpga.vcu118
+
+import chisel3._
+
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.system._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+import chipyard.{DigitalTop, DigitalTopModule}
+
+// ------------------------------------
+// VCU118 DigitalTop
+// ------------------------------------
+
+class VCU118DigitalTop(implicit p: Parameters) extends DigitalTop
+  with sifive.blocks.devices.spi.HasPeripherySPI
+  with CanHaveMasterTLMemPort
+{
+  override lazy val module = new VCU118DigitalTopModule(this)
+}
+
+class VCU118DigitalTopModule[+L <: VCU118DigitalTop](l: L) extends DigitalTopModule(l)
+  with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
+
+/** Adds a TileLink port to the system intended to master an MMIO device bus */
+trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
+  private val memPortParamsOpt = p(ExtMem)
+  private val portName = "tl_mem"
+  private val device = new MemoryDevice
+  private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
+
+  val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) =>
+    Seq.tabulate(nMemoryChannels) { channel =>
+      val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
+      val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
+
+     TLSlavePortParameters.v1(
+       managers = Seq(TLSlaveParameters.v1(
+         address            = base.flatMap(_.intersect(filter)),
+         resources          = device.reg,
+         regionType         = RegionType.UNCACHED, // cacheable
+         executable         = true,
+         supportsGet        = TransferSizes(1, mbus.blockBytes),
+         supportsPutFull    = TransferSizes(1, mbus.blockBytes),
+         supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
+         beatBytes = memPortParams.beatBytes)
+   }
+ }).toList.flatten)
+
+ mbus.coupleTo(s"memory_controller_port_named_$portName") {
+   (memTLNode
+     :*= TLBuffer()
+     :*= TLSourceShrinker(1 << idBits)
+     :*= TLWidthWidget(mbus.beatBytes)
+     :*= _)
+  }
+
+  val mem_tl = InModuleBody { memTLNode.makeIOs() }
+}

fpga/src/main/scala/vcu118/HarnessBinders.scala

@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle}
 import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
 import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
 
-import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences}
+import chipyard.{HasHarnessSignalReferences}
 import chipyard.harness.{OverrideHarnessBinder}
 
 /*** UART ***/
@@ -18,8 +18,6 @@ class WithUART extends OverrideHarnessBinder({
     th match { case vcu118th: VCU118FPGATestHarnessImp => {
       vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head
     } }
-
-    Nil
   }
 })
 
@@ -29,8 +27,6 @@ class WithSPISDCard extends OverrideHarnessBinder({
     th match { case vcu118th: VCU118FPGATestHarnessImp => {
       vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head
     } }
-
-    Nil
   }
 })
 
@@ -45,7 +41,5 @@ class WithDDRMem extends OverrideHarnessBinder({
       bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
       ddrClientBundle <> ports.head
     } }
-
-    Nil
   }
 })

fpga/src/main/scala/vcu118/IOBinders.scala

@@ -11,7 +11,6 @@ import freechips.rocketchip.tilelink.{TLBundle}
 import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp}
 import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice}
 
-import chipyard.{CanHaveMasterTLMemPort}
 import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder}
 
 class WithUARTIOPassthrough extends OverrideIOBinder({

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -15,10 +15,9 @@ import sifive.fpgashells.clocks._
 
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
-import sifive.blocks.devices.i2c._
 import sifive.blocks.devices.gpio._
 
-import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop}
+import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop}
 import chipyard.iobinders.{HasIOBinders}
 import chipyard.harness.{ApplyHarnessBinders}
 
@@ -125,10 +124,13 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
 
   _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset)
 
-  // cy stuff
+  // reset setup
+  val hReset = Wire(Reset())
+  hReset := _outer.dutClock.in.head._1.reset
+
   val harnessClock = _outer.dutClock.in.head._1.clock
-  val harnessReset = WireInit(_outer.dutClock.in.head._1.reset)
+  val harnessReset = WireInit(hReset)
-  val dutReset = harnessReset
+  val dutReset = hReset.asAsyncReset
   val success = false.B
 
   childClock := harnessClock

fpga/src/main/scala/vcu118/bringup/Configs.scala

@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118.bringup
 
 import math.min
 
-import freechips.rocketchip.config.{Config}
+import freechips.rocketchip.config.{Config, Parameters}
 import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
 
 import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams}
@@ -13,6 +13,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
 
+import chipyard.{BuildSystem}
+
 import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config}
 
 class WithBringupPeripherals extends Config((site, here, up) => {
@@ -34,6 +36,10 @@ class WithBringupPeripherals extends Config((site, here, up) => {
   }
 })
 
+class WithBringupVCU118System extends Config((site, here, up) => {
+  case BuildSystem => (p: Parameters) => new BringupVCU118DigitalTop()(p) // use the VCU118-extended bringup digital top
+})
+
 class WithBringupAdditions extends Config(
   new WithBringupUART ++
   new WithBringupSPI ++
@@ -41,7 +47,8 @@ class WithBringupAdditions extends Config(
   new WithBringupGPIO ++
   new WithI2CIOPassthrough ++
   new WithGPIOIOPassthrough ++
-  new WithBringupPeripherals)
+  new WithBringupPeripherals ++
+  new WithBringupVCU118System)
 
 class RocketBringupConfig extends Config(
   new WithBringupPeripherals ++

fpga/src/main/scala/vcu118/bringup/DigitalTop.scala

@@ -0,0 +1,25 @@
+package chipyard.fpga.vcu118.bringup
+
+import chisel3._
+
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.system._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule}
+
+// ------------------------------------
+// BringupVCU118 DigitalTop
+// ------------------------------------
+
+class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop
+  with sifive.blocks.devices.i2c.HasPeripheryI2C
+{
+  override lazy val module = new BringupVCU118DigitalTopModule(this)
+}
+
+class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l)
+  with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp

fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala

@@ -19,8 +19,6 @@ class WithBringupUART extends ComposeHarnessBinder({
 
       vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last
     } }
-
-    Nil
   }
 })
 
@@ -32,8 +30,6 @@ class WithBringupSPI extends ComposeHarnessBinder({
 
       vcu118th.bringupOuter.io_adi_spi_bb.bundle <> ports.last
     } }
-
-    Nil
   }
 })
 
@@ -45,8 +41,6 @@ class WithBringupI2C extends OverrideHarnessBinder({
 
       vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head
     } }
-
-    Nil
   }
 })
 
@@ -58,7 +52,5 @@ class WithBringupGPIO extends OverrideHarnessBinder({
         bb_io.bundle <> dut_io
       }
     } }
-
-    Nil
   }
 })

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -26,7 +26,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
   with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
   with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
-  with CanHaveMasterTLMemPort
 {
   override lazy val module = new DigitalTopModule(this)
 }
@@ -39,42 +38,3 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
   with chipyard.example.CanHavePeripheryGCDModuleImp
   with freechips.rocketchip.util.DontTouch
 // DOC include end: DigitalTop
-
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-
-/** Adds a TileLink port to the system intended to master an MMIO device bus */
-trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
-  private val memPortParamsOpt = p(ExtMem)
-  private val portName = "tl_mem"
-  private val device = new MemoryDevice
-  private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
-
-  val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) =>
-    Seq.tabulate(nMemoryChannels) { channel =>
-      val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
-      val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
-
-      TLSlavePortParameters.v1(
-        managers = Seq(TLSlaveParameters.v1(
-          address            = base.flatMap(_.intersect(filter)),
-          resources          = device.reg,
-          regionType         = RegionType.UNCACHED, // cacheable
-          executable         = true,
-          supportsGet        = TransferSizes(1, mbus.blockBytes),
-          supportsPutFull    = TransferSizes(1, mbus.blockBytes),
-          supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
-        beatBytes = memPortParams.beatBytes)
-    }
-  }).toList.flatten)
-
-  mbus.coupleTo(s"memory_controller_port_named_$portName") {
-    (memTLNode
-      :*= TLBuffer()
-      :*= TLSourceShrinker(1 << idBits)
-      :*= TLWidthWidget(mbus.beatBytes)
-      :*= _)
-  }
-
-  val mem_tl = InModuleBody { memTLNode.makeIOs() }
-}