Updated VCU118 | Bumped naming on Arty

fpga/src/main/scala/vcu118/bringup/Configs.scala

@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118.bringup
 
 import math.min
 
-import freechips.rocketchip.config.{Config}
+import freechips.rocketchip.config.{Config, Parameters}
 import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
 
 import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams}
@@ -13,6 +13,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
 
+import chipyard.{BuildSystem}
+
 import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config}
 
 class WithBringupPeripherals extends Config((site, here, up) => {
@@ -34,6 +36,10 @@ class WithBringupPeripherals extends Config((site, here, up) => {
   }
 })
 
+class WithBringupVCU118System extends Config((site, here, up) => {
+  case BuildSystem => (p: Parameters) => new BringupVCU118DigitalTop()(p) // use the VCU118-extended bringup digital top
+})
+
 class WithBringupAdditions extends Config(
   new WithBringupUART ++
   new WithBringupSPI ++
@@ -41,7 +47,8 @@ class WithBringupAdditions extends Config(
   new WithBringupGPIO ++
   new WithI2CIOPassthrough ++
   new WithGPIOIOPassthrough ++
-  new WithBringupPeripherals)
+  new WithBringupPeripherals ++
+  new WithBringupVCU118System)
 
 class RocketBringupConfig extends Config(
   new WithBringupPeripherals ++

fpga/src/main/scala/vcu118/bringup/DigitalTop.scala

@@ -0,0 +1,25 @@
+package chipyard.fpga.vcu118.bringup
+
+import chisel3._
+
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.system._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule}
+
+// ------------------------------------
+// BringupVCU118 DigitalTop
+// ------------------------------------
+
+class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop
+  with sifive.blocks.devices.i2c.HasPeripheryI2C
+{
+  override lazy val module = new BringupVCU118DigitalTopModule(this)
+}
+
+class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l)
+  with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp

fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala

@@ -19,8 +19,6 @@ class WithBringupUART extends ComposeHarnessBinder({
 
       vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last
     } }
-
-    Nil
   }
 })
 
@@ -32,8 +30,6 @@ class WithBringupSPI extends ComposeHarnessBinder({
 
       vcu118th.bringupOuter.io_adi_spi_bb.bundle <> ports.last
     } }
-
-    Nil
   }
 })
 
@@ -45,8 +41,6 @@ class WithBringupI2C extends OverrideHarnessBinder({
 
       vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head
     } }
-
-    Nil
   }
 })
 
@@ -58,7 +52,5 @@ class WithBringupGPIO extends OverrideHarnessBinder({
         bb_io.bundle <> dut_io
       }
     } }
-
-    Nil
   }
 })