Updated VCU118 | Bumped naming on Arty

2020-11-05 13:59:10 -08:00
parent 356fa70c3c
commit a7ab0dab59
11 changed files with 117 additions and 71 deletions
--- a/fpga/src/main/scala/vcu118/IOBinders.scala
+++ b/fpga/src/main/scala/vcu118/IOBinders.scala
@@ -11,7 +11,6 @@ import freechips.rocketchip.tilelink.{TLBundle}
 import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp}
 import sifive.blocks.devices.spi.{HasPeripherySPI, HasPeripherySPIModuleImp, MMCDevice}

-import chipyard.{CanHaveMasterTLMemPort}
 import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder}

 class WithUARTIOPassthrough extends OverrideIOBinder({