From a715dab1e2965e630ee80eeb2de1785c4bca0a0f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 10 Jun 2022 07:35:37 -0400 Subject: [PATCH] stage: avoid naming targets listed in RocketChiselStage (#1170) --- .../chipyard/src/main/scala/stage/ChipyardStage.scala | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala index a830c3a8..def8dd90 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala @@ -19,14 +19,8 @@ class ChipyardStage extends ChiselStage { Dependency[freechips.rocketchip.stage.phases.Checks], Dependency[freechips.rocketchip.stage.phases.TransformAnnotations], Dependency[freechips.rocketchip.stage.phases.PreElaboration], - Dependency[chisel3.stage.phases.Checks], - Dependency[chisel3.stage.phases.Elaborate], - Dependency[freechips.rocketchip.stage.phases.GenerateROMs], - Dependency[chisel3.stage.phases.AddImplicitOutputFile], - Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile], - Dependency[chisel3.stage.phases.MaybeAspectPhase], - Dependency[chisel3.stage.phases.Emitter], - Dependency[chisel3.stage.phases.Convert], + // Note: Dependency[RocketChiselStage] is not listed here because it is + // package private, however it is named as a prereq for the passes below. Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], Dependency[freechips.rocketchip.stage.phases.AddDefaultTests], Dependency[chipyard.stage.phases.AddDefaultTests],