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Fix FireChip BridgeBinders

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This commit is contained in:
Jerry Zhao
2020-07-01 12:21:51 -07:00
parent 863f723708
commit a7047c4ba2
3 changed files with 79 additions and 62 deletions
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54
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -26,7 +26,7 @@ import ariane.ArianeTile
import boom.common.{BoomTile}
import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters}
import testchipip.{CanHaveTraceIOModuleImp}
object MainMemoryConsts {
@@ -35,63 +35,67 @@ object MainMemoryConsts {
}
class WithSerialBridge extends OverrideIOBinder({
(system: CanHavePeripherySerialModuleImp, p) =>
system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(p)); Nil
(system: CanHavePeripherySerialModuleImp) =>
system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(system.p)); Nil
})
class WithNICBridge extends OverrideIOBinder({
(system: CanHavePeripheryIceNICModuleImp, p) =>
system.net.foreach(n => NICBridge(system.clock, n)(p)); Nil
(system: CanHavePeripheryIceNICModuleImp) =>
system.net.foreach(n => NICBridge(system.clock, n)(system.p)); Nil
})
class WithUARTBridge extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp, p) =>
system.uart.foreach(u => UARTBridge(system.clock, u)(p)); Nil
(system: HasPeripheryUARTModuleImp) =>
system.uart.foreach(u => UARTBridge(system.clock, u)(system.p)); Nil
})
class WithBlockDeviceBridge extends OverrideIOBinder({
(system: CanHavePeripheryBlockDeviceModuleImp, p) =>
system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(p)); Nil
(system: CanHavePeripheryBlockDeviceModuleImp) =>
system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(system.p)); Nil
})
class WithFASEDBridge extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPort, p) => {
(system: CanHaveMasterAXI4MemPort) => {
implicit val p: Parameters = GetSystemParameters(system)
(system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) =>
val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
axi4.ar.bits.addr.getWidth,
axi4.ar.bits.id.getWidth)
FASEDBridge(system.module.clock, axi4, system.module.reset.toBool,
CompleteConfig(p(firesim.configs.MemModelKey),
nastiKey,
Some(AXI4EdgeSummary(edge)),
Some(MainMemoryConsts.globalName)))
system match {
case s: BaseSubsystem => FASEDBridge(s.module.clock, axi4, s.module.reset.toBool,
CompleteConfig(p(firesim.configs.MemModelKey),
nastiKey,
Some(AXI4EdgeSummary(edge)),
Some(MainMemoryConsts.globalName)))
case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design")
}
})
Nil
}
})
class WithTracerVBridge extends ComposeIOBinder({
(system: CanHaveTraceIOModuleImp, p) =>
system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(p))); Nil
(system: CanHaveTraceIOModuleImp) =>
system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil
})
class WithDromajoBridge extends ComposeIOBinder({
(system: CanHaveTraceIOModuleImp, p) => {
system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(p))); Nil
(system: CanHaveTraceIOModuleImp) => {
system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil
}
})
class WithTraceGenBridge extends OverrideIOBinder({
(system: TraceGenSystemModuleImp, p) =>
(system: TraceGenSystemModuleImp) =>
GroundTestBridge(system.clock, system.success)(system.p); Nil
})
class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
(system: HasTilesModuleImp, p) => {
(system: HasTilesModuleImp) => {
system.outer.tiles.map {
case r: RocketTile => {
annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
@@ -115,13 +119,13 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
})
class WithTiedOffSystemGPIO extends OverrideIOBinder({
(system: HasPeripheryGPIOModuleImp, p) =>
(system: HasPeripheryGPIOModuleImp) =>
system.gpio.foreach(_.pins.foreach(_.i.ival := false.B)); Nil
})
class WithTiedOffSystemDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp, p) => {
Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(p)
(system: HasPeripheryDebugModuleImp) => {
Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p)
// tieoffDebug doesn't actually tie everything off :/
system.debug.foreach { d =>
d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
@@ -132,7 +136,7 @@ class WithTiedOffSystemDebug extends OverrideIOBinder({
})
class WithTiedOffSystemInterrupts extends OverrideIOBinder({
(system: HasExtInterruptsModuleImp, p) =>
(system: HasExtInterruptsModuleImp) =>
system.interrupts := 0.U; Nil
})