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Rename GPUConfig->CoalescerConfigs; fix trace filenames

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This commit is contained in:
Hansung Kim
2023-07-22 14:36:50 -07:00
parent d85a651324
commit a63f3b9d1d
1 changed files with 57 additions and 70 deletions
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85
generators/chipyard/src/main/scala/config/GPUConfig.scala → generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
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@@ -3,7 +3,6 @@ package chipyard
import org.chipsalliance.cde.config.{Config} import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
class MemtraceCoreConfig extends Config( class MemtraceCoreConfig extends Config(
// Memtrace // Memtrace
new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace", new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
@@ -28,8 +27,7 @@ class MemtraceCoreConfig extends Config(
//8 src id section //8 src id section
class MemtraceCoreNV64B8IdConfig extends Config( class MemtraceCoreNV64B8IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++ traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
@@ -43,8 +41,7 @@ class MemtraceCoreNV64B8IdConfig extends Config(
) )
class MemtraceCoreNV128B8IdConfig extends Config( class MemtraceCoreNV128B8IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++ traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
@@ -58,8 +55,7 @@ class MemtraceCoreNV128B8IdConfig extends Config(
) )
class MemtraceCoreNV256B8IdConfig extends Config( class MemtraceCoreNV256B8IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++ traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
@@ -72,25 +68,23 @@ class MemtraceCoreNV256B8IdConfig extends Config(
new chipyard.config.AbstractConfig new chipyard.config.AbstractConfig
) )
class MemtraceCoreNV512B8IdConfig extends Config( class MemtraceCoreNV512B8IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace", traceHasSource = false) ++
traceHasSource = false) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ // L2
// L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(512) ++
new chipyard.config.WithSystemBusWidth(512) ++ // Small Rocket core that does nothing
// Small Rocket core that does nothing new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ new chipyard.config.AbstractConfig
new chipyard.config.AbstractConfig )
)
//16 src id section //16 src id section
class MemtraceCoreNV64B16IdConfig extends Config( class MemtraceCoreNV64B16IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++ traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
@@ -104,8 +98,7 @@ class MemtraceCoreNV64B16IdConfig extends Config(
) )
class MemtraceCoreNV128B16IdConfig extends Config( class MemtraceCoreNV128B16IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++ traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
@@ -119,8 +112,7 @@ class MemtraceCoreNV128B16IdConfig extends Config(
) )
class MemtraceCoreNV256B16IdConfig extends Config( class MemtraceCoreNV256B16IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++ traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
@@ -134,8 +126,7 @@ class MemtraceCoreNV256B16IdConfig extends Config(
) )
class MemtraceCoreNV512B16IdConfig extends Config( class MemtraceCoreNV512B16IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++ traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
@@ -150,8 +141,7 @@ class MemtraceCoreNV512B16IdConfig extends Config(
// 32 ids sections // 32 ids sections
class MemtraceCoreNV64B32IdConfig extends Config( class MemtraceCoreNV64B32IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++ traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
@@ -165,8 +155,7 @@ class MemtraceCoreNV64B32IdConfig extends Config(
) )
class MemtraceCoreNV128B32IdConfig extends Config( class MemtraceCoreNV128B32IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++ traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
@@ -180,8 +169,7 @@ class MemtraceCoreNV128B32IdConfig extends Config(
) )
class MemtraceCoreNV256B32IdConfig extends Config( class MemtraceCoreNV256B32IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
traceHasSource = false) ++ traceHasSource = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
@@ -194,17 +182,16 @@ class MemtraceCoreNV256B32IdConfig extends Config(
new chipyard.config.AbstractConfig new chipyard.config.AbstractConfig
) )
class MemtraceCoreNV512B32IdConfig extends Config( class MemtraceCoreNV512B32IdConfig extends Config(
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace", traceHasSource = false) ++
traceHasSource = false) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ // L2
// L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.WithSystemBusWidth(512) ++
new chipyard.config.WithSystemBusWidth(512) ++ // Small Rocket core that does nothing
// Small Rocket core that does nothing new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ new chipyard.config.AbstractConfig
new chipyard.config.AbstractConfig )
)