diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 74f2cdda..e61e5d03 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -7,18 +7,12 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // Rocket Configs // -------------- - - - class RocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) class TinyRocketConfig extends Config( new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO FIX: Don't dontTouch the ports - new chipyard.config.WithTLSerialLocation( - freechips.rocketchip.subsystem.FBUS, - freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory @@ -55,7 +49,6 @@ class GB1MemoryRocketConfig extends Config( // DOC include start: l1scratchpadrocket class ScratchpadOnlyRocketConfig extends Config( - new testchipip.WithSerialPBusMem ++ new chipyard.config.WithL2TLBs(0) ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port @@ -77,36 +70,38 @@ class L1ScratchpadRocketConfig extends Config( new chipyard.config.AbstractConfig) // DOC include start: mbusscratchpadrocket -class MbusScratchpadRocketConfig extends Config( - new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad - new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port +class MbusScratchpadOnlyRocketConfig extends Config( + new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: mbusscratchpadrocket +class SbusScratchpadRocketConfig extends Config( + new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus backing scratchpad + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + + class MulticlockRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Frequency specifications - new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 - new chipyard.config.WithSystemBusFrequency(800.0) ++ // Ditto - new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) - new chipyard.config.WithPeripheryBusFrequency(100) ++ // Retains the default pbus frequency - new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz) + new chipyard.config.WithTileFrequency(1000.0) ++ // Matches the maximum frequency of U540 + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit"), Nil), + ("periphery", Seq("pbus", "fbus"), Nil)) ++ + new chipyard.config.WithSystemBusFrequency(500.0) ++ // Matches the maximum frequency of U540 + new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Matches the maximum frequency of U540 + new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Matches the maximum frequency of U540 // Crossing specifications + new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between FBUS and SBUS new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new chipyard.config.AbstractConfig) -class TestChipMulticlockRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.WithTestChipBusFreqs ++ - new chipyard.config.AbstractConfig) - // DOC include start: MulticlockAXIOverSerialConfig class MulticlockAXIOverSerialConfig extends Config( - new chipyard.config.WithSystemBusFrequencyAsDefault ++ new chipyard.config.WithSystemBusFrequency(250) ++ new chipyard.config.WithPeripheryBusFrequency(250) ++ new chipyard.config.WithMemoryBusFrequency(250) ++ @@ -121,9 +116,10 @@ class MulticlockAXIOverSerialConfig extends Config( AsynchronousCrossing().sourceSync) ++ new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled - new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory + new testchipip.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory new freechips.rocketchip.subsystem.WithNBigCores(2) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel new chipyard.config.AbstractConfig) // DOC include end: MulticlockAXIOverSerialConfig @@ -132,3 +128,12 @@ class CustomIOChipTopRocketConfig extends Config( new chipyard.example.WithCustomIOCells ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) + +class PrefetchingRocketConfig extends Config( + new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$ + new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2 + new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, sits between L1D$ and L2, monitors L1D$ misses to prefetch into L2 + new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus + new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++ // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new chipyard.config.AbstractConfig)