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Support using HarnessBinders without IOBinders

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This commit is contained in:
Jerry Zhao
2023-10-25 11:49:16 -07:00
parent f80426ef9d
commit a5597fd32f
13 changed files with 38 additions and 17 deletions
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1
fpga/src/main/scala/arty/TestHarness.scala
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@@ -9,7 +9,6 @@ import org.chipsalliance.cde.config.{Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.harness.{HasHarnessInstantiators}
import chipyard.iobinders.{HasIOBinders}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
// Convert harness resets from Bool to Reset type.

1
fpga/src/main/scala/arty100t/Harness.scala
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@@ -17,7 +17,6 @@ import sifive.blocks.devices.uart._
import chipyard._
import chipyard.harness._
import chipyard.iobinders.{HasIOBinders}
class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell {
def dp = designParameters

1
fpga/src/main/scala/nexysvideo/Harness.scala
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@@ -16,7 +16,6 @@ import sifive.blocks.devices.uart._
import chipyard._
import chipyard.harness._
import chipyard.iobinders.{HasIOBinders}
class NexysVideoHarness(override implicit val p: Parameters) extends NexysVideoShell {
def dp = designParameters

1
fpga/src/main/scala/vc707/TestHarness.scala
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@@ -18,7 +18,6 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import chipyard._
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness._
class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer =>

1
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -18,7 +18,6 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import chipyard._
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness._
class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays {