From a5385c0a54d9291ba0ec444c58042fdcc387ee98 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 10 Sep 2020 23:20:37 -0700 Subject: [PATCH] Update testchipip/icenet to use rocket-chip Located API --- .../chipyard/src/main/scala/DigitalTop.scala | 2 - .../src/main/scala/HarnessBinders.scala | 28 ++++++----- .../chipyard/src/main/scala/IOBinders.scala | 48 +++++++++---------- .../src/main/scala/BridgeBinders.scala | 14 +++--- .../src/main/scala/TargetConfigs.scala | 2 +- generators/icenet | 2 +- generators/testchipip | 2 +- 7 files changed, 49 insertions(+), 49 deletions(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index ddcf66f3..a065b6be 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -32,11 +32,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with testchipip.CanHaveTraceIOModuleImp - with testchipip.CanHavePeripheryBlockDeviceModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp - with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 90365b39..06a3af5d 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -20,10 +20,10 @@ import barstools.iocell.chisel._ import testchipip._ import chipyard.HasHarnessSignalReferences -import chipyard.iobinders.ClockedIO +import chipyard.iobinders.GetSystemParameters import tracegen.{TraceGenSystemModuleImp} -import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly} +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import scala.reflect.{ClassTag} @@ -89,24 +89,27 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder }) class WithSimBlockDevice extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { - ports.map { p => SimBlockDevice.connect(p.clock, th.harnessReset.asBool, Some(p.bits))(system.p) } + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + implicit val p: Parameters = GetSystemParameters(system) + ports.map { b => SimBlockDevice.connect(b.clock, th.harnessReset.asBool, Some(b.bits)) } Nil } }) class WithBlockDeviceModel extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { - ports.map { p => withClockAndReset(p.clock, th.harnessReset) { BlockDeviceModel.connect(Some(p.bits))(system.p) } } + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + implicit val p: Parameters = GetSystemParameters(system) + ports.map { b => withClockAndReset(b.clock, th.harnessReset) { BlockDeviceModel.connect(Some(b.bits)) } } Nil } }) class WithLoopbackNIC extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { - ports.map { p => - withClockAndReset(p.clock, th.harnessReset) { - NicLoopback.connect(Some(p.bits), system.p(NICKey)) + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + implicit val p: Parameters = GetSystemParameters(system) + ports.map { n => + withClockAndReset(n.clock, th.harnessReset) { + NicLoopback.connect(Some(n.bits), p(NICKey)) } } Nil @@ -114,8 +117,9 @@ class WithLoopbackNIC extends OverrideHarnessBinder({ }) class WithSimNetwork extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { - ports.map { p => SimNetwork.connect(Some(p.bits), p.clock, th.harnessReset.asBool) } + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + implicit val p: Parameters = GetSystemParameters(system) + ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.harnessReset.asBool) } Nil } }) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 969ad571..78233118 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -4,7 +4,7 @@ import chisel3._ import chisel3.util.experimental.{BoringUtils} import chisel3.experimental.{Analog, IO, DataMirror} -import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.config._ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} @@ -22,7 +22,7 @@ import tracegen.{TraceGenSystemModuleImp} import barstools.iocell.chisel._ import testchipip._ -import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly} +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.GlobalResetSchemeKey @@ -43,15 +43,15 @@ import scala.reflect.{ClassTag} case object IOBinders extends Field[Map[String, (Any) => (Seq[Data], Seq[IOCell])]]( Map[String, (Any) => (Seq[Data], Seq[IOCell])]().withDefaultValue((Any) => (Nil, Nil)) ) - object ApplyIOBinders { def apply(sys: LazyModule, map: Map[String, (Any) => (Seq[Data], Seq[IOCell])]): (Iterable[Data], Iterable[IOCell], Map[String, Seq[Data]]) = { val lzy = map.map({ case (s,f) => s -> f(sys) }) val imp = map.map({ case (s,f) => s -> f(sys.module) }) + val unzipped = (lzy.values ++ imp.values).unzip - val ports: Iterable[Data] = lzy.values.map(_._1).flatten ++ imp.values.map(_._1).flatten - val cells: Iterable[IOCell] = lzy.values.map(_._2).flatten ++ imp.values.map(_._2).flatten + val ports: Iterable[Data] = unzipped._1.flatten + val cells: Iterable[IOCell] = unzipped._2.flatten val portMap: Map[String, Seq[Data]] = map.keys.map(k => k -> (lzy(k)._1 ++ imp(k)._1)).toMap (ports, cells, portMap) } @@ -72,13 +72,17 @@ object GetSystemParameters { } } +class IOBinder(f: (View, View, View) => PartialFunction[Any, Any]) extends Config(f) + // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((t: Any) => { t match { - case system: T => fn(system) + case system: T => + val (ports, cells) = fn(system) + (ports, cells) case _ => (Nil, Nil) } }) @@ -87,14 +91,16 @@ class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implic // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends IOBinder((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((t: Any) => { t match { case system: T => val r = up(IOBinders, site)(tag.runtimeClass.toString)(system) val h = fn(system) - (r._1 ++ h._1, r._2 ++ h._2) + val ports = r._1 ++ h._1 + val cells = r._2 ++ h._2 + (ports, cells) case _ => (Nil, Nil) } }) @@ -116,11 +122,6 @@ object BoreHelper { case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams()) -class ClockedIO[T <: Data](gen: T) extends Bundle { - val clock = Output(Clock()) - val bits = gen - override def cloneType: this.type = (new ClockedIO(DataMirror.internal.chiselTypeClone[T](gen))).asInstanceOf[this.type] -} class WithGPIOCells extends OverrideIOBinder({ (system: HasPeripheryGPIOModuleImp) => { @@ -252,10 +253,7 @@ class WithDebugIOCells extends OverrideIOBinder({ class WithSerialIOCells extends OverrideIOBinder({ (system: CanHavePeripherySerial) => system.serial.map({ s => val sys = system.asInstanceOf[BaseSubsystem] - val clocked_serial = Wire(new ClockedIO(DataMirror.internal.chiselTypeClone[SerialIO](s))).suggestName("serial_wire") - clocked_serial.clock := BoreHelper("serial_clock", sys.fbus.module.clock) - clocked_serial.bits <> s - val (port, cells) = IOCell.generateIOFromSignal(clocked_serial, Some("serial"), sys.p(IOCellKey)) + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial"), sys.p(IOCellKey)) port.suggestName("serial") (Seq(port), cells) }).getOrElse((Nil, Nil)) @@ -299,11 +297,10 @@ class WithL2FBusAXI4Punchthrough extends OverrideIOBinder({ }) class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => { + (system: CanHavePeripheryBlockDevice) => { val ports: Seq[ClockedIO[BlockDeviceIO]] = system.bdev.map({ bdev => - val p = IO(new ClockedIO(new BlockDeviceIO()(system.p))).suggestName("blockdev") - p.clock := BoreHelper("blkdev_clk", system.outer.controller.get.module.clock) - p.bits <> bdev + val p = IO(new ClockedIO(new BlockDeviceIO()(GetSystemParameters(system)))).suggestName("blockdev") + p <> bdev p }).toSeq (ports, Nil) @@ -311,11 +308,10 @@ class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({ }) class WithNICIOPunchthrough extends OverrideIOBinder({ - (system: CanHavePeripheryIceNICModuleImp) => { - val ports: Seq[ClockedIO[NICIOvonly]] = system.net.map({ n => + (system: CanHavePeripheryIceNIC) => { + val ports: Seq[ClockedIO[NICIOvonly]] = system.icenicOpt.map({ n => val p = IO(new ClockedIO(new NICIOvonly)).suggestName("nic") - p.clock := BoreHelper("nic_clk", system.outer.icenicOpt.get.module.clock) - p.bits <> n + p <> n p }).toSeq (ports, Nil) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 5dcddcfa..f42a1adf 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart._ import testchipip._ -import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly} +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import junctions.{NastiKey, NastiParameters} import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} @@ -26,7 +26,7 @@ import ariane.ArianeTile import boom.common.{BoomTile} import barstools.iocell.chisel._ -import chipyard.iobinders.{ClockedIO, IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey} +import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey} import chipyard.{HasHarnessSignalReferences} import chipyard.harness._ @@ -67,8 +67,9 @@ class WithSerialBridge extends OverrideHarnessBinder({ }) class WithNICBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { - ports.map { p => withClockAndReset(p.clock, th.harnessReset) { NICBridge(p.clock, p.bits)(system.p) } } + (system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => { + val p: Parameters = GetSystemParameters(system) + ports.map { n => withClockAndReset(n.clock, th.harnessReset) { NICBridge(n.clock, n.bits)(p) } } Nil } }) @@ -79,8 +80,9 @@ class WithUARTBridge extends OverrideHarnessBinder({ }) class WithBlockDeviceBridge extends OverrideHarnessBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { - ports.map { p => BlockDevBridge(p.clock, p.bits, th.harnessReset.toBool)(system.p) } + (system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => { + implicit val p: Parameters = GetSystemParameters(system) + ports.map { b => BlockDevBridge(b.clock, b.bits, th.harnessReset.toBool) } Nil } }) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 0d8cd367..2dede960 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} import freechips.rocketchip.diplomacy.LazyModule -import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams} +import testchipip.{BlockDeviceKey, BlockDeviceConfig, TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} diff --git a/generators/icenet b/generators/icenet index bb23c81f..277a9080 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit bb23c81fcfbdfde6767c5b7daa95f8f9436fb7db +Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 diff --git a/generators/testchipip b/generators/testchipip index 6f4e7ae2..70df93e5 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6f4e7ae2c94e867f08cd0d408a106fba2f389de2 +Subproject commit 70df93e5867e6676e62bb23b11b9086471fdecf7