From cb24357a8abcf094e324f2d2e189a7cea50b48da Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 8 Jun 2023 10:52:49 -0700 Subject: [PATCH 1/9] Ignore barstools compilation if not needed --- common.mk | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/common.mk b/common.mk index 9bb2f94c..981d9f4a 100644 --- a/common.mk +++ b/common.mk @@ -68,7 +68,7 @@ include $(base_dir)/tools/torture.mk ######################################################################################### # Prerequisite lists ######################################################################################### -# Returns a list of files in directory $1 with file extension $2. +# Returns a list of files in directories $1 with single file extension $2. # If available, use 'fd' to find the list of files, which is faster than 'find'. ifeq ($(shell which fd 2> /dev/null),) lookup_srcs = $(shell find -L $(1)/ -name target -prune -o \( -iname "*.$(2)" ! -iname ".*" \) -print 2> /dev/null) @@ -76,9 +76,17 @@ else lookup_srcs = $(shell fd -L -t f -e $(2) . $(1)) endif -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools fpga/fpga-shells fpga/src) -SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) -VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) +# Returns a list of files in directories $1 with *any* of the file extensions in $2 +lookup_srcs_by_multiple_type = $(foreach type,$(2),$(call lookup_srcs,$(1),$(type))) + +SCALA_EXT = scala +VLOG_EXT = sv v +CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src) +CHIPYARD_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(SCALA_EXT)) +CHIPYARD_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(VLOG_EXT)) +BARSTOOLS_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/barstools) +BARSTOOLS_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(SCALA_EXT)) +BARSTOOLS_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(VLOG_EXT)) # This assumes no SBT meta-build sources SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties @@ -106,12 +114,12 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip ######################################################################################### # compile scala jars ######################################################################################### -$(CHIPYARD_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) +$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) mkdir -p $(dir $@) $(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH)) # order only dependency between sbt runs needed to avoid concurrent sbt runs -$(TAPEOUT_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(CHIPYARD_CLASSPATH_TARGETS) +$(TAPEOUT_CLASSPATH_TARGETS) &: $(BARSTOOLS_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(CHIPYARD_CLASSPATH_TARGETS) mkdir -p $(dir $@) $(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH)) @@ -206,13 +214,13 @@ else echo "$(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays" > $@ endif -$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LEVEL) +$(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(SFC_LEVEL) if [ $(shell cat $(SFC_LEVEL)) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $@; fi if [ $(shell cat $(SFC_LEVEL)) = none ]; then cat $(EXTRA_ANNO_FILE) > $@; fi touch $@ $(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX) -$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) +$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) $(CHIPYARD_VLOG_SOURCES) $(BARSTOOLS_VLOG_SOURCES) rm -rf $(GEN_COLLATERAL_DIR) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\ --no-dedup \ From 5ccd2b8bb4182c51ed2fed11ac4c0aac2323ce55 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 8 Jun 2023 13:42:09 -0700 Subject: [PATCH 2/9] Fix parallelism issue --- common.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/common.mk b/common.mk index 981d9f4a..7e0f664b 100644 --- a/common.mk +++ b/common.mk @@ -208,6 +208,7 @@ else endif $(MFC_LOWERING_OPTIONS): + mkdir -p $(dir $@) ifeq (,$(ENABLE_YOSYS_FLOW)) echo "$(MFC_BASE_LOWERING_OPTIONS)" > $@ else From a403736e6211bde806987e0f2855249424398040 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 9 Jun 2023 11:24:41 -0700 Subject: [PATCH 3/9] Disable NVDLA simulations in CI --- .github/scripts/defaults.sh | 2 +- .github/workflows/chipyard-run-tests.yml | 47 ++++++++++++------------ 2 files changed, 24 insertions(+), 25 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 1c1b7def..8d9e30c6 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -44,7 +44,7 @@ mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig" mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig" -mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" +mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig verilog" mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig" mapping["chipyard-dmiboom"]=" CONFIG=dmiMediumBoomCosimConfig" diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 02de6935..05fc617e 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -741,28 +741,28 @@ jobs: group-key: "group-accels" project-key: "chipyard-manymmioaccels" - chipyard-nvdla-run-tests: - name: chipyard-nvdla-run-tests - needs: prepare-chipyard-accels - runs-on: self-hosted - steps: - - name: Delete old checkout - run: | - ls -alh . - rm -rf ${{ github.workspace }}/* || true - rm -rf ${{ github.workspace }}/.* || true - ls -alh . - - name: Checkout - uses: actions/checkout@v3 - - name: Git workaround - uses: ./.github/actions/git-workaround - - name: Create conda env - uses: ./.github/actions/create-conda-env - - name: Run tests - uses: ./.github/actions/run-tests - with: - group-key: "group-accels" - project-key: "chipyard-nvdla" + # chipyard-nvdla-run-tests: + # name: chipyard-nvdla-run-tests + # needs: prepare-chipyard-accels + # runs-on: self-hosted + # steps: + # - name: Delete old checkout + # run: | + # ls -alh . + # rm -rf ${{ github.workspace }}/* || true + # rm -rf ${{ github.workspace }}/.* || true + # ls -alh . + # - name: Checkout + # uses: actions/checkout@v3 + # - name: Git workaround + # uses: ./.github/actions/git-workaround + # - name: Create conda env + # uses: ./.github/actions/create-conda-env + # - name: Run tests + # uses: ./.github/actions/run-tests + # with: + # group-key: "group-accels" + # project-key: "chipyard-nvdla" chipyard-mempress-run-tests: name: chipyard-mempress-run-tests @@ -1035,8 +1035,7 @@ jobs: chipyard-manyperipherals-run-tests, chipyard-sha3-run-tests, chipyard-gemmini-run-tests, - chipyard-manymmioaccels-run-tests, - chipyard-nvdla-run-tests, + chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, chipyard-mempress-run-tests, chipyard-constellation-run-tests, tracegen-boom-run-tests, From 486176999ef6711eca2cc08103c713196f1fed90 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 10 Jun 2023 22:32:03 -0700 Subject: [PATCH 4/9] Update NoC example config to match new PRCI organization --- generators/chipyard/src/main/scala/config/NoCConfigs.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index 0036e988..0b6be558 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -68,9 +68,9 @@ class MultiNoCConfig extends Config( "serial-tl" -> 0), outNodeMapping = ListMap( "error" -> 1, "l2[0]" -> 2, "pbus" -> 3, "plic" -> 4, - "clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "tileClockGater" -> 8, "tileResetSetter" -> 9)), + "clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)), NoCParams( - topology = TerminalRouter(BidirectionalLine(10)), + topology = TerminalRouter(BidirectionalLine(9)), channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }), routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1)) )) ++ From 22889212db915e77a7b3ad3ba766b45d900b6e1a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 8 Jun 2023 13:40:55 -0700 Subject: [PATCH 5/9] Add barf submodule --- .gitmodules | 3 +++ generators/bar-fetchers | 1 + 2 files changed, 4 insertions(+) create mode 160000 generators/bar-fetchers diff --git a/.gitmodules b/.gitmodules index 5a3eb6fc..2a4bbac3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -124,3 +124,6 @@ [submodule "software/embench/embench-iot"] path = software/embench/embench-iot url = https://github.com/embench/embench-iot.git +[submodule "generators/bar-fetchers"] + path = generators/bar-fetchers + url = https://github.com/ucb-bar/bar-fetchers.git diff --git a/generators/bar-fetchers b/generators/bar-fetchers new file mode 160000 index 00000000..e1a16ff9 --- /dev/null +++ b/generators/bar-fetchers @@ -0,0 +1 @@ +Subproject commit e1a16ff9834aafe805ec4a113b7dd5ce7ddd905b From 5e893ea77c3a6698b700d8e38d5eecf3d309d878 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 8 Jun 2023 14:16:38 -0700 Subject: [PATCH 6/9] Add prefetching rocket example config --- build.sbt | 7 ++++++- .../src/main/scala/config/RocketConfigs.scala | 8 ++++++++ .../scala/config/fragments/TileFragments.scala | 17 +++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 6f72940a..0fbdd747 100644 --- a/build.sbt +++ b/build.sbt @@ -153,7 +153,7 @@ lazy val chipyard = (project in file("generators/chipyard")) sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress) + constellation, mempress, barf) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -168,6 +168,11 @@ lazy val mempress = (project in file("generators/mempress")) .settings(chiselTestSettings) .settings(commonSettings) +lazy val barf = (project in file("generators/bar-fetchers")) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val constellation = (project in file("generators/constellation")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 21b630cc..f71b6ea7 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -126,3 +126,11 @@ class CustomIOChipTopRocketConfig extends Config( new chipyard.example.WithCustomIOCells ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) + +class PrefetchingRocketConfig extends Config( + new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher into L1D$ + new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher into L2 for L1I$ accesses + new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher into L2 for L1D$ accesses + new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index 56042c3d..17eaa3f0 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -9,7 +9,10 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import boom.common.{BoomTileAttachParams} import cva6.{CVA6TileAttachParams} +import sodor.common.{SodorTileAttachParams} +import ibex.{IbexTileAttachParams} import testchipip._ +import barf.{TilePrefetchingMasterPortParams} class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { @@ -79,3 +82,17 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { } }) +class WithTilePrefetchers extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( + master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + } +}) From 7cbabaa18abbf65811b9a650a5f0dc904f8a4e76 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 8 Jun 2023 14:21:26 -0700 Subject: [PATCH 7/9] Add CI on PrefetchingRocketConfig --- .github/scripts/check-commit.sh | 2 +- .github/scripts/defaults.sh | 3 ++- .github/scripts/run-tests.sh | 3 +++ .github/workflows/chipyard-run-tests.yml | 24 ++++++++++++++++++++++++ 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index fe1de2bf..031c9c0a 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,7 +45,7 @@ search () { done } -submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress") +submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers") dir="generators" branches=("master" "main" "dev") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 8d9e30c6..dbcc1528 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -28,7 +28,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone" +grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike" grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla" grouping["group-constellation"]="chipyard-constellation" @@ -42,6 +42,7 @@ mapping["chipyard-rocket"]=" CONFIG=QuadChannelRocketConfig" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig" +mapping["chipyard-prefetchers"]=" CONFIG=PrefetchingRocketConfig" mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig verilog" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 4a5a0802..a878eb36 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -56,6 +56,9 @@ case $1 in chipyard-hetero) run_bmark ${mapping[$1]} ;; + chipyard-prefetchers) + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv + ;; rocketchip) run_bmark ${mapping[$1]} ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 05fc617e..fdcbd51e 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -442,6 +442,29 @@ jobs: group-key: "group-cores" project-key: "chipyard-rocket" + chipyard-prefetchers-run-tests: + name: chipyard-prefetchers-run-tests + needs: prepare-chipyard-cores + runs-on: self-hosted + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-cores" + project-key: "chipyard-prefetchers" + chipyard-hetero-run-tests: name: chipyard-hetero-run-tests needs: prepare-chipyard-cores @@ -1036,6 +1059,7 @@ jobs: chipyard-sha3-run-tests, chipyard-gemmini-run-tests, chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, + chipyard-prefetchers-run-tests, chipyard-mempress-run-tests, chipyard-constellation-run-tests, tracegen-boom-run-tests, From 903971f32ff2eff3f5e9a83920b0bd1001ec5d66 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 8 Jun 2023 14:24:34 -0700 Subject: [PATCH 8/9] Add documentation page indicating existence of prefetchers --- docs/Generators/Prefetchers.rst | 9 +++++++++ docs/Generators/index.rst | 1 + .../chipyard/src/main/scala/config/RocketConfigs.scala | 6 +++--- scripts/tutorial-patches/build.sbt.patch | 2 +- 4 files changed, 14 insertions(+), 4 deletions(-) create mode 100644 docs/Generators/Prefetchers.rst diff --git a/docs/Generators/Prefetchers.rst b/docs/Generators/Prefetchers.rst new file mode 100644 index 00000000..550d22e7 --- /dev/null +++ b/docs/Generators/Prefetchers.rst @@ -0,0 +1,9 @@ +Prefetchers +==================================== + +The BAR-fetchers library is a collection of Chisel-implemented prefetchers, designed for compatibility with Chipyard and Rocket-Chip SoCs. +This package implements a generic prefetcher API, and example implementations of NextLine, Strided, and AMPM prefetchers. + +Prefetchers can be instantiated in front of a L1D HellaCache, or as TileLink nodes in front of some TileLink bus. + +An example configuration using prefetchers is found in the ``PrefetchingRocketConfig`` diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index cb8cdc47..b8f5df1b 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -34,3 +34,4 @@ so changes to the generators themselves will automatically be used when building NVDLA Sodor Mempress + Prefetchers diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index f71b6ea7..1c3884bc 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -128,9 +128,9 @@ class CustomIOChipTopRocketConfig extends Config( new chipyard.config.AbstractConfig) class PrefetchingRocketConfig extends Config( - new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher into L1D$ - new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher into L2 for L1I$ accesses - new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher into L2 for L1D$ accesses + new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$ + new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2 + new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, site between L1D$ and L2, monitors L1D$ misses to prefetch into L2 new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index db81b052..dee7fcf5 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -10,7 +10,7 @@ index ec36a85f..c0c2849a 100644 +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress) + constellation, mempress, barf) @@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) From 7b05dd199d3e6ebdfacf4163d0823a1eea019e0b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 12 Jun 2023 16:26:00 -0700 Subject: [PATCH 9/9] Prefetching config should use non-blocking L1D$ --- generators/bar-fetchers | 2 +- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/bar-fetchers b/generators/bar-fetchers index e1a16ff9..3a33d818 160000 --- a/generators/bar-fetchers +++ b/generators/bar-fetchers @@ -1 +1 @@ -Subproject commit e1a16ff9834aafe805ec4a113b7dd5ce7ddd905b +Subproject commit 3a33d818aefe5444aa27fc1557008f747538d2cc diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 1c3884bc..95c2cbae 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -130,7 +130,8 @@ class CustomIOChipTopRocketConfig extends Config( class PrefetchingRocketConfig extends Config( new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$ new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2 - new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, site between L1D$ and L2, monitors L1D$ misses to prefetch into L2 + new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, sits between L1D$ and L2, monitors L1D$ misses to prefetch into L2 new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus + new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++ // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig)