First attempt at getting Offchip AXI port

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -103,6 +103,34 @@ class WithBlockDeviceBridge extends OverrideHarnessBinder({
   }
 })
 
+class WithOffchipNetworkSerialAXIBridge extends OverrideHarnessBinder({
+  (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedAndResetIO[ClockedIO[SerialIO]]]) => {
+    implicit val p = GetSystemParameters(system)
+
+    ports.map({ port =>
+      val offchipNetwork = SerialAdapter.connectOffChipNetwork(system.serdesser.get, port, th.harnessReset)
+      SerialBridge(port.bits.clock, offchipNetwork.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
+
+      // connect SimAxiMem
+      (offchipNetwork.mem_axi4 zip offchipNetwork.memAXI4Node.edges.in).map { case (axi4, edge) =>
+        val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
+                                      axi4.ar.bits.addr.getWidth,
+                                      axi4.ar.bits.id.getWidth)
+        system match {
+          case s: BaseSubsystem => FASEDBridge(port.clock, axi4, port.reset.asBool,
+            CompleteConfig(p(firesim.configs.MemModelKey),
+                          nastiKey,
+                          Some(AXI4EdgeSummary(edge)),
+                          Some(MainMemoryConsts.globalName)))
+          case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design")
+        }
+      }
+    })
+
+    Nil
+  }
+})
+
 class WithFASEDBridge extends OverrideHarnessBinder({
   (system: CanHaveMasterAXI4MemPort, th: FireSim, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
     implicit val p: Parameters = GetSystemParameters(system)

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -215,3 +215,58 @@ class FireSim16LargeBoomConfig extends Config(
   new WithFireSimConfigTweaks ++
   new boom.common.WithNLargeBooms(16) ++
   new chipyard.config.AbstractConfig)
+
+class WithOffchipAXINoClksSetup(pbusFreqMHz: BigInt = 3200) extends Config(
+  // normal bridges + new offchip bridge
+  new WithNICBridge ++
+  new WithUARTBridge ++
+  new WithBlockDeviceBridge ++
+  new WithOffchipNetworkSerialAXIBridge ++ // NEW BRIDGE COMBINING SERIAL/AXI
+  new WithFireSimMultiCycleRegfile ++
+  new WithFireSimFAME5 ++
+  //new WithTracerVBridge ++
+  new WithFireSimIOCellModels ++
+
+  // new tweaks
+  // Required: Bake in the default FASED memory model
+  new WithDefaultMemModel ++
+  // Required*: Uses FireSim ClockBridge and PeekPokeBridge to drive the system with a single clock/reset
+  new WithFireSimSimpleClocks ++
+  // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
+  new WithBootROM ++
+  // Required: Existing FAME-1 transform cannot handle black-box clock gates
+  new WithoutClockGating ++
+  // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix)
+  new WithoutTLMonitors ++
+  // Optional: Adds IO to attach tracerV bridges
+  //new chipyard.config.WithTraceIO ++
+  // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
+  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
+  // Optional: Removing this will require using an initramfs under linux
+  new testchipip.WithBlockDevice ++
+  // Required*: Scale default baud rate with periphery bus frequency
+  // Rough math...
+  // NEW:
+  //   pbus @ 500MHz.... baud @ 576000 = 115200 * 5 (somehow the default was 100M)
+  // OLD: pbus @ 3200MHz, HW baud @ 3686400L AKA 115200 * 32
+  // OLD: Linux @ 115200, SBI @ 115200
+  // scale down to 100MHz before multipling up
+  new chipyard.config.WithUART((pbusFreqMHz / 100) * BigInt(115200L)) ++
+  // Required: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock)
+  new chipyard.config.WithNoDebug
+)
+
+class FireSimDebugOffchipConfig extends Config(
+  new WithOffchipAXINoClksSetup(3200) ++
+  new chipyard.DebugOffchipConfig
+)
+
+class FireSimDebugOffchip2Config extends Config(
+  new WithOffchipAXINoClksSetup(3200) ++
+  new chipyard.DebugOffchip2Config
+)
+
+class FireSimDebugOffchip3Config extends Config(
+  new WithOffchipAXINoClksSetup(4000) ++
+  new chipyard.DebugOffchip3Config
+)