Merge remote-tracking branch 'origin/dev' into add-hwacha-tests

CHANGELOG.md

@@ -0,0 +1,3 @@
+[1.0.0] - 2019-10-11
+Added
+This repository used to be "project-template", a template for Chisel-based projects. Through tighter integration of multiple projects from the Berkeley Architecture Research group at UC Berkeley, this repository is re-released as Chipyard - a framework for agile hardware development of RISC-V based Systems-on-Chip.

CONTRIBUTING.md

@@ -0,0 +1,8 @@
+Contributing to Chipyard
+=============================
+
+### Branch management:
+
+1) github:com/ucb-bar/chipyard: master = stable release. All merges to master must go through PR.
+2) github:com/ucb-bar/chipyard: dev = pre-release non-stable branch with latest features. All merges to dev must go through PR.
+3) Other dependencies pointed at by Chipyard (e.g. firesim, boom): master should be the version submoduled in ucb-bar/chipyard master.

LICENSE

@@ -1,4 +1,4 @@
-Copyright (c) 2017, The Regents of the University of California (Regents).
+Copyright (c) 2017-2019, The Regents of the University of California (Regents).
 All Rights Reserved.
 
 Redistribution and use in source and binary forms, with or without

README.md

@@ -1,22 +1,34 @@
-![CHIPYARD](https://raw.githubusercontent.com/ucb-bar/chipyard/dev/docs/_static/images/chipyard_logo.svg?sanitize=true)
+![CHIPYARD](https://github.com/ucb-bar/chipyard/raw/alon-docs-dev/docs/_static/images/chipyard-logo-full.png)
 
 # Chipyard Framework [![CircleCI](https://circleci.com/gh/ucb-bar/chipyard/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/chipyard/tree/master)
 
 ## Using Chipyard
 
-To get started using Chipyard, see the documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/en/latest/
+To get started using Chipyard, see the documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/
 
 ## What is Chipyard
 
-Chipyard is an open source starter template for your custom Chisel project.
+Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
 It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
-It contains processor cores ([Rocket][rocket-chip], [BOOM][boom]), accelerators ([Hwacha][hwacha]), FPGA simulation tools ([FireSim][firesim]), ASIC tools ([HAMMER][hammer]) and other tooling to help create a full featured SoC.
+Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom]), accelerators ([Hwacha][hwacha]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
+Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
 Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
 
 ## Resources
 
-* Chipyard Website: ...TBD at a later date...
 * Chipyard Documentation: https://chipyard.readthedocs.io/
+* Chipyard Basics slides: https://fires.im/micro19-slides-pdf/02_chipyard_basics.pdf 
+* Chipyard Tutorial Exercise slides: https://fires.im/micro19-slides-pdf/03_building_custom_socs.pdf
+
+## Need help?
+
+* Join the Chipyard Mailing List: https://groups.google.com/forum/#!forum/chipyard
+* If you find a bug, post an issue on this repo
+
+## Contributing
+
+* See [CONTRIBUTING.md](/CONTRIBUTING.md)
+
 
 [hwacha]:http://hwacha.org
 [hammer]:https://github.com/ucb-bar/hammer
@@ -27,3 +39,4 @@ Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb
 [riscv]: https://riscv.org/
 [rocket-chip]: https://github.com/freechipsproject/rocket-chip
 [boom]: https://github.com/ucb-bar/riscv-boom
+[firemarshal]: https://github.com/firesim/FireMarshal/

docs/Chipyard-Basics/Development-Ecosystem.rst

@@ -11,7 +11,7 @@ Chipyard aims to be the "one-stop shop" for creating and testing your own unique
 Chisel/FIRRTL
 -------------------------------------------
 
-One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language <https://chisel.eecs.berkeley.edu/>`__ and the `FIRRTL Compiler <https://freechipsproject.github.io/firrtl/>`__.
+One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language <https://chisel-lang.org/>`__ and the `FIRRTL Compiler <https://chisel-lang.org/firrtl/>`__.
 Chisel is an embedded language within Scala that provides a set of libraries to help hardware designers create highly parameterizable RTL.
 FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more!
 These two tools in combination allow quick design space exploration and development of new RTL.

docs/Tools/Chisel.rst

@@ -1,7 +1,7 @@
 Chisel
 ===========================
 
-`Chisel <https://chisel.eecs.berkeley.edu/>`__ is an open-source hardware description language embedded in Scala.
+`Chisel <https://chisel-lang.org/>`__ is an open-source hardware description language embedded in Scala.
 It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM.
 
 After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog.
@@ -16,4 +16,4 @@ However, if that passes, the output of the generator gives you an FIRRTL file an
 See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog.
 
 For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp <https://github.com/freechipsproject/chisel-bootcamp>`__.
-Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel.eecs.berkeley.edu/>`__.
+Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel-lang.org/>`__.

docs/Tools/FIRRTL.rst

@@ -8,6 +8,4 @@ Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (ano
 An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
 Once the transformations are done, a Verilog file is emitted and the build process is done.
 
-For more information on please visit their `website <https://freechipsproject.github.io/firrtl/>`__.
+For more information on please visit their `website <https://chisel-lang.org/firrtl/>`__.
-
-

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -132,9 +132,9 @@ abstract class FireSimTestSuite(
 }
 
 class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config")
-class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
+class BoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
 class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimRocketChipConfig", "BaseF1Config") {
   runSuite("verilator")(NICLoopbackTests)
 }
 class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")
-class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")
+class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")