Rename Ariane to CVA6

.circleci/check-commit.sh

@@ -48,7 +48,7 @@ search () {
     done
 }
 
-submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
+submodules=("cva6" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
 dir="generators"
 if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ]
 then

.circleci/config.yml

@@ -234,12 +234,12 @@ jobs:
             - run-tests:
                 group-key: "group-cores"
                 project-key: "chipyard-boom"
-    chipyard-ariane-run-tests:
+    chipyard-cva6-run-tests:
         executor: main-env
         steps:
             - run-tests:
                 group-key: "group-cores"
-                project-key: "chipyard-ariane"
+                project-key: "chipyard-cva6"
                 timeout: "30m"
     chipyard-sodor-run-tests:
         executor: main-env
@@ -431,7 +431,7 @@ workflows:
             - chipyard-boom-run-tests:
                 requires:
                     - prepare-chipyard-cores
-            - chipyard-ariane-run-tests:
+            - chipyard-cva6-run-tests:
                 requires:
                     - prepare-chipyard-cores
             - chipyard-sodor-run-tests:

.circleci/defaults.sh

@@ -47,7 +47,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
 
 # key value store to get the build groups
 declare -A grouping
-grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop"
+grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop"
 grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
 grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
 grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -67,7 +67,7 @@ mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig"
 mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
 mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
 mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
-mapping["chipyard-ariane"]=" CONFIG=ArianeConfig"
+mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
 mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
 mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"

.circleci/run-tests.sh

@@ -91,7 +91,7 @@ case $1 in
     tracegen-boom)
         run_tracegen ${mapping[$1]}
         ;;
-    chipyard-ariane)
+    chipyard-cva6)
         make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv
         ;;
     chipyard-sodor)

.gitmodules

@@ -113,9 +113,9 @@
 [submodule "software/firemarshal"]
 	path = software/firemarshal
 	url = https://github.com/firesim/FireMarshal.git
-[submodule "generators/ariane"]
-	path = generators/ariane
-	url = https://github.com/ucb-bar/ariane-wrapper.git
+[submodule "generators/cva6"]
+	path = generators/cva6
+	url = git@github.com:ucb-bar/cva6-wrapper.git
 [submodule "tools/DRAMSim2"]
 	path = tools/DRAMSim2
 	url = https://github.com/firesim/DRAMSim2.git

README.md

@@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati
 
 Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
 It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
-Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
+Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
 Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
 Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
 
@@ -80,6 +80,6 @@ These additional publications cover many of the internal components used in Chip
 [rocket-chip]: https://github.com/freechipsproject/rocket-chip
 [boom]: https://github.com/riscv-boom/riscv-boom
 [firemarshal]: https://github.com/firesim/FireMarshal/
-[ariane]: https://github.com/pulp-platform/ariane/
+[cva6]: https://github.com/openhwgroup/cva6/
 [gemmini]: https://github.com/ucb-bar/gemmini
 [nvdla]: http://nvdla.org/

build.sbt

@@ -132,7 +132,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
   .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, `rocket-dsptools`,
-    gemmini, icenet, tracegen, ariane, nvdla, sodor)
+    gemmini, icenet, tracegen, cva6, nvdla, sodor)
   .settings(commonSettings)
 
 lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
@@ -154,7 +154,7 @@ lazy val boom = conditionalDependsOn(project in file("generators/boom"))
   .dependsOn(rocketchip)
   .settings(commonSettings)
 
-lazy val ariane = (project in file("generators/ariane"))
+lazy val cva6 = (project in file("generators/cva6"))
   .dependsOn(rocketchip)
   .settings(commonSettings)
 

common.mk

@@ -47,7 +47,7 @@ HELP_COMMANDS += \
 # include additional subproject make fragments
 # see HELP_COMPILATION_VARIABLES
 #########################################################################################
-include $(base_dir)/generators/ariane/ariane.mk
+include $(base_dir)/generators/cva6/cva6.mk
 include $(base_dir)/generators/tracegen/tracegen.mk
 include $(base_dir)/generators/nvdla/nvdla.mk
 include $(base_dir)/tools/dromajo/dromajo.mk
@@ -103,7 +103,7 @@ $(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala
 $(FIRRTL_FILE) $(ANNO_FILE): generator_temp
 	@echo "" > /dev/null
 
-# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile
+# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
 generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS)
 	mkdir -p $(build_dir)
 	$(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\

docs/Chipyard-Basics/Chipyard-Components.rst

@@ -20,9 +20,9 @@ Processor Cores
   An out-of-order RISC-V core.
   See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information.
 
-**Ariane Core**
+**CVA6 Core**
   An in-order RISC-V core written in System Verilog.
-  See :ref:`Ariane Core` for more information.
+  See :ref:`CVA6 Core` for more information.
 
 Accelerators
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

docs/Customization/Custom-Core.rst

@@ -296,6 +296,6 @@ Now you have finished all the steps to prepare your cores for Chipyard! To gener
 in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`.
 You can now run most desired workflows for the new config just as you would for the built-in cores (depending on the functionality your core supports).
 
-If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala``
-provides a concrete example of the Ariane core. Note that this particular example includes additional nuances with respect to the interaction of the AXI
+If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/CVA6Tile.scala``
+provides a concrete example of the CVA6 core. Note that this particular example includes additional nuances with respect to the interaction of the AXI
 interface with the memory coherency system.

docs/Generators/CVA6.rst

@@ -1,14 +1,14 @@
-Ariane Core
+CVA6 Core
 ====================================
 
-`Ariane <https://github.com/pulp-platform/ariane>`__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
-The `Ariane core` is wrapped in an `Ariane tile` so it can be used as a component within the `Rocket Chip SoC generator`.
+`CVA6 <https://github.com/openhwgroup/cva6>`__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
+The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
 The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
 
 .. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface).
 
-While the core itself is not a generator, we expose the same parameterization that the Ariane core provides (i.e. change branch prediction parameters).
+While the core itself is not a generator, we expose the same parameterization that the CVA6 core provides (i.e. change branch prediction parameters).
 
 .. Warning::  This target does not support Verilator simulation at this time. Please use VCS.
 
-For more information, please refer to the `GitHub repository <https://github.com/pulp-platform/ariane>`__.
+For more information, please refer to the `GitHub repository <https://github.com/openhwgroup/cva6>`__.

docs/Generators/index.rst

@@ -27,7 +27,7 @@ so changes to the generators themselves will automatically be used when building
    TestChipIP
    SiFive-Generators
    SHA3
-   Ariane
+   CVA6
    NVDLA
    Sodor
 

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -21,7 +21,7 @@ import hwacha.{Hwacha}
 import gemmini.{Gemmini, GemminiConfigs}
 
 import boom.common.{BoomTileAttachParams}
-import ariane.{ArianeTileAttachParams}
+import cva6.{CVA6TileAttachParams}
 
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
@@ -120,7 +120,7 @@ class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
-    case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
     case other => other
   }

generators/chipyard/src/main/scala/TestSuites.scala

@@ -7,9 +7,6 @@ import freechips.rocketchip.tile.{XLen, TileParams}
 import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
-import boom.common.{BoomTileAttachParams}
-import ariane.{ArianeTileAttachParams}
-
 /**
  * A set of pre-chosen regression tests
  */

generators/chipyard/src/main/scala/config/ArianeConfigs.scala

@@ -1,19 +0,0 @@
-package chipyard
-
-import chisel3._
-
-import freechips.rocketchip.config.{Config}
-
-// ---------------------
-// Ariane Configs
-// ---------------------
-
-class ArianeConfig extends Config(
-  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.config.AbstractConfig)
-
-class dmiArianeConfig extends Config(
-  new chipyard.harness.WithSerialAdapterTiedOff ++     // Tie off the serial port, override default instantiation of SimSerial
-  new chipyard.config.WithDMIDTM ++                    // have debug module expose a clocked DMI port
-  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/CVA6Configs.scala

@@ -0,0 +1,19 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// CVA6 Configs
+// ---------------------
+
+class CVA6Config extends Config(
+  new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
+  new chipyard.config.AbstractConfig)
+
+class dmiCVA6Config extends Config(
+  new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial
+  new chipyard.config.WithDMIDTM ++                // have debug module expose a clocked DMI port
+  new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -16,7 +16,7 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.amba.axi4._
 
-// Example parameter class copied from Ariane, not included in documentation but for compile check only
+// Example parameter class copied from CVA6, not included in documentation but for compile check only
 // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
 // out what parameters you need before you write the parameter class
 case class MyCoreParams(
@@ -164,7 +164,7 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
   //   val core = Module(new MyCoreBlackbox(params...))
   // (as described in the blackbox tutorial) and connect appropriate signals. See the blackbox tutorial
   // (link on the top of the page) for more info.
-  // You can look at https://github.com/ucb-bar/ariane-wrapper/blob/master/src/main/scala/ArianeTile.scala
+  // You can look at https://github.com/ucb-bar/cva6-wrapper/blob/master/src/main/scala/CVA6Tile.scala
   // for a Verilog example.
 
   // If your core is in Chisel, you can simply instantiate the top module here like other Chisel module

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -22,7 +22,7 @@ import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotatio
 import firesim.bridges._
 import firesim.configs.MemModelKey
 import tracegen.{TraceGenSystemModuleImp}
-import ariane.ArianeTile
+import cva6.CVA6Tile
 
 import boom.common.{BoomTile}
 import barstools.iocell.chisel._

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -188,13 +188,13 @@ class SupernodeFireSimRocketConfig extends Config(
   new FireSimRocketConfig)
 
 //**********************************************************************************
-//* Ariane Configurations
+//* CVA6 Configurations
 //*********************************************************************************/
-class FireSimArianeConfig extends Config(
+class FireSimCVA6Config extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks ++
-  new chipyard.ArianeConfig)
+  new chipyard.CVA6Config)
 
 //**********************************************************************************
 //* Multiclock Configurations

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -110,7 +110,7 @@ class RocketMulticlockF1Tests extends FireSimTestSuite(
   "FireSimMulticlockRocketConfig",
   "WithSynthAsserts_BaseF1Config")
 
-class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config")
+class CVA6F1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimCVA6Config", "BaseF1Config")
 
 // This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call.
 class CITests extends Suites(

scripts/tutorial-patches/build.sbt.patch

@@ -9,9 +9,9 @@ index 5d642c1..56f6fda 100644
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
      dsptools, `rocket-dsptools`,
-     gemmini, icenet, tracegen, ariane, nvdla, sodor)
+     gemmini, icenet, tracegen, cva6, nvdla, sodor)
    .settings(commonSettings)
-@@ -158,9 +158,9 @@ lazy val ariane = (project in file("generators/ariane"))
+@@ -158,9 +158,9 @@ lazy val cva6 = (project in file("generators/cva6"))
    .dependsOn(rocketchip)
    .settings(commonSettings)
 

sims/verilator/Makefile

@@ -91,7 +91,7 @@ VERILATOR_OPT_FLAGS := \
 	--output-split 10000 \
 	--output-split-cfuncs 100
 
-# default flags added for external IP (ariane/NVDLA)
+# default flags added for external IP (cva6/NVDLA)
 VERILOG_IP_VERILATOR_FLAGS := \
 	--unroll-count 256 \
 	-Wno-PINCONNECTEMPTY \
@@ -103,14 +103,14 @@ VERILOG_IP_VERILATOR_FLAGS := \
 	-Wno-style \
 	-Wall
 
-# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane/NVDLA)
+# normal flags used for chipyard builds (that are incompatible with vlog ip aka cva6/NVDLA)
 CHIPYARD_VERILATOR_FLAGS := \
 	--assert
 
-# options dependent on whether external IP (ariane/NVDLA) or just chipyard is used
+# options dependent on whether external IP (cva6/NVDLA) or just chipyard is used
 # NOTE: defer the evaluation of this until it is used!
 PLATFORM_OPTS = $(shell \
-	if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \
+	if grep -qiP "module\s+(CVA6|NVDLA)" $(build_dir)/*.*v; \
 	then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
 	else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)