revert module imp && fix for 4gb ram

fpga/src/main/scala/vc707/HarnessBinders.scala

@@ -1,6 +1,7 @@
 package chipyard.fpga.vc707
 
 import chisel3._
+import chisel3.experimental.{BaseModule}
 
 import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.tilelink.{TLBundle}
@@ -14,26 +15,32 @@ import chipyard.harness.{OverrideHarnessBinder}
 
 /*** UART ***/
 class WithVC707UARTHarnessBinder extends OverrideHarnessBinder({
-  (system: HasPeripheryUARTModuleImp, th: VC707FPGATestHarness, ports: Seq[UARTPortIO]) => {
+  (system: HasPeripheryUARTModuleImp, th: BaseModule, ports: Seq[UARTPortIO]) => {
-    th.io_uart_bb.bundle <> ports.head
+    th match { case vc707th: VC707FPGATestHarnessImp => {
+      vc707th.vc707Outer.io_uart_bb.bundle <> ports.head
+    }}
   }
 })
 
 /*** SPI ***/
 class WithVC707SPISDCardHarnessBinder extends OverrideHarnessBinder({
-  (system: HasPeripherySPI, th: VC707FPGATestHarness, ports: Seq[SPIPortIO]) => {
+  (system: HasPeripherySPI, th: BaseModule, ports: Seq[SPIPortIO]) => {
-    th.io_spi_bb.bundle <> ports.head
+    th match { case vc707th: VC707FPGATestHarnessImp => {
+      vc707th.vc707Outer.io_spi_bb.bundle <> ports.head
+    }}
   }
 })
 
 /*** Experimental DDR ***/
 class WithVC707DDRMemHarnessBinder extends OverrideHarnessBinder({
-  (system: CanHaveMasterTLMemPort, th: VC707FPGATestHarness, ports: Seq[HeterogeneousBag[TLBundle]]) => {
+  (system: CanHaveMasterTLMemPort, th: BaseModule, ports: Seq[HeterogeneousBag[TLBundle]]) => {
-    require(ports.size == 1)
+    th match { case vc707th: VC707FPGATestHarnessImp => {
+      require(ports.size == 1)
 
-    val bundles = th.ddrClient.out.map(_._1)
+      val bundles = vc707th.vc707Outer.ddrClient.out.map(_._1)
-    val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
+      val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
-    bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
+      bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
-    ddrClientBundle <> ports.head
+      ddrClientBundle <> ports.head
+    }}
   }
 })

fpga/src/main/scala/vc707/TestHarness.scala

@@ -26,8 +26,8 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
 
 
   // Order matters; ddr depends on sys_clock
-  val uart      = Overlay(UARTOverlayKey, new UARTVC707ShellPlacer(this, UARTShellInput()))
+  val uart = Overlay(UARTOverlayKey, new UARTVC707ShellPlacer(this, UARTShellInput()))
-  val pcie       = Overlay(PCIeOverlayKey, new PCIeVC707ShellPlacer(this, PCIeShellInput()))
+  val pcie = Overlay(PCIeOverlayKey, new PCIeVC707ShellPlacer(this, PCIeShellInput()))
 
   val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
 
@@ -63,8 +63,8 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
   dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb))
 
   /*** DDR ***/
-
+  // Modify the last field of `DDRDesignInput` for 1GB RAM size
-  val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr
+  val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL, true)).overlayOutput.ddr
 
   // connect 1 mem. channel to the FPGA DDR
   val inParams = topDesign match { case td: ChipTop =>
@@ -76,47 +76,52 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
   ddrNode := ddrClient
 
   // module implementation
-  override lazy val module = new LazyRawModuleImp(this) with HasHarnessSignalReferences {
+  override lazy val module = new VC707FPGATestHarnessImp(this)
-    val reset = IO(Input(Bool()))
+}
-    xdc.addBoardPin(reset, "reset")
 
-    val resetIBUF = Module(new IBUF)
+class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
-    resetIBUF.io.I := reset
+  
+  val vc707Outer = _outer
 
-    val sysclk: Clock = sysClkNode.out.head._1.clock
+  val reset = IO(Input(Bool()))
-    // val sysclk: Clock = sys_clock.get() match {
+  _outer.xdc.addBoardPin(reset, "reset")
-    //   case Some(x: SysClockVC707PlacedOverlay) => x.clock
-    // }
 
-    val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
+  val resetIBUF = Module(new IBUF)
-    sdc.addAsyncPath(Seq(powerOnReset))
+  resetIBUF.io.I := reset
 
-    val ereset: Bool = chiplink.get() match {
+  val sysclk: Clock = _outer.sysClkNode.out.head._1.clock
-      case Some(x: ChipLinkVC707PlacedOverlay) => !x.ereset_n
+  // val sysclk: Clock = sys_clock.get() match {
-      case _ => false.B
+  //   case Some(x: SysClockVC707PlacedOverlay) => x.clock
-    }
+  // }
 
-    pllReset := (resetIBUF.io.O || powerOnReset || ereset)
+  val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
+  _outer.sdc.addAsyncPath(Seq(powerOnReset))
 
-    // reset setup
+  val ereset: Bool = _outer.chiplink.get() match {
-    val hReset = Wire(Reset())
+    case Some(x: ChipLinkVC707PlacedOverlay) => !x.ereset_n
-    hReset := dutClock.in.head._1.reset
+    case _ => false.B
-
-    val buildtopClock = dutClock.in.head._1.clock
-    val buildtopReset = WireInit(hReset)
-    val dutReset = hReset.asAsyncReset
-    val success = false.B
-
-    childClock := buildtopClock
-    childReset := buildtopReset
-
-    // harness binders are non-lazy
-    topDesign match { case d: HasIOBinders =>
-      ApplyHarnessBinders(this, d.lazySystem, d.portMap)
-    }
-
-    // check the top-level reference clock is equal to the default
-    // non-exhaustive since you need all ChipTop clocks to equal the default
-    require(getRefClockFreq == p(DefaultClockFrequencyKey))
   }
+
+  _outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset)
+
+  // reset setup
+  val hReset = Wire(Reset())
+  hReset := _outer.dutClock.in.head._1.reset
+
+  val buildtopClock = _outer.dutClock.in.head._1.clock
+  val buildtopReset = WireInit(hReset)
+  val dutReset = hReset.asAsyncReset
+  val success = false.B
+
+  childClock := buildtopClock
+  childReset := buildtopReset
+
+  // harness binders are non-lazy
+  _outer.topDesign match { case d: HasIOBinders =>
+    ApplyHarnessBinders(this, d.lazySystem, d.portMap)
+  }
+
+  // check the top-level reference clock is equal to the default
+  // non-exhaustive since you need all ChipTop clocks to equal the default
+  require(getRefClockFreq == p(DefaultClockFrequencyKey))
 }