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Initialize cospike memory from SimDRAM memory

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This commit is contained in:
Jerry Zhao
2023-04-20 18:58:53 -07:00
parent 44ef2e3f29
commit a299dae1a5
2 changed files with 98 additions and 76 deletions
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34
generators/chipyard/src/main/resources/csrc/cospike.cc
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@@ -20,6 +20,12 @@ extern testchip_dtm_t* dtm;
bool spike_loadarch_done = false; bool spike_loadarch_done = false;
#endif #endif
#if __has_include ("mm.h")
#define COSPIKE_SIMDRAM
#include "mm.h"
extern std::map<long long int, backing_data_t> backing_mem_data;
#endif
#define CLINT_BASE (0x2000000) #define CLINT_BASE (0x2000000)
#define CLINT_SIZE (0x1000) #define CLINT_SIZE (0x1000)
@@ -169,6 +175,22 @@ extern "C" void cospike_cosim(long long int cycle,
nullptr nullptr
); );
#ifdef COSPIKE_SIMDRAM
// match sim_t's backing memory with the SimDRAM memory
bus_t temp_mem_bus;
for (auto& pair : mems) temp_mem_bus.add_device(pair.first, pair.second);
for (auto& pair : backing_mem_data) {
size_t base = pair.first;
size_t size = pair.second.size;
printf("Matching spike memory initial state for region %lx-%lx\n", base, base + size);
if (!temp_mem_bus.store(base, size, pair.second.data)) {
printf("Error, unable to match memory at address %lx\n", base);
abort();
}
}
#endif
sim->configure_log(true, true); sim->configure_log(true, true);
// Use our own reset vector // Use our own reset vector
for (int i = 0; i < info->nharts; i++) { for (int i = 0; i < info->nharts; i++) {
@@ -305,7 +327,6 @@ extern "C" void cospike_cosim(long long int cycle,
printf("Probable magic mem %lx\n", w_data); printf("Probable magic mem %lx\n", w_data);
magic_addrs.insert(w_data); magic_addrs.insert(w_data);
} }
}
// Try to remember magic_mem addrs, and ignore these in the future // Try to remember magic_mem addrs, and ignore these in the future
if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) { if ( waddr == tohost_addr && w_data >= info->mem0_base && w_data < (info->mem0_base + info->mem0_size)) {
printf("Probable magic mem %lx\n", w_data); printf("Probable magic mem %lx\n", w_data);
@@ -335,8 +356,7 @@ extern "C" void cospike_cosim(long long int cycle,
((magic_addrs.count(mem_read_addr) || ((magic_addrs.count(mem_read_addr) ||
(tohost_addr && mem_read_addr == tohost_addr) || (tohost_addr && mem_read_addr == tohost_addr) ||
(fromhost_addr && mem_read_addr == fromhost_addr) || (fromhost_addr && mem_read_addr == fromhost_addr) ||
(CLINT_BASE <= mem_read_addr && (CLINT_BASE <= mem_read_addr && mem_read_addr < (CLINT_BASE + CLINT_SIZE)))));
mem_read_addr < (CLINT_BASE + CLINT_SIZE)))));
// check the type is compliant with writeback first // check the type is compliant with writeback first
if ((type == 0 || type == 1)) if ((type == 0 || type == 1))
@@ -376,9 +396,11 @@ extern "C" void cospike_cosim(long long int cycle,
} }
} }
if (scalar_wb ^ has_wdata) { // TODO FIX: Rocketchip TracedInstruction.wdata should be Valid(UInt)
printf("Scalar behavior divergence between spike and DUT\n"); // if (scalar_wb ^ has_wdata) {
exit(-1); // printf("Scalar wdata behavior divergence between spike and DUT\n");
// exit(-1);
// }
} }
} }
} }

2
generators/testchipip

Submodule generators/testchipip updated: b192ac11d2...de6a4a19b5