Fix Arty merge and errors from CY bump

fpga/src/main/scala/arty/TestHarness.scala

@@ -1,23 +1,27 @@
 package chipyard.fpga.arty
 
 import chisel3._
-import chisel3.experimental.{Analog}
-import scala.collection.mutable.{ArrayBuffer}
+
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.config.{Parameters}
+
 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
+
 import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions}
+import chipyard.harness.{ApplyHarnessBinders}
 import chipyard.iobinders.{HasIOBinders}
-import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
 
 class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
 
   val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
 
-  // turn IO clock into Reset type
+  // Convert harness resets from Bool to Reset type.
   val hReset = Wire(Reset())
   hReset := ck_rst
 
+  val dReset = Wire(AsyncReset())
+  dReset := reset_core.asAsyncReset
+
   // default to 32MHz clock
   withClockAndReset(clock_32MHz, hReset) {
     val dut = Module(lazyDut.module)
@@ -27,13 +31,14 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
   val harnessReset = hReset
   val success = false.B
 
-  val dutReset = reset_core
+  val dutReset = dReset
 
+  // must be after HasHarnessSignalReferences assignments
   lazyDut match { case d: HasTestHarnessFunctions =>
     d.harnessFunctions.foreach(_(this))
   }
   lazyDut match { case d: HasIOBinders =>
     ApplyHarnessBinders(this, d.lazySystem, d.portMap)
   }
-
 }
+