Fix Arty merge and errors from CY bump

fpga/src/main/scala/arty/IOBinders.scala

@@ -0,0 +1,24 @@
+package chipyard.fpga.arty
+
+import chisel3._
+import chisel3.experimental.{IO}
+
+import freechips.rocketchip.util._
+import freechips.rocketchip.devices.debug._
+
+import chipyard.iobinders.{ComposeIOBinder}
+
+class WithResetPassthrough extends ComposeIOBinder({
+  (system: HasPeripheryDebugModuleImp) => {
+    // Debug module reset
+    val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset")
+    io_ndreset := system.debug.get.ndreset
+
+    // JTAG reset
+    val sjtag = system.debug.get.systemjtag.get
+    val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
+    sjtag.reset := io_sjtag_reset
+
+    (Seq(io_ndreset, io_sjtag_reset), Nil)
+  }
+})