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Fix Arty merge and errors from CY bump

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This commit is contained in:
abejgonzalez
2020-11-05 15:04:44 -08:00
parent a7ab0dab59
commit a281869041
6 changed files with 89 additions and 106 deletions
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90
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -1,71 +1,69 @@
package chipyard.fpga.arty
import chisel3._
import chisel3.experimental.{Analog}
import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.subsystem._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import barstools.iocell.chisel._
import testchipip._
import chipyard.harness.OverrideHarnessBinder
import chipyard.HasHarnessSignalReferences
import chipyard.iobinders.GetSystemParameters
import tracegen.{TraceGenSystemModuleImp}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import scala.reflect.{ClassTag}
import sifive.blocks.devices.jtag._
import sifive.blocks.devices.pinctrl._
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => {
// (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
// ports.map {
// case d: ClockedDMIIO =>
// // Want to error here.
// case j: JTAGIO =>
// //val dtm_success = WireInit(false.B)
// //when (dtm_success) { th.success := true.B }
// //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success)
import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
// j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt
class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) {
// Debug module reset
th.dut_ndreset := ports(0)
// IOBUF(th.jd_5, j.TMS)
// PULLUP(th.jd_5)
// JTAG reset
ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
}
}
})
// IOBUF(th.jd_4, j.TDI)
// PULLUP(th.jd_4)
class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
ports.map {
case j: JTAGIO =>
withClockAndReset(th.harnessClock, th.hReset) {
val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
// IOBUF(th.jd_0, j.TDO)
JTAGPinsFromPort(io_jtag, j)
// // mimic putting a pullup on this line (part of reset vote)
// th.SRST_n := IOBUF(th.jd_6)
// PULLUP(th.jd_6)
io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool
// IOBUF(th.jd_1, j.TRSTn)
// PULLUP(th.jd_1)
// }
IOBUF(th.jd_5, io_jtag.TMS)
PULLUP(th.jd_5)
IOBUF(th.jd_4, io_jtag.TDI)
PULLUP(th.jd_4)
IOBUF(th.jd_0, io_jtag.TDO)
// mimic putting a pullup on this line (part of reset vote)
th.SRST_n := IOBUF(th.jd_6)
PULLUP(th.jd_6)
// ignore the po input
io_jtag.TCK.i.po.map(_ := DontCare)
io_jtag.TDI.i.po.map(_ := DontCare)
io_jtag.TMS.i.po.map(_ := DontCare)
io_jtag.TDO.i.po.map(_ := DontCare)
}
}
}
})
class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
// (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
// UARTAdapter.connect(ports)(system.p)
// IOBUF(th.ck_io(2), ports.txd)
// IOBUF(th.ck_io(3), ports.rxd)
withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_txd_in, ports.head.txd)
ports.head.rxd := IOBUF(th.uart_rxd_out)
}
}
})