Bump rocket-chip to standalone diplomacy

2024-03-10 12:16:12 -07:00
parent b592934402
commit a27bc7f5ed
32 changed files with 88 additions and 63 deletions
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -23,7 +23,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
    case t: boom.v4.lsu.BoomTraceGenTile => t.statusNode.makeSink()
  }

-  lazy val fakeClockDomain = sbus.generateSynchronousDomain
+  lazy val fakeClockDomain = locateTLBusWrapper("sbus").generateSynchronousDomain

  lazy val clintOpt = None
  lazy val debugOpt = None