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Bump rocket-chip to standalone diplomacy

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This commit is contained in:
Jerry Zhao
2024-03-10 12:16:12 -07:00
parent b592934402
commit a27bc7f5ed
32 changed files with 88 additions and 63 deletions
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4
fpga/src/main/scala/vc707/HarnessBinders.scala
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@@ -3,10 +3,10 @@ package chipyard.fpga.vc707
import chisel3._
import chisel3.experimental.{BaseModule}
import freechips.rocketchip.util.{HeterogeneousBag}
import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
import sifive.blocks.devices.uart.{UARTPortIO}
import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{HasSystemXilinxVC707PCIeX1ModuleImp, XilinxVC707PCIeX1IO}