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Bump rocket-chip to standalone diplomacy

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This commit is contained in:
Jerry Zhao
2024-03-10 12:16:12 -07:00
parent b592934402
commit a27bc7f5ed
32 changed files with 88 additions and 63 deletions
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5
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -5,10 +5,9 @@ import chisel3._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
import freechips.rocketchip.tilelink.{TLBundle}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
import sifive.blocks.devices.uart.{UARTPortIO, UARTParams}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
import sifive.blocks.devices.pinctrl.{BasePin}
import sifive.fpgashells.shell._