diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
index 18da543e..1a366d19 100644
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -16,6 +16,7 @@ import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTest
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
+import tracegen.{TraceGenSystemModuleImp}
 
 import barstools.iocell.chisel._
 
@@ -389,7 +390,7 @@ class WithSimSerial extends OverrideIOBinder({
 })
 
 class WithTraceGenSuccessBinder extends OverrideIOBinder({
-  (system: GroundTestSubsystemModuleImp[GroundTestSubsystem]) => {
+  (system: TraceGenSystemModuleImp) => {
     val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success"))
     successPort.suggestName("success")
     val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil }
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 1cec6e69..653efa99 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 1cec6e697ce9ea8ffa13a6d95e0734946db3adb1
+Subproject commit 653efa99a27dc155bd4b4706a7e71c5c930f62b1
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
index d6b72d4a..ca3572d7 100644
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -22,7 +22,10 @@ class TraceGenSystemModuleImp(outer: TraceGenSystem)
 
   outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := i.U }
 
-  val status = dontTouch(DebugCombiner(outer.tiles.collect { case t: GroundTestTile => t.module.status }))
+  val status = dontTouch(DebugCombiner(outer.tiles.collect {
+    case t: GroundTestTile => t.module.status
+    case t: BoomTraceGenTile => t.module.status
+  }))
   success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR
 
 }
diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala
index 329203e2..1ddf0d84 100644
--- a/generators/tracegen/src/main/scala/Tile.scala
+++ b/generators/tracegen/src/main/scala/Tile.scala
@@ -3,7 +3,7 @@ package tracegen
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing, ClockCrossingType}
+import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, SynchronousCrossing, ClockCrossingType}
 import freechips.rocketchip.groundtest._
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.rocket.constants.{MemoryOpConstants}
@@ -178,11 +178,14 @@ case class BoomTraceGenParams(
     numGens: Int,
     dcache: Option[DCacheParams] = Some(DCacheParams()),
     hartId: Int = 0
-) extends InstantiableTileParams[BoomTraceGenTile] with GroundTestTileParams
+) extends InstantiableTileParams[BoomTraceGenTile]
 {
   def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = {
     new BoomTraceGenTile(this, crossing, lookup)
   }
+  val core = RocketCoreParams(nPMPs = 0) //TODO remove this
+  val btb = None
+  val icache = Some(ICacheParams())
   val beuAddr = None
   val blockerCtrlAddr = None
   val name = None
@@ -193,23 +196,32 @@ class BoomTraceGenTile private(
   val params: BoomTraceGenParams,
   crossing: ClockCrossingType,
   lookup: LookupByHartIdImpl,
-  q: Parameters) extends GroundTestTile(params, crossing, lookup, q)
+  q: Parameters) extends BaseTile(params, crossing, lookup, q)
+  with SinksExternalInterrupts
+  with SourcesExternalNotifications
 {
   def this(params: BoomTraceGenParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
     this(params, crossing.crossingType, lookup, p)
 
+  val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil)
+  val intOutwardNode: IntOutwardNode = IntIdentityNode()
+  val slaveNode: TLInwardNode = TLIdentityNode()
+
   val boom_params = p.alterMap(Map(TileKey -> BoomTileParams(
     dcache=params.dcache,
     core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false))))
   val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params))
 
-  val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode())
+  val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node
 
   override lazy val module = new BoomTraceGenTileModuleImp(this)
 }
 
 class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
-  extends GroundTestTileModuleImp(outer){
+  extends BaseTileModuleImp(outer){
+
+  val status = IO(new GroundTestStatus)
+  val halt_and_catch_fire = None
 
   val tracegen = Module(new TraceGenerator(outer.params.traceParams))
   tracegen.io.hartid := constants.hartid