Merge pull request #568 from ucb-bar/dev-dsptools
Dsptools example cleanup
This commit is contained in:
Abraham Gonzalez
@@ -23,6 +23,8 @@ class DigitalTop(implicit p: Parameters) extends System
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with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
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with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
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with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
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with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
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with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
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with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
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{
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override lazy val module = new DigitalTopModule(this)
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@@ -465,6 +465,46 @@ class RingSystemBusRocketConfig extends Config(
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new freechips.rocketchip.system.BaseConfig)
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// DOC include end: RingSystemBusRocket
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class StreamingPassthroughRocketConfig extends Config(
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new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include start: StreamingFIRRocketConfig
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class StreamingFIRRocketConfig extends Config (
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new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new chipyard.iobinders.WithBlackBoxSimMem ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithSimSerial ++
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new testchipip.WithTSI ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithUART ++
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new chipyard.config.WithL2TLBs(1024) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include end: StreamingFIRRocketConfig
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class SmallNVDLARocketConfig extends Config(
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new chipyard.iobinders.WithUARTAdapter ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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@@ -0,0 +1,162 @@
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package chipyard.example
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import chisel3._
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import chisel3.util._
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import dspblocks._
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import dsptools.numbers._
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import freechips.rocketchip.amba.axi4stream._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.subsystem._
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/**
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* The memory interface writes entries into the queue.
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* They stream out the streaming interface
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* @param depth number of entries in the queue
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* @param streamParameters parameters for the stream node
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* @param p
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*/
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abstract class WriteQueue[D, U, E, O, B <: Data]
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(
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val depth: Int,
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val streamParameters: AXI4StreamMasterParameters = AXI4StreamMasterParameters()
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)(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR {
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// stream node, output only
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val streamNode = AXI4StreamMasterNode(streamParameters)
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lazy val module = new LazyModuleImp(this) {
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require(streamNode.out.length == 1)
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// get the output bundle associated with the AXI4Stream node
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val out = streamNode.out.head._1
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// width (in bits) of the output interface
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val width = out.params.n * 8
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// instantiate a queue
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val queue = Module(new Queue(UInt(out.params.dataBits.W), depth))
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// connect queue output to streaming output
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out.valid := queue.io.deq.valid
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out.bits.data := queue.io.deq.bits
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// don't use last
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out.bits.last := false.B
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queue.io.deq.ready := out.ready
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regmap(
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// each write adds an entry to the queue
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0x0 -> Seq(RegField.w(width, queue.io.enq)),
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// read the number of entries in the queue
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(width+7)/8 -> Seq(RegField.r(width, queue.io.count)),
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)
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}
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}
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/**
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* TLDspBlock specialization of WriteQueue
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* @param depth number of entries in the queue
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* @param csrAddress address range for peripheral
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* @param beatBytes beatBytes of TL interface
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* @param p
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*/
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class TLWriteQueue (depth: Int, csrAddress: AddressSet, beatBytes: Int)
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(implicit p: Parameters) extends WriteQueue[
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TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle
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](depth) with TLHasCSR {
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val devname = "tlQueueIn"
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val devcompat = Seq("ucb-art", "dsptools")
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val device = new SimpleDevice(devname, devcompat) {
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override def describe(resources: ResourceBindings): Description = {
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val Description(name, mapping) = super.describe(resources)
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Description(name, mapping)
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}
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}
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// make diplomatic TL node for regmap
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override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes))
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}
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object TLWriteQueue {
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def apply(
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depth: Int = 8,
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csrAddress: AddressSet = AddressSet(0x2000, 0xff),
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beatBytes: Int = 8,
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)(implicit p: Parameters) = {
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val writeQueue = LazyModule(new TLWriteQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes))
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writeQueue
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}
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}
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/**
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* The streaming interface adds elements into the queue.
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* The memory interface can read elements out of the queue.
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* @param depth number of entries in the queue
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* @param streamParameters parameters for the stream node
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* @param p
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*/
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abstract class ReadQueue[D, U, E, O, B <: Data]
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(
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val depth: Int,
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val streamParameters: AXI4StreamSlaveParameters = AXI4StreamSlaveParameters()
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)(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR {
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val streamNode = AXI4StreamSlaveNode(streamParameters)
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lazy val module = new LazyModuleImp(this) {
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require(streamNode.in.length == 1)
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// get the input associated with the stream node
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val in = streamNode.in.head._1
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// make a Decoupled[UInt] that RegReadFn can do something with
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val out = Wire(Decoupled(UInt()))
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// get width of streaming input interface
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val width = in.params.n * 8
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// instantiate a queue
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val queue = Module(new Queue(UInt(in.params.dataBits.W), depth))
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// connect input to the streaming interface
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queue.io.enq.valid := in.valid
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queue.io.enq.bits := in.bits.data
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in.ready := queue.io.enq.ready
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// connect output to wire
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out.valid := queue.io.deq.valid
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out.bits := queue.io.deq.bits
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queue.io.deq.ready := out.ready
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regmap(
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// map the output of the queue
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0x0 -> Seq(RegField.r(width, RegReadFn(out))),
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// read the number of elements in the queue
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(width+7)/8 -> Seq(RegField.r(width, queue.io.count)),
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)
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}
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}
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/**
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* TLDspBlock specialization of ReadQueue
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* @param depth number of entries in the queue
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* @param csrAddress address range
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* @param beatBytes beatBytes of TL interface
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* @param p
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*/
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class TLReadQueue( depth: Int, csrAddress: AddressSet, beatBytes: Int)
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(implicit p: Parameters) extends ReadQueue[
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TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle
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](depth) with TLHasCSR {
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val devname = "tlQueueOut"
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val devcompat = Seq("ucb-art", "dsptools")
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val device = new SimpleDevice(devname, devcompat) {
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override def describe(resources: ResourceBindings): Description = {
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val Description(name, mapping) = super.describe(resources)
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Description(name, mapping)
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}
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}
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// make diplomatic TL node for regmap
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override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes))
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}
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object TLReadQueue {
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def apply(
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depth: Int = 8,
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csrAddress: AddressSet = AddressSet(0x2100, 0xff),
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beatBytes: Int = 8)(implicit p: Parameters) = {
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val readQueue = LazyModule(new TLReadQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes))
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readQueue
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}
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}
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@@ -0,0 +1,225 @@
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//// See LICENSE for license details.
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//
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package chipyard.example
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import chisel3._
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import chisel3.experimental.FixedPoint
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import chisel3.util._
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import dspblocks._
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import dsptools.numbers._
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import freechips.rocketchip.amba.axi4stream._
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import freechips.rocketchip.config.{Parameters, Field, Config}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.subsystem._
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// FIR params
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case class GenericFIRParams(
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writeAddress: BigInt = 0x2000,
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readAddress: BigInt = 0x2100,
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depth: Int
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)
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case object GenericFIRKey extends Field[Option[GenericFIRParams]](None)
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class GenericFIRCellBundle[T<:Data:Ring](genIn:T, genOut:T) extends Bundle {
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val data: T = genIn.cloneType
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val carry: T = genOut.cloneType
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override def cloneType: this.type = GenericFIRCellBundle(genIn, genOut).asInstanceOf[this.type]
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}
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object GenericFIRCellBundle {
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def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRCellBundle[T] = new GenericFIRCellBundle(genIn, genOut)
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}
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class GenericFIRCellIO[T<:Data:Ring](genIn:T, genOut:T) extends Bundle {
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val coeff = Input(genIn.cloneType)
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val in = Flipped(Decoupled(GenericFIRCellBundle(genIn, genOut)))
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val out = Decoupled(GenericFIRCellBundle(genIn, genOut))
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}
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object GenericFIRCellIO {
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def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRCellIO[T] = new GenericFIRCellIO(genIn, genOut)
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}
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class GenericFIRBundle[T<:Data:Ring](proto: T) extends Bundle {
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val data: T = proto.cloneType
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override def cloneType: this.type = GenericFIRBundle(proto).asInstanceOf[this.type]
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}
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object GenericFIRBundle {
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def apply[T<:Data:Ring](proto: T): GenericFIRBundle[T] = new GenericFIRBundle(proto)
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}
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class GenericFIRIO[T<:Data:Ring](genIn:T, genOut:T) extends Bundle {
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val in = Flipped(Decoupled(GenericFIRBundle(genIn)))
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val out = Decoupled(GenericFIRBundle(genOut))
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}
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object GenericFIRIO {
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def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRIO[T] = new GenericFIRIO(genIn, genOut)
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}
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// A generic FIR filter
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// DOC include start: GenericFIR chisel
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class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module {
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val io = IO(GenericFIRIO(genIn, genOut))
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// Construct a vector of genericFIRDirectCells
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val directCells = Seq.fill(coeffs.length){ Module(new GenericFIRDirectCell(genIn, genOut)).io }
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// Construct the direct FIR chain
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for ((cell, coeff) <- directCells.zip(coeffs)) {
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cell.coeff := coeff
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}
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// Connect input to first cell
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directCells.head.in.bits.data := io.in.bits.data
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directCells.head.in.bits.carry := Ring[T].zero
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directCells.head.in.valid := io.in.valid
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io.in.ready := directCells.head.in.ready
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// Connect adjacent cells
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// Note that .tail() returns a collection that consists of all
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// elements in the inital collection minus the first one.
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// This means that we zip together directCells[0, n] and
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// directCells[1, n]. However, since zip ignores unmatched elements,
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// the resulting zip is (directCells[0], directCells[1]) ...
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// (directCells[n-1], directCells[n])
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for ((current, next) <- directCells.zip(directCells.tail)) {
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next.in.bits := current.out.bits
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next.in.valid := current.out.valid
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current.out.ready := next.in.ready
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}
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// Connect output to last cell
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io.out.bits.data := directCells.last.out.bits.carry
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directCells.last.out.ready := io.out.ready
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io.out.valid := directCells.last.out.valid
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}
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// DOC include end: GenericFIR chisel
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// A generic FIR direct cell used to construct a larger direct FIR chain
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//
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// in ----- [z^-1]-- out
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// |
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// coeff ----[*]
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// |
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// carryIn --[+]-- carryOut
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//
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// DOC include start: GenericFIRDirectCell chisel
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class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
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val io = IO(GenericFIRCellIO(genIn, genOut))
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// Registers to delay the input and the valid to propagate with calculations
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val hasNewData = RegInit(0.U)
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val inputReg = Reg(genIn.cloneType)
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// Passthrough ready
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io.in.ready := io.out.ready
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// When a new transaction is ready on the input, we will have new data to output
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// next cycle. Take this data in
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when (io.in.fire()) {
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hasNewData := 1.U
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inputReg := io.in.bits.data
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}
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// We should output data when our cell has new data to output and is ready to
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// recieve new data. This insures that every cell in the chain passes its data
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// on at the same time
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io.out.valid := hasNewData & io.in.fire()
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io.out.bits.data := inputReg
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|
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// Compute carry
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// This uses the ring implementation for + and *, i.e.
|
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// (a * b) maps to (Ring[T].prod(a, b)) for whicever T you use
|
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io.out.bits.carry := inputReg * io.coeff + io.in.bits.carry
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}
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// DOC include end: GenericFIRDirectCell chisel
|
||||
|
||||
|
||||
// DOC include start: GenericFIRBlock chisel
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abstract class GenericFIRBlock[D, U, EO, EI, B<:Data, T<:Data:Ring]
|
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(
|
||||
genIn: T,
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genOut: T,
|
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coeffs: Seq[T]
|
||||
)(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] {
|
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val streamNode = AXI4StreamIdentityNode()
|
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val mem = None
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
require(streamNode.in.length == 1)
|
||||
require(streamNode.out.length == 1)
|
||||
|
||||
val in = streamNode.in.head._1
|
||||
val out = streamNode.out.head._1
|
||||
|
||||
// instantiate generic fir
|
||||
val fir = Module(new GenericFIR(genIn, genOut, coeffs))
|
||||
|
||||
// Attach ready and valid to outside interface
|
||||
in.ready := fir.io.in.ready
|
||||
fir.io.in.valid := in.valid
|
||||
|
||||
fir.io.out.ready := out.ready
|
||||
out.valid := fir.io.out.valid
|
||||
|
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// cast UInt to T
|
||||
fir.io.in.bits := in.bits.data.asTypeOf(GenericFIRBundle(genIn))
|
||||
|
||||
// cast T to UInt
|
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out.bits.data := fir.io.out.bits.asUInt
|
||||
}
|
||||
}
|
||||
// DOC include end: GenericFIRBlock chisel
|
||||
|
||||
// DOC include start: TLGenericFIRBlock chisel
|
||||
class TLGenericFIRBlock[T<:Data:Ring]
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||||
(
|
||||
val genIn: T,
|
||||
val genOut: T,
|
||||
coeffs: Seq[T]
|
||||
)(implicit p: Parameters) extends
|
||||
GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T](
|
||||
genIn, genOut, coeffs
|
||||
) with TLDspBlock
|
||||
// DOC include end: TLGenericFIRBlock chisel
|
||||
|
||||
// DOC include start: TLGenericFIRChain chisel
|
||||
class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], params: GenericFIRParams)(implicit p: Parameters)
|
||||
extends TLChain(Seq(
|
||||
TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_),
|
||||
{ implicit p: Parameters =>
|
||||
val fir = LazyModule(new TLGenericFIRBlock(genIn, genOut, coeffs))
|
||||
fir
|
||||
},
|
||||
TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_)
|
||||
))
|
||||
// DOC include end: TLGenericFIRChain chisel
|
||||
|
||||
// DOC include start: CanHavePeripheryStreamingFIR chisel
|
||||
trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
|
||||
val streamingFIR = p(GenericFIRKey) match {
|
||||
case Some(params) => {
|
||||
val streamingFIR = LazyModule(new TLGenericFIRChain(
|
||||
genIn = FixedPoint(8.W, 3.BP),
|
||||
genOut = FixedPoint(8.W, 3.BP),
|
||||
coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)),
|
||||
params = params))
|
||||
pbus.toVariableWidthSlave(Some("streamingFIR")) { streamingFIR.mem.get := TLFIFOFixer() }
|
||||
Some(streamingFIR)
|
||||
}
|
||||
case None => None
|
||||
}
|
||||
}
|
||||
// DOC include end: CanHavePeripheryStreamingFIR chisel
|
||||
|
||||
/**
|
||||
* Mixin to add FIR to rocket config
|
||||
*/
|
||||
// DOC include start: WithStreamingFIR
|
||||
class WithStreamingFIR extends Config((site, here, up) => {
|
||||
case GenericFIRKey => Some(GenericFIRParams(depth = 8))
|
||||
})
|
||||
// DOC include end: WithStreamingFIR
|
||||
@@ -0,0 +1,150 @@
|
||||
//// See LICENSE for license details.
|
||||
//
|
||||
package chipyard.example
|
||||
|
||||
import chisel3._
|
||||
import chisel3.{Bundle, Module}
|
||||
import chisel3.util._
|
||||
import dspblocks._
|
||||
import dsptools.numbers._
|
||||
import freechips.rocketchip.amba.axi4stream._
|
||||
import freechips.rocketchip.config.{Parameters, Field, Config}
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.subsystem._
|
||||
|
||||
// Simple passthrough to use as testbed sanity check
|
||||
// StreamingPassthrough params
|
||||
case class StreamingPassthroughParams(
|
||||
writeAddress: BigInt = 0x2000,
|
||||
readAddress: BigInt = 0x2100,
|
||||
depth: Int
|
||||
)
|
||||
|
||||
// StreamingPassthrough key
|
||||
case object StreamingPassthroughKey extends Field[Option[StreamingPassthroughParams]](None)
|
||||
|
||||
class StreamingPassthroughBundle[T<:Data:Ring](proto: T) extends Bundle {
|
||||
val data: T = proto.cloneType
|
||||
|
||||
override def cloneType: this.type = StreamingPassthroughBundle(proto).asInstanceOf[this.type]
|
||||
}
|
||||
object StreamingPassthroughBundle {
|
||||
def apply[T<:Data:Ring](proto: T): StreamingPassthroughBundle[T] = new StreamingPassthroughBundle(proto)
|
||||
}
|
||||
|
||||
class StreamingPassthroughIO[T<:Data:Ring](proto: T) extends Bundle {
|
||||
val in = Flipped(Decoupled(StreamingPassthroughBundle(proto)))
|
||||
val out = Decoupled(StreamingPassthroughBundle(proto))
|
||||
}
|
||||
object StreamingPassthroughIO {
|
||||
def apply[T<:Data:Ring](proto: T): StreamingPassthroughIO[T] = new StreamingPassthroughIO(proto)
|
||||
}
|
||||
|
||||
class StreamingPassthrough[T<:Data:Ring](proto: T) extends Module {
|
||||
val io = IO(StreamingPassthroughIO(proto))
|
||||
|
||||
io.in.ready := io.out.ready
|
||||
io.out.bits.data := io.in.bits.data
|
||||
io.out.valid := io.in.valid
|
||||
}
|
||||
|
||||
/**
|
||||
* Make DspBlock wrapper for StreamingPassthrough
|
||||
* @param cordicParams parameters for cordic
|
||||
* @param ev$1
|
||||
* @param ev$2
|
||||
* @param ev$3
|
||||
* @param p
|
||||
* @tparam D
|
||||
* @tparam U
|
||||
* @tparam EO
|
||||
* @tparam EI
|
||||
* @tparam B
|
||||
* @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal
|
||||
*/
|
||||
abstract class StreamingPassthroughBlock[D, U, EO, EI, B<:Data, T<:Data:Ring]
|
||||
(
|
||||
proto: T
|
||||
)(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] {
|
||||
val streamNode = AXI4StreamIdentityNode()
|
||||
val mem = None
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
require(streamNode.in.length == 1)
|
||||
require(streamNode.out.length == 1)
|
||||
|
||||
val in = streamNode.in.head._1
|
||||
val out = streamNode.out.head._1
|
||||
|
||||
// instantiate passthrough
|
||||
val passthrough = Module(new StreamingPassthrough(proto))
|
||||
|
||||
// Pass ready and valid from read queue to write queue
|
||||
in.ready := passthrough.io.in.ready
|
||||
passthrough.io.in.valid := in.valid
|
||||
|
||||
// cast UInt to T
|
||||
passthrough.io.in.bits := in.bits.data.asTypeOf(StreamingPassthroughBundle(proto))
|
||||
|
||||
passthrough.io.out.ready := out.ready
|
||||
out.valid := passthrough.io.out.valid
|
||||
|
||||
// cast T to UInt
|
||||
out.bits.data := passthrough.io.out.bits.asUInt
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* TLDspBlock specialization of StreamingPassthrough
|
||||
* @param cordicParams parameters for passthrough
|
||||
* @param ev$1
|
||||
* @param ev$2
|
||||
* @param ev$3
|
||||
* @param p
|
||||
* @tparam T Type parameter for passthrough data type
|
||||
*/
|
||||
class TLStreamingPassthroughBlock[T<:Data:Ring]
|
||||
(
|
||||
val proto: T
|
||||
)(implicit p: Parameters) extends
|
||||
StreamingPassthroughBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T](proto)
|
||||
with TLDspBlock
|
||||
|
||||
/**
|
||||
* A chain of queues acting as our MMIOs with the passthrough module in between them.
|
||||
* @param depth depth of queues
|
||||
* @param ev$1
|
||||
* @param ev$2
|
||||
* @param ev$3
|
||||
* @param p
|
||||
* @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal
|
||||
*/
|
||||
class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughParams, proto: T)(implicit p: Parameters)
|
||||
extends TLChain(Seq(
|
||||
TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_),
|
||||
{ implicit p: Parameters => {
|
||||
val streamingPassthrough = LazyModule(new TLStreamingPassthroughBlock(proto))
|
||||
streamingPassthrough
|
||||
}},
|
||||
TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_)
|
||||
))
|
||||
|
||||
trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
|
||||
val passthrough = p(StreamingPassthroughKey) match {
|
||||
case Some(params) => {
|
||||
val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W)))
|
||||
pbus.toVariableWidthSlave(Some("streamingPassthrough")) { streamingPassthroughChain.mem.get := TLFIFOFixer() }
|
||||
Some(streamingPassthroughChain)
|
||||
}
|
||||
case None => None
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Mixin to add passthrough to rocket config
|
||||
*/
|
||||
class WithStreamingPassthrough extends Config((site, here, up) => {
|
||||
case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8))
|
||||
})
|
||||
|
||||
Reference in New Issue
Block a user