From a13869b6aa5b0c5da00d974c4de7229ad400834a Mon Sep 17 00:00:00 2001 From: Angie Wang Date: Sun, 2 Apr 2017 04:10:46 -0700 Subject: [PATCH] Refactor repo for lastest changes to firrtl transform api changes (#19) --- .../transforms/ConvertToExtModPass.scala | 10 +++---- .../scala/transforms/EnumerateModules.scala | 8 +++--- .../scala/transforms/ReParentCircuit.scala | 9 +++---- .../transforms/RemoveUnusedModules.scala | 8 +++--- .../RenameModulesAndInstances.scala | 8 +++--- .../main/scala/transforms/ResetInverter.scala | 1 - .../transforms/clkgen/ClkSrcTransform.scala | 22 +++++++++------ .../clkgen/CreateClkConstraints.scala | 2 -- .../transforms/pads/AddIOPadsTransform.scala | 27 ++++++++++++------- .../scala/transforms/pads/AddPadFrame.scala | 4 +-- .../transforms/pads/AnnotatePortPads.scala | 1 - 11 files changed, 53 insertions(+), 47 deletions(-) diff --git a/tapeout/src/main/scala/transforms/ConvertToExtModPass.scala b/tapeout/src/main/scala/transforms/ConvertToExtModPass.scala index 22e6bda2..46e12ed0 100644 --- a/tapeout/src/main/scala/transforms/ConvertToExtModPass.scala +++ b/tapeout/src/main/scala/transforms/ConvertToExtModPass.scala @@ -3,6 +3,7 @@ package barstools.tapeout.transforms import firrtl._ +import firrtl.annotations.CircuitName import firrtl.ir._ import firrtl.passes.Pass @@ -10,8 +11,6 @@ import firrtl.passes.Pass // that function returns "true" then the module is converted into an ExtModule, // otherwise it's left alone. class ConvertToExtModPass(classify: (Module) => Boolean) extends Pass { - def name = "Convert to External Modules" - def run(c: Circuit): Circuit = { val modulesx = c.modules.map { case m: ExtModule => m @@ -25,12 +24,13 @@ class ConvertToExtModPass(classify: (Module) => Boolean) extends Pass { Circuit(c.info, modulesx, c.main) } } -class ConvertToExtMod(classify: (Module) => Boolean) extends Transform with PassBased { +class ConvertToExtMod(classify: (Module) => Boolean) extends Transform with SeqTransformBased { def inputForm = MidForm def outputForm = MidForm - def passSeq = Seq(new ConvertToExtModPass(classify)) + def transforms = Seq(new ConvertToExtModPass(classify)) def execute(state: CircuitState): CircuitState = { - state.copy(circuit = runPasses(state.circuit)) + val ret = runTransforms(state) + CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames) } } diff --git a/tapeout/src/main/scala/transforms/EnumerateModules.scala b/tapeout/src/main/scala/transforms/EnumerateModules.scala index 27d3e9e8..11da911e 100644 --- a/tapeout/src/main/scala/transforms/EnumerateModules.scala +++ b/tapeout/src/main/scala/transforms/EnumerateModules.scala @@ -7,7 +7,6 @@ import firrtl.ir._ import firrtl.passes.Pass class EnumerateModulesPass(enumerate: (Module) => Unit) extends Pass { - def name = "Enumurate Modules" def run(c: Circuit): Circuit = { val modulesx = c.modules.map { @@ -21,12 +20,13 @@ class EnumerateModulesPass(enumerate: (Module) => Unit) extends Pass { } } -class EnumerateModules(enumerate: (Module) => Unit) extends Transform with PassBased { +class EnumerateModules(enumerate: (Module) => Unit) extends Transform with SeqTransformBased { def inputForm = LowForm def outputForm = LowForm - def passSeq = Seq(new EnumerateModulesPass(enumerate)) + def transforms = Seq(new EnumerateModulesPass(enumerate)) def execute(state: CircuitState): CircuitState = { - state.copy(circuit = runPasses(state.circuit)) + val ret = runTransforms(state) + CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames) } } diff --git a/tapeout/src/main/scala/transforms/ReParentCircuit.scala b/tapeout/src/main/scala/transforms/ReParentCircuit.scala index acf26c98..bee7a6b3 100644 --- a/tapeout/src/main/scala/transforms/ReParentCircuit.scala +++ b/tapeout/src/main/scala/transforms/ReParentCircuit.scala @@ -8,19 +8,18 @@ import firrtl.passes.Pass // "Re-Parents" a circuit, which changes the top module to something else. class ReParentCircuitPass(newTopName: String) extends Pass { - def name = "Re-Parent Circuit" - def run(c: Circuit): Circuit = { Circuit(c.info, c.modules, newTopName) } } -class ReParentCircuit(newTopName: String) extends Transform with PassBased { +class ReParentCircuit(newTopName: String) extends Transform with SeqTransformBased { def inputForm = HighForm def outputForm = HighForm - def passSeq = Seq(new ReParentCircuitPass(newTopName)) + def transforms = Seq(new ReParentCircuitPass(newTopName)) def execute(state: CircuitState): CircuitState = { - state.copy(circuit = runPasses(state.circuit)) + val ret = runTransforms(state) + CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames) } } diff --git a/tapeout/src/main/scala/transforms/RemoveUnusedModules.scala b/tapeout/src/main/scala/transforms/RemoveUnusedModules.scala index 72a7aaf3..848b7a2c 100644 --- a/tapeout/src/main/scala/transforms/RemoveUnusedModules.scala +++ b/tapeout/src/main/scala/transforms/RemoveUnusedModules.scala @@ -9,7 +9,6 @@ import firrtl.passes.Pass // Removes all the unused modules in a circuit by recursing through every // instance (starting at the main module) class RemoveUnusedModulesPass extends Pass { - def name = "Remove Unused Modules" def run(c: Circuit): Circuit = { val modulesByName = c.modules.map{ @@ -48,12 +47,13 @@ class RemoveUnusedModulesPass extends Pass { } } -class RemoveUnusedModules extends Transform with PassBased { +class RemoveUnusedModules extends Transform with SeqTransformBased { def inputForm = MidForm def outputForm = MidForm - def passSeq = Seq(new RemoveUnusedModulesPass) + def transforms = Seq(new RemoveUnusedModulesPass) def execute(state: CircuitState): CircuitState = { - state.copy(circuit = runPasses(state.circuit)) + val ret = runTransforms(state) + CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames) } } diff --git a/tapeout/src/main/scala/transforms/RenameModulesAndInstances.scala b/tapeout/src/main/scala/transforms/RenameModulesAndInstances.scala index f0a4dd80..83c3dd71 100644 --- a/tapeout/src/main/scala/transforms/RenameModulesAndInstances.scala +++ b/tapeout/src/main/scala/transforms/RenameModulesAndInstances.scala @@ -11,7 +11,6 @@ import firrtl.passes.Pass // allow FIRRTL to be linked together using "cat" and ExtModules don't get // emitted, this should be safe. class RenameModulesAndInstancesPass(rename: (String) => String) extends Pass { - def name = "Rename Modules and Instances" def renameInstances(body: Statement): Statement = { body match { @@ -31,12 +30,13 @@ class RenameModulesAndInstancesPass(rename: (String) => String) extends Pass { } } -class RenameModulesAndInstances(rename: (String) => String) extends Transform with PassBased { +class RenameModulesAndInstances(rename: (String) => String) extends Transform with SeqTransformBased { def inputForm = LowForm def outputForm = LowForm - def passSeq = Seq(new RenameModulesAndInstancesPass(rename)) + def transforms = Seq(new RenameModulesAndInstancesPass(rename)) def execute(state: CircuitState): CircuitState = { - state.copy(circuit = runPasses(state.circuit)) + val ret = runTransforms(state) + CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames) } } diff --git a/tapeout/src/main/scala/transforms/ResetInverter.scala b/tapeout/src/main/scala/transforms/ResetInverter.scala index c699499e..d2f756f0 100644 --- a/tapeout/src/main/scala/transforms/ResetInverter.scala +++ b/tapeout/src/main/scala/transforms/ResetInverter.scala @@ -18,7 +18,6 @@ object ResetInverterAnnotation { } object ResetN extends Pass { - def name: String = "ResetN" private val Bool = UIntType(IntWidth(1)) // Only works on Modules with a Bool port named reset def invertReset(mod: Module): Module = { diff --git a/tapeout/src/main/scala/transforms/clkgen/ClkSrcTransform.scala b/tapeout/src/main/scala/transforms/clkgen/ClkSrcTransform.scala index a98086d1..f727b1cb 100644 --- a/tapeout/src/main/scala/transforms/clkgen/ClkSrcTransform.scala +++ b/tapeout/src/main/scala/transforms/clkgen/ClkSrcTransform.scala @@ -1,28 +1,34 @@ +// See LICENSE for license details. + package barstools.tapeout.transforms.clkgen import firrtl._ -import firrtl.annotations._ import firrtl.passes._ -import firrtl.ir._ -class ClkSrcTransform extends Transform with SimpleRun { +import scala.collection.mutable + +class ClkSrcTransform extends Transform with SeqTransformBased { override def inputForm: CircuitForm = LowForm override def outputForm: CircuitForm = LowForm + val transformList = new mutable.ArrayBuffer[Transform] + def transforms = transformList + override def execute(state: CircuitState): CircuitState = { val collectedAnnos = HasClkAnnotation(getMyAnnotations(state)) collectedAnnos match { // Transform not used case None => CircuitState(state.circuit, LowForm) - case Some((clkModAnnos, clkPortAnnos)) => + case Some((clkModAnnos, clkPortAnnos)) => val targetDir = barstools.tapeout.transforms.GetTargetDir(state) - val passSeq = Seq( - // TODO: Enable when it's legal? - // InferTypes, + + transformList ++= Seq( + InferTypes, new CreateClkConstraints(clkModAnnos, clkPortAnnos, targetDir) ) - state.copy(circuit = runPasses(state.circuit, passSeq)) + val ret = runTransforms(state) + CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames) } } } diff --git a/tapeout/src/main/scala/transforms/clkgen/CreateClkConstraints.scala b/tapeout/src/main/scala/transforms/clkgen/CreateClkConstraints.scala index 0c6e8823..1915bdbf 100644 --- a/tapeout/src/main/scala/transforms/clkgen/CreateClkConstraints.scala +++ b/tapeout/src/main/scala/transforms/clkgen/CreateClkConstraints.scala @@ -21,8 +21,6 @@ class CreateClkConstraints( clkPortAnnos: Seq[TargetClkPortAnnoF], targetDir: String) extends Pass { - def name = "Create clock constraints" - // TODO: Are annotations only valid on ports? def run(c: Circuit): Circuit = { diff --git a/tapeout/src/main/scala/transforms/pads/AddIOPadsTransform.scala b/tapeout/src/main/scala/transforms/pads/AddIOPadsTransform.scala index df4536a5..f9501f8f 100644 --- a/tapeout/src/main/scala/transforms/pads/AddIOPadsTransform.scala +++ b/tapeout/src/main/scala/transforms/pads/AddIOPadsTransform.scala @@ -1,3 +1,5 @@ +// See LICENSE for license details. + package barstools.tapeout.transforms.pads import firrtl._ @@ -6,22 +8,27 @@ import firrtl.passes._ import firrtl.ir._ import barstools.tapeout.transforms._ +import scala.collection.mutable + // Main Add IO Pad transform operates on low Firrtl -class AddIOPadsTransform extends Transform with SimpleRun { +class AddIOPadsTransform extends Transform with SeqTransformBased { override def inputForm: CircuitForm = LowForm override def outputForm: CircuitForm = LowForm + val transformList = new mutable.ArrayBuffer[Transform] + def transforms: Seq[Transform] = transformList + override def execute(state: CircuitState): CircuitState = { val collectedAnnos = HasPadAnnotation(getMyAnnotations(state)) collectedAnnos match { // Transform not used case None => state - case Some(x) => + case Some(x) => val techLoc = (new TechnologyLocation).get(state) // Get foundry pad templates from yaml val foundryPads = FoundryPadsYaml.parse(techLoc) - val portPads = AnnotatePortPads(state.circuit, x.topModName, foundryPads, x.componentAnnos, + val portPads = AnnotatePortPads(state.circuit, x.topModName, foundryPads, x.componentAnnos, HasPadAnnotation.getSide(x.defaultPadSide)) val supplyPads = AnnotateSupplyPads(foundryPads, x.supplyAnnos) val (circuitWithBBs, bbAnnotations) = CreatePadBBs(state.circuit, portPads, supplyPads) @@ -30,7 +37,7 @@ class AddIOPadsTransform extends Transform with SimpleRun { val topInternalName = namespace newName s"${x.topModName}_Internal" val targetDir = barstools.tapeout.transforms.GetTargetDir(state) PadPlacementFile.generate(techLoc, targetDir, padFrameName, portPads, supplyPads) - val passSeq = Seq( + transformList ++= Seq( Legalize, ResolveGenders, // Types really need to be known... @@ -44,13 +51,13 @@ class AddIOPadsTransform extends Transform with SimpleRun { ResolveGenders ) // Expects BlackBox helper to be run after to inline pad Verilog! - val prevAnnos = state.annotations.getOrElse(AnnotationMap(Seq.empty)).annotations - val cs = state.copy( - circuit = runPasses(circuitWithBBs, passSeq), - annotations = Some(AnnotationMap(prevAnnos ++ bbAnnotations))) - + val ret = runTransforms(state) + val currentAnnos = ret.annotations.getOrElse(AnnotationMap(Seq.empty)).annotations + val newAnnoMap = AnnotationMap(currentAnnos ++ bbAnnotations) + val newState = CircuitState(ret.circuit, outputForm, Some(newAnnoMap), ret.renames) + // TODO: *.f file is overwritten on subsequent executions, but it doesn't seem to be used anywhere? - (new firrtl.transforms.BlackBoxSourceHelper).execute(cs) + (new firrtl.transforms.BlackBoxSourceHelper).execute(newState) } } } \ No newline at end of file diff --git a/tapeout/src/main/scala/transforms/pads/AddPadFrame.scala b/tapeout/src/main/scala/transforms/pads/AddPadFrame.scala index 17b22fbb..853cfced 100644 --- a/tapeout/src/main/scala/transforms/pads/AddPadFrame.scala +++ b/tapeout/src/main/scala/transforms/pads/AddPadFrame.scala @@ -5,7 +5,7 @@ package barstools.tapeout.transforms.pads import firrtl.annotations._ import firrtl.ir._ import firrtl._ -import firrtl.passes._ +import firrtl.passes.Pass // Analog is like UInt, SInt; it's not a direction (which is kind of weird) // WARNING: Analog type is associated with Verilog InOut! i.e. even if digital pads are tri-statable, b/c tristate @@ -19,8 +19,6 @@ class AddPadFrame( ioPads: Seq[PortIOPad], supplyPads: Seq[TopSupplyPad]) extends Pass { - def name: String = "Add Padframe" - def run(c: Circuit): Circuit = { // New modules consist of old modules (with top renamed to internal) + padFrame + newTop val newMods = c.modules.map { diff --git a/tapeout/src/main/scala/transforms/pads/AnnotatePortPads.scala b/tapeout/src/main/scala/transforms/pads/AnnotatePortPads.scala index 1f6911a0..8164463e 100644 --- a/tapeout/src/main/scala/transforms/pads/AnnotatePortPads.scala +++ b/tapeout/src/main/scala/transforms/pads/AnnotatePortPads.scala @@ -3,7 +3,6 @@ package barstools.tapeout.transforms.pads import firrtl.annotations._ import firrtl._ import firrtl.ir._ -import firrtl.passes._ import barstools.tapeout.transforms._ // TODO: Make some trait with commonalities between IO Pad + supply pad