some docs cleanup
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alonamid
@@ -29,6 +29,13 @@ Accelerators
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Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface.
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See :ref:`Hwacha` for more information.
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.. Fixed Function Accelerators:
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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TBD
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**SHA3**
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A fixed-function accelerator for the SHA3 hash function. This simple accelerator is used as a demonstration for some of the
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Chipyard integration flows using the RoCC interface.
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System Components:
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@@ -45,9 +52,6 @@ System Components:
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**testchipip**
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A collection of utilities used for testing chips and interfacing them with larger test environments.
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.. Fixed Function Accelerators:
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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TBD
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Tools
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-------------------------------------------
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@@ -68,6 +72,9 @@ Tools
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A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL.
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See :ref:`Barstools` for more information.
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**Dsptools**
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A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC).
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Toolchains
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-------------------------------------------
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@@ -105,9 +112,9 @@ Sims
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VLSI
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-------------------------------------------
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**HAMMER**
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HAMMER is a VLSI flow designed to provide a layer of abstraction between general physical design concepts to vendor-specific EDA tool commands.
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**Hammer**
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Hammer is a VLSI flow designed to provide a layer of abstraction between general physical design concepts to vendor-specific EDA tool commands.
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The HAMMER flow provide automated scripts which generate relevant tool commands based on a higher level description of physical design constraints.
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The HAMMER flow also allows for re-use of process technology knowledge by enabling the construction of process-technology-specific plug-ins, which describe particular constraints relating to that process technology (obsolete standard cells, metal layer routing constraints, etc.).
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The HAMMER flow requires access to proprietary EDA tools and process technology libraries.
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The Hammer flow also allows for re-use of process technology knowledge by enabling the construction of process-technology-specific plug-ins, which describe particular constraints relating to that process technology (obsolete standard cells, metal layer routing constraints, etc.).
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The Hammer flow requires access to proprietary EDA tools and process technology libraries.
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See :ref:`Core HAMMER` for more information.
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@@ -1,133 +0,0 @@
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SoC Generator Config Mix-ins:
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==============================
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Rocket Chip
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-----------------------
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+ System-on-Chip
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- HasTiles
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- HasClockDomainCrossing
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- HasResetVectorWire
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- HasNoiseMakerIO
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+ Basic Core
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- HasRocketTiles
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- HasRocketCoreParameters
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- HasCoreIO
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+ Branch Prediction
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- HasBtbParameters
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+ Additional Compute
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- HasFPUCtrlSigs
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- HasFPUParameters
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- HasLazyRoCC
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- HasFpuOpt
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+ Memory System
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- HasRegMap
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- HasCoreMemOp
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- HasHellaCache
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- HasL1ICacheParameters
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- HasICacheFrontendModule
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- HasAXI4ControlRegMap
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- HasTLControlRegMap
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- HasTLBusParams
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- HasTLXbarPhy
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+ Interrupts
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- HasInterruptSources
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- HasExtInterrupts
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- HasAsyncExtInterrupts
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- HasSyncExtInterrupts
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+ Periphery
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- HasPeripheryDebug
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- HasPeripheryBootROM
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- HasBuiltInDeviceParams
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BOOM
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-----------------------
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+ Basic Core
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- HasBoomTiles
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- HasBoomCoreParameters
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- HasBoomCoreIO
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- HasBoomUOP
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- HasRegisterFileIO
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+ Branch Prediction
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- HasGShareParameters
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- HasBoomBTBParameters
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+ Memory System
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- HasL1ICacheBankedParameters
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- HasBoomICacheFrontend
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- HasBoomHellaCache
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SiFive Blocks
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-----------------------
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+ Peripherals
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- HasPeripheryGPIO
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- HasPeripheryI2C
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- HasPeripheryMockAON
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- HasPeripheryPWM
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- HasPeripherySPI
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- HasSPIProtocol
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- HasSPIEndian
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- HasSPILength
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- HasSPICSMode
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- HasPeripherySPIFlash
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- HasPeripheryUART
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testchipip
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-----------------------
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+ Peripherals
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- HasPeripheryBlockDevice
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- HasPeripherySerial
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- HasNoDebug
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Icenet
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-----------------------
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+ Periphery Network Interface Controller
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- HasPeripheryIceNIC
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AWL
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-----------------------
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+ IO
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- HasEncoding8b10b
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- HasTLBidirectionalPacketizer
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- HasTLController
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- HasGenericTransceiverSubsystem
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+ Debug/Testing
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- HasBertDebug
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- HasPatternMemDebug
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- HasBitStufferDebug4Modes
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- HasBitReversalDebug
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@@ -129,7 +129,8 @@ contain the implementation for the module, and may instantiate
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other normal modules OR lazy modules (for nested Diplomacy
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graphs, for example).
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Mix-in
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Mix-in
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---------------------------
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A mix-in is a Scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses.
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@@ -24,12 +24,12 @@ Building a Toolchain
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The `toolchains` directory contains toolchains that include a cross-compiler toolchain, frontend server, and proxy kernel, which you will need in order to compile code to RISC-V instructions and run them on your design.
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Currently there are two toolchains, one for normal RISC-V programs, and another for Hwacha (``esp-tools``).
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There are detailed instructions at https://github.com/riscv/riscv-tools to install the ``riscv-tools`` toolchain, however, the instructions are similar for the Hwacha ``esp-tools`` toolchain.
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But to get a basic installation, just the following steps are necessary.
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For custom installations, Each tool within the toolchains contains individual installation procedures within its README file.
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To get a basic installation (which is the only thing needed for most Chipyard use-cases), just the following steps are necessary.
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.. code-block:: shell
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./scripts/build-toolchains.sh riscv # for a normal risc-v toolchain
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./scripts/build-toolchains.sh riscv-tools # for a normal risc-v toolchain
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# OR
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