Merge remote-tracking branch 'origin/main' into tcip-bump

common.mk

@@ -28,7 +28,6 @@ EXTRA_SIM_CXXFLAGS   ?=
 EXTRA_SIM_LDFLAGS    ?=
 EXTRA_SIM_SOURCES    ?=
 EXTRA_SIM_REQS       ?=
-ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_YOSYS_FLOW)
 
 ifneq ($(ASPECTS), )
 	comma = ,

docs/VLSI/Sky130-Commercial-Tutorial.rst

@@ -123,8 +123,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e
 and (2) the mapping of memory instances in the design to SRAM macros;
 all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory.
 Note that the files in ``generated-src`` vary for each tool/technology flow.
-This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
+This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows, so these flows should be run in separate
-(due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate
 chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
 
 

docs/VLSI/Sky130-OpenROAD-Tutorial.rst

@@ -161,8 +161,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e
 and (2) the mapping of memory instances in the design to SRAM macros;
 all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory.
 Note that the files in ``generated-src`` vary for each tool/technology flow.
-This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
+This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows, so these flows should be run in separate
-(due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate
 chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly.
 
 
@@ -175,7 +174,6 @@ which will cause additional variables to be set in ``tutorial.mk``, a few of whi
 * ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
 * ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
 * ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
-* ``ENABLE_YOSYS_FLOW = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog.
 
 Running the VLSI Flow
 ---------------------

generators/chipyard/src/main/scala/config/NoCConfigs.scala

@@ -6,6 +6,7 @@ import freechips.rocketchip.subsystem.{SBUS, MBUS}
 
 import constellation.channel._
 import constellation.routing._
+import constellation.router._
 import constellation.topology._
 import constellation.noc._
 import constellation.soc.{GlobalNoCParams}
@@ -62,19 +63,19 @@ import scala.collection.immutable.ListMap
  */
 // DOC include start: MultiNoCConfig
 class MultiNoCConfig extends Config(
-  new constellation.soc.WithCbusNoC(constellation.protocol.TLNoCParams(
+  new constellation.soc.WithCbusNoC(constellation.protocol.SimpleTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
       inNodeMapping = ListMap(
         "serial_tl" -> 0),
       outNodeMapping = ListMap(
-        "error" -> 1, "l2[0]" -> 2, "pbus" -> 3, "plic" -> 4,
+        "error" -> 1, "ctrls[0]" -> 2, "pbus" -> 3, "plic" -> 4,
         "clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)),
     NoCParams(
       topology = TerminalRouter(BidirectionalLine(9)),
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }),
       routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1))
   )) ++
-  new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams(
+  new constellation.soc.WithMbusNoC(constellation.protocol.SimpleTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
       inNodeMapping = ListMap(
         "L2 InclusiveCache[0]" -> 1, "L2 InclusiveCache[1]" -> 2,
@@ -87,7 +88,7 @@ class MultiNoCConfig extends Config(
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
       routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalTorus1DShortestRouting()), 5, 2))
   )) ++
-  new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
+  new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
       inNodeMapping = ListMap(
         "Core 0" -> 1, "Core 1" -> 2,  "Core 2" -> 4 , "Core 3" -> 7,
@@ -162,15 +163,15 @@ class SharedNoCConfig extends Config(
                            BidirectionalLineRouting()))), 10, 2)
     )
   )) ++
-  new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams(
+  new constellation.soc.WithMbusNoC(constellation.protocol.GlobalTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
       inNodeMapping = ListMap(
         "Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6),
       outNodeMapping = ListMap(
         "system[0]" -> 3, "system[1]" -> 5,
         "serial_tl_0" -> 9))
-  ), true) ++
+  )) ++
-  new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
+  new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
       inNodeMapping = ListMap(
         "serial_tl" -> 9, "Core 0" -> 2,
@@ -179,7 +180,7 @@ class SharedNoCConfig extends Config(
       outNodeMapping = ListMap(
         "system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6,
         "pbus" -> 4))
-  ), true) ++
+  )) ++
   new freechips.rocketchip.subsystem.WithNBigCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
@@ -187,8 +188,9 @@ class SharedNoCConfig extends Config(
 )
 // DOC include end: SharedNoCConfig
 
+// This Config implements a simple ring interconnect for the system bus
 class SbusRingNoCConfig extends Config(
-  new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
+  new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
       inNodeMapping = ListMap(
         "Core 0" -> 0,
@@ -205,13 +207,61 @@ class SbusRingNoCConfig extends Config(
         "system[1]" -> 10,
         "system[2]" -> 11,
         "system[3]" -> 12,
-        "pbus" -> 8)), // TSI is on the pbus, so serial_tl and pbus should be on the same node
+        "pbus" -> 8)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
-    NoCParams(
+    acdNoCParams = NoCParams(
       topology        = UnidirectionalTorus1D(13),
-      channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
+      channelParamGen = (a, b) => UserChannelParams(Seq.fill(6) { UserVirtualChannelParams(4) }),
-      routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2))
+      routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 3, 2)),
+    beNoCParams = NoCParams(
+      topology        = UnidirectionalTorus1D(13),
+      channelParamGen = (a, b) => UserChannelParams(Seq.fill(4) { UserVirtualChannelParams(1) }),
+      routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 2, 2))
   )) ++
   new freechips.rocketchip.subsystem.WithNBigCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.AbstractConfig
 )
+
+// This config integrates a mesh interconnect for the system bus, and divides the system bus
+// tilelink messages across two isolated interconnects
+class SbusMeshNoCConfig extends Config(
+  new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams(
+    constellation.protocol.DiplomaticNetworkNodeMapping(
+      inNodeMapping = ListMap(
+        "Core 0 " -> 0,
+        "Core 1 " -> 1,
+        "Core 2 " -> 2,
+        "Core 3 " -> 3,
+        "Core 4 " -> 4,
+        "Core 5 " -> 7,
+        "Core 6 " -> 8,
+        "Core 7 " -> 11,
+        "Core 8 " -> 12,
+        "Core 9 " -> 13,
+        "Core 10 " -> 14,
+        "Core 11 " -> 15,
+        "serial-tl" -> 0),
+      outNodeMapping = ListMap(
+        "system[0]" -> 5,
+        "system[1]" -> 6,
+        "system[2]" -> 9,
+        "system[3]" -> 10,
+        "pbus" -> 0)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
+    acdNoCParams = NoCParams(
+      topology        = Mesh2D(4, 4),
+      channelParamGen = (a, b) => UserChannelParams(Seq.fill(3) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
+      routerParams    = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
+      routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1)),
+    beNoCParams = NoCParams(
+      topology        = Mesh2D(4, 4),
+      channelParamGen = (a, b) => UserChannelParams(Seq.fill(2) { UserVirtualChannelParams(3) }, unifiedBuffer = false),
+      routerParams    = (i) => UserRouterParams(combineRCVA=true, combineSAST=true),
+      routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1)),
+    beDivision = 4
+  )) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(12) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new chipyard.config.AbstractConfig
+)
+

generators/chipyard/src/main/scala/config/TutorialConfigs.scala

@@ -90,14 +90,14 @@ class TutorialNoCConfig extends Config(
   // The inNodeMapping and outNodeMapping values are the physical identifiers of
   // routers on the topology to map the agents to. Try changing these to any
   // value within the range [0, topology.nNodes)
-  new constellation.soc.WithPbusNoC(constellation.protocol.TLNoCParams(
+  new constellation.soc.WithPbusNoC(constellation.protocol.GlobalTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
       inNodeMapping = ListMap("Core" -> 7),
       outNodeMapping = ListMap(
         "pbus" -> 8, "uart" -> 9, "control" -> 10, "gcd" -> 11,
         "writeQueue[0]" -> 0, "writeQueue[1]" -> 1, "tailChain[0]" -> 2))
-  ), true) ++
+  )) ++
-  new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams(
+  new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
       inNodeMapping = ListMap(
         "Core 0" -> 0, "Core 1" -> 1,
@@ -105,7 +105,7 @@ class TutorialNoCConfig extends Config(
       outNodeMapping = ListMap(
         "system[0]" -> 3, "system[1]" -> 4, "system[2]" -> 5, "system[3]" -> 6,
         "pbus" -> 7))
-  ), true) ++
+  )) ++
   new chipyard.example.WithGCD ++
   new chipyard.harness.WithLoopbackNIC ++
   new icenet.WithIceNIC ++

scripts/replace-content.py

@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!/usr/bin/env python3
 
 # Replace text in a file given a key identifying a block to replace.
 # If the file doesn't exist, create it.

vlsi/example-designs/sky130-openroad-rockettile.yml

@@ -22,27 +22,16 @@ vlsi.inputs.placement_constraints:
       bottom: 10
 
   # Place SRAM memory instances
-  # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
+    # data cache
-  # data cache
+  - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
-  - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
     type: hardmacro
     x: 50
     y: 50
     orientation: r90
-  - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
+  - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
     type: hardmacro
     x: 50
-    y: 450
+    y: 800
-    orientation: r90
-  - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 850
-    orientation: r90
-  - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 1250
     orientation: r90
 
   # tag array
@@ -53,7 +42,7 @@ vlsi.inputs.placement_constraints:
     orientation: r90
 
   # instruction cache
-  - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
+  - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
     type: hardmacro
     x: 50
     y: 2100

vlsi/example-designs/sky130-openroad.yml

@@ -54,8 +54,6 @@ vlsi.inputs.placement_constraints:
       bottom: 10
 
   # Place SRAM memory instances
-  # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
-  # data cache
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
     type: hardmacro
     x: 50

vlsi/example-sky130.yml

@@ -48,6 +48,11 @@ vlsi.inputs.placement_constraints:
     x: 50
     y: 50
     orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
+    type: hardmacro
+    x: 50
+    y: 800
+    orientation: r90
 
   # tag array
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"

vlsi/tutorial.mk

@@ -39,7 +39,6 @@ ifeq ($(tutorial),sky130-openroad)
                             example-designs/sky130-openroad-rockettile.yml, )
     VLSI_OBJ_DIR      ?= build-sky130-openroad
     INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
-    # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
+    # Yosys compatibility for CIRCT-generated Verilog
     ENABLE_YOSYS_FLOW  = 1
 endif
-