Add more configs for coalescer perf testing

Add run-coalperfs.sh in sims/vcs for ease of testing (please delete this file in the future)

generators/chipyard/src/main/scala/config/GPUConfig.scala

@@ -10,8 +10,8 @@ class MemtraceCoreConfig extends Config(
     traceHasSource = false) ++
   // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
   //   traceHasSource = false) ++
-  new freechips.rocketchip.subsystem.WithCoalescer ++
-  new freechips.rocketchip.subsystem.WithNLanes(4) ++
+  new freechips.rocketchip.subsystem.WithCoalescer() ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=4) ++
   // L2
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
@@ -22,49 +22,17 @@ class MemtraceCoreConfig extends Config(
   )
 
 
-class MemtraceCore128SbusConfig extends Config(
-  // Memtrace
-  new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
-    traceHasSource = false) ++
-  // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
-  //   traceHasSource = false) ++
-  new freechips.rocketchip.subsystem.WithCoalescer ++
-  new freechips.rocketchip.subsystem.WithNLanes(4) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
-  new chipyard.config.WithSystemBusWidth(128) ++ 
-  // Small Rocket core that does nothing
-  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
-  new chipyard.config.AbstractConfig
-)
+/////////////////////////////////////////////////
+/// Various Configs for perf testing (feel free to delete them later)
+/////////////////////////////////////////////////
 
-class MemtraceCore256SbusConfig extends Config(
-  // Memtrace
-  new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
-    traceHasSource = false) ++
-  // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
-  //   traceHasSource = false) ++
-  new freechips.rocketchip.subsystem.WithCoalescer ++
-  new freechips.rocketchip.subsystem.WithNLanes(4) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
-  new chipyard.config.WithSystemBusWidth(256) ++ 
-  // Small Rocket core that does nothing
-  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
-  new chipyard.config.AbstractConfig
-)
+//8 src id section
+class MemtraceCoreNV64B8IdConfig extends Config(
 
-class MemtraceCorePoXarConfig extends Config(
-  // Memtrace
-  new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
-    traceHasSource = false) ++
-  // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
-  //   traceHasSource = false) ++
-  new freechips.rocketchip.subsystem.WithCoalescer ++
-  new freechips.rocketchip.subsystem.WithPriorityCoalXbar++
-  new freechips.rocketchip.subsystem.WithNLanes(4) ++
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
   // L2
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
@@ -72,4 +40,171 @@ class MemtraceCorePoXarConfig extends Config(
   // Small Rocket core that does nothing
   new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
   new chipyard.config.AbstractConfig
-  )
+  )
+
+class MemtraceCoreNV128B8IdConfig extends Config(
+
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(128) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+class MemtraceCoreNV256B8IdConfig extends Config(
+
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(256) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+ class MemtraceCoreNV512B8IdConfig extends Config(
+
+    new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+    traceHasSource = false) ++
+    new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=8) ++
+    new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++
+    // L2
+    new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+    new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+    new chipyard.config.WithSystemBusWidth(512) ++ 
+    // Small Rocket core that does nothing
+    new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+    new chipyard.config.AbstractConfig
+    )
+
+//16 src id section
+class MemtraceCoreNV64B16IdConfig extends Config(
+
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(64) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+class MemtraceCoreNV128B16IdConfig extends Config(
+
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(128) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+class MemtraceCoreNV256B16IdConfig extends Config(
+
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(256) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+class MemtraceCoreNV512B16IdConfig extends Config(
+
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=16) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(512) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+// 32 ids sections
+class MemtraceCoreNV64B32IdConfig extends Config(
+
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(64) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+class MemtraceCoreNV128B32IdConfig extends Config(
+
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(128) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+class MemtraceCoreNV256B32IdConfig extends Config(
+
+  new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+  traceHasSource = false) ++
+  new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
+  new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
+  // L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(256) ++ 
+  // Small Rocket core that does nothing
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+ class MemtraceCoreNV512B32IdConfig extends Config(
+
+    new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace",
+    traceHasSource = false) ++
+    new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds=32) ++
+    new freechips.rocketchip.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++
+    // L2
+    new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+    new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+    new chipyard.config.WithSystemBusWidth(512) ++ 
+    // Small Rocket core that does nothing
+    new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+    new chipyard.config.AbstractConfig
+    )