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Remove Cadence & Synopsys plugins (#1410)

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* remove Cadence & Synopsys plugins from docs and scripts

* update conda-locks
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Harrison Liew
2023-03-21 09:34:38 -07:00
committed by GitHub
parent c62ff145eb
commit 9ef3001ce1
15 changed files with 332 additions and 286 deletions
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docs/VLSI/Basic-Flow.rst
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@@ -162,7 +162,7 @@ Simulation-exacted power estimation often requires a dedicated testharness for t
The simulation-extracted power estimation flow implicitly uses Hammer's gate-level simulation flow (in order to generate the ``saif`` activity data file). This gate-level simulation flow can also be run independantly from the power estimation flow using the ``make sim-par`` command.
.. Note:: The gate-level simulation flow (and there the simulation-extracted power-estimation) is currently integrated only with the Synopsys VCS simulation (Verilator does not support gate-level simulation. Support for Cadence Incisive is work-in-progress)
.. Note:: The gate-level simulation flow (and there the simulation-extracted power-estimation) is currently integrated only with the Synopsys VCS simulation (Verilator does not support gate-level simulation. Support for Cadence Xcelium is work-in-progress)
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