add SynFlops
This commit is contained in:
Donggyu Kim
@@ -5,6 +5,7 @@ import firrtl.ir.{Circuit, NoInfo}
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import firrtl.passes.RemoveEmpty
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import firrtl.Parser.parse
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import java.io.{File, StringWriter}
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import Utils.readJSON
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abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalatest.Matchers {
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val macroDir = new File("tapeout/src/test/resources/macros")
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@@ -19,11 +20,16 @@ abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalate
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MacroCompiler.run(args(mem, lib, v, synflops))
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}
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def execute(mem: Option[File], lib: Option[File], synflops: Boolean, output: String) {
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require(mem.isDefined)
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val macros = Utils.readJSON(mem).get map (x => (new Macro(x)).blackbox)
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def execute(memFile: Option[File], libFile: Option[File], synflops: Boolean, output: String) {
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require(memFile.isDefined)
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val mems = readJSON(memFile) map (_ map (x => new Macro(x)))
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val libs = readJSON(libFile) map (_ map (x => new Macro(x)))
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val macros = mems.get map (_.blackbox)
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val circuit = Circuit(NoInfo, macros, macros.last.name)
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val passes = Seq(new MacroCompilerPass(mem, lib), RemoveEmpty)
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val passes = Seq(
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new MacroCompilerPass(mems, libs),
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new SynFlopsPass(synflops, libs getOrElse mems.get),
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RemoveEmpty)
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val result = (passes foldLeft circuit)((c, pass) => pass run c)
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val gold = RemoveEmpty run parse(output)
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(result.serialize) should be (gold.serialize)
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333
tapeout/src/test/scala/transforms/macros/SynFlops.scala
Normal file
333
tapeout/src/test/scala/transforms/macros/SynFlops.scala
Normal file
@@ -0,0 +1,333 @@
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package barstools.tapeout.transforms.macros
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import java.io.File
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class Synflops2048x16_mrw extends MacroCompilerSpec {
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val mem = new File(macroDir, "mem-2048x16-mrw.json")
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val v = new File(testDir, "syn_flops_2048x16_mrw.v")
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val output =
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"""
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circuit name_of_sram_module :
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module name_of_sram_module :
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input clock : Clock
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input RW0A : UInt<11>
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input RW0I : UInt<16>
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output RW0O : UInt<16>
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input RW0E : UInt<1>
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input RW0W : UInt<1>
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input RW0M : UInt<2>
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mem ram :
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data-type => UInt<8>[2]
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depth => 2048
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read-latency => 0
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write-latency => 1
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reader => R_0
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writer => W_0
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read-under-write => undefined
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reg R_0_addr_reg : UInt<11>, clock with :
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reset => (UInt<1>("h0"), R_0_addr_reg)
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ram.R_0.clk <= clock
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ram.R_0.addr <= R_0_addr_reg
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ram.R_0.en <= RW0E
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RW0O <= cat(ram.R_0.data[1], ram.R_0.data[0])
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R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
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ram.W_0.clk <= clock
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ram.W_0.addr <= RW0A
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ram.W_0.en <= and(RW0E, RW0W)
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ram.W_0.data[0] <= bits(RW0I, 7, 0)
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ram.W_0.data[1] <= bits(RW0I, 15, 8)
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ram.W_0.mask[0] <= bits(RW0M, 0, 0)
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ram.W_0.mask[1] <= bits(RW0M, 1, 1)
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"""
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compile(mem, None, v, true)
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execute(Some(mem), None, true, output)
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}
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class Synflops2048x8_r_mw extends MacroCompilerSpec {
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val mem = new File(macroDir, "mem-2048x8-r-mw.json")
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val v = new File(testDir, "syn_flops_2048x8_r_mw.v")
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val output =
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"""
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circuit name_of_sram_module :
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module name_of_sram_module :
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input clock : Clock
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input W0A : UInt<11>
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input W0I : UInt<8>
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input W0E : UInt<1>
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input W0M : UInt<1>
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input clock : Clock
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input R0A : UInt<11>
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output R0O : UInt<8>
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mem ram :
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data-type => UInt<8>[1]
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depth => 2048
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read-latency => 0
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write-latency => 1
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reader => R_0
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writer => W_0
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read-under-write => undefined
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reg R_0_addr_reg : UInt<11>, clock with :
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reset => (UInt<1>("h0"), R_0_addr_reg)
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ram.R_0.clk <= clock
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ram.R_0.addr <= R_0_addr_reg
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ram.R_0.en <= UInt<1>("h1")
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R0O <= ram.R_0.data[0]
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R_0_addr_reg <= mux(UInt<1>("h1"), R0A, R_0_addr_reg)
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ram.W_0.clk <= clock
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ram.W_0.addr <= W0A
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ram.W_0.en <= W0E
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ram.W_0.data[0] <= bits(W0I, 7, 0)
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ram.W_0.mask[0] <= bits(W0M, 0, 0)
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"""
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compile(mem, None, v, true)
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execute(Some(mem), None, true, output)
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}
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class Synflops2048x10_rw extends MacroCompilerSpec {
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val mem = new File(macroDir, "lib-2048x10-rw.json")
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val v = new File(testDir, "syn_flops_2048x10_rw.v")
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val output =
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"""
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circuit vendor_sram :
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module vendor_sram :
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input clock : Clock
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input RW0A : UInt<11>
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input RW0I : UInt<10>
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output RW0O : UInt<10>
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input RW0E : UInt<1>
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input RW0W : UInt<1>
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mem ram :
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data-type => UInt<10>
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depth => 2048
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read-latency => 0
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write-latency => 1
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reader => R_0
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writer => W_0
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read-under-write => undefined
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reg R_0_addr_reg : UInt<11>, clock with :
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reset => (UInt<1>("h0"), R_0_addr_reg)
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ram.R_0.clk <= clock
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ram.R_0.addr <= R_0_addr_reg
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ram.R_0.en <= RW0E
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RW0O <= ram.R_0.data
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R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
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ram.W_0.clk <= clock
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ram.W_0.addr <= RW0A
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ram.W_0.en <= and(RW0E, RW0W)
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ram.W_0.data <= RW0I
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ram.W_0.mask <= UInt<1>("h1")
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"""
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compile(mem, None, v, true)
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execute(Some(mem), None, true, output)
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}
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class Synflops2048x8_mrw_re extends MacroCompilerSpec {
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val mem = new File(macroDir, "lib-2048x8-mrw-re.json")
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val v = new File(testDir, "syn_flops_2048x8_mrw_re.v")
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val output =
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"""
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circuit vendor_sram :
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module vendor_sram :
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input clock : Clock
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input RW0A : UInt<11>
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input RW0I : UInt<8>
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output RW0O : UInt<8>
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input RW0E : UInt<1>
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input RW0R : UInt<1>
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input RW0W : UInt<1>
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input RW0M : UInt<1>
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mem ram :
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data-type => UInt<8>[1]
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depth => 2048
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read-latency => 0
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write-latency => 1
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reader => R_0
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writer => W_0
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read-under-write => undefined
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reg R_0_addr_reg : UInt<11>, clock with :
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reset => (UInt<1>("h0"), R_0_addr_reg)
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ram.R_0.clk <= clock
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ram.R_0.addr <= R_0_addr_reg
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ram.R_0.en <= and(RW0E, not(RW0R))
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RW0O <= ram.R_0.data[0]
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R_0_addr_reg <= mux(and(RW0E, not(RW0R)), RW0A, R_0_addr_reg)
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ram.W_0.clk <= clock
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ram.W_0.addr <= RW0A
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ram.W_0.en <= and(RW0E, RW0W)
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ram.W_0.data[0] <= bits(RW0I, 7, 0)
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ram.W_0.mask[0] <= bits(RW0M, 0, 0)
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"""
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compile(mem, None, v, true)
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execute(Some(mem), None, true, output)
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}
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class Synflops2048x16_n28 extends MacroCompilerSpec {
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val mem = new File(macroDir, "lib-2048x16-n28.json")
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val v = new File(testDir, "syn_flops_2048x16_n28.v")
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val output =
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"""
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circuit vendor_sram_4 :
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module vendor_sram_16 :
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input clock : Clock
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input RW0A : UInt<11>
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input RW0I : UInt<16>
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output RW0O : UInt<16>
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input RW0E : UInt<1>
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input RW0W : UInt<1>
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input RW0M : UInt<16>
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mem ram :
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data-type => UInt<1>[16]
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depth => 2048
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read-latency => 0
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write-latency => 1
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reader => R_0
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writer => W_0
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read-under-write => undefined
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reg R_0_addr_reg : UInt<11>, clock with :
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reset => (UInt<1>("h0"), R_0_addr_reg)
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ram.R_0.clk <= clock
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ram.R_0.addr <= R_0_addr_reg
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ram.R_0.en <= RW0E
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RW0O <= cat(ram.R_0.data[15], cat(ram.R_0.data[14], cat(ram.R_0.data[13], cat(ram.R_0.data[12], cat(ram.R_0.data[11], cat(ram.R_0.data[10], cat(ram.R_0.data[9], cat(ram.R_0.data[8], cat(ram.R_0.data[7], cat(ram.R_0.data[6], cat(ram.R_0.data[5], cat(ram.R_0.data[4], cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))))))))))))))
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R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
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ram.W_0.clk <= clock
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ram.W_0.addr <= RW0A
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ram.W_0.en <= and(RW0E, RW0W)
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ram.W_0.data[0] <= bits(RW0I, 0, 0)
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ram.W_0.data[1] <= bits(RW0I, 1, 1)
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ram.W_0.data[2] <= bits(RW0I, 2, 2)
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ram.W_0.data[3] <= bits(RW0I, 3, 3)
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ram.W_0.data[4] <= bits(RW0I, 4, 4)
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ram.W_0.data[5] <= bits(RW0I, 5, 5)
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ram.W_0.data[6] <= bits(RW0I, 6, 6)
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ram.W_0.data[7] <= bits(RW0I, 7, 7)
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ram.W_0.data[8] <= bits(RW0I, 8, 8)
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ram.W_0.data[9] <= bits(RW0I, 9, 9)
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ram.W_0.data[10] <= bits(RW0I, 10, 10)
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ram.W_0.data[11] <= bits(RW0I, 11, 11)
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ram.W_0.data[12] <= bits(RW0I, 12, 12)
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ram.W_0.data[13] <= bits(RW0I, 13, 13)
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ram.W_0.data[14] <= bits(RW0I, 14, 14)
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ram.W_0.data[15] <= bits(RW0I, 15, 15)
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ram.W_0.mask[0] <= bits(RW0M, 0, 0)
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ram.W_0.mask[1] <= bits(RW0M, 1, 1)
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ram.W_0.mask[2] <= bits(RW0M, 2, 2)
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ram.W_0.mask[3] <= bits(RW0M, 3, 3)
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ram.W_0.mask[4] <= bits(RW0M, 4, 4)
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ram.W_0.mask[5] <= bits(RW0M, 5, 5)
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ram.W_0.mask[6] <= bits(RW0M, 6, 6)
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ram.W_0.mask[7] <= bits(RW0M, 7, 7)
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ram.W_0.mask[8] <= bits(RW0M, 8, 8)
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ram.W_0.mask[9] <= bits(RW0M, 9, 9)
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ram.W_0.mask[10] <= bits(RW0M, 10, 10)
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ram.W_0.mask[11] <= bits(RW0M, 11, 11)
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ram.W_0.mask[12] <= bits(RW0M, 12, 12)
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ram.W_0.mask[13] <= bits(RW0M, 13, 13)
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ram.W_0.mask[14] <= bits(RW0M, 14, 14)
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ram.W_0.mask[15] <= bits(RW0M, 15, 15)
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module vendor_sram_4 :
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input clock : Clock
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input RW0A : UInt<11>
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input RW0I : UInt<4>
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output RW0O : UInt<4>
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input RW0E : UInt<1>
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input RW0W : UInt<1>
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input RW0M : UInt<4>
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mem ram :
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data-type => UInt<1>[4]
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depth => 2048
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read-latency => 0
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write-latency => 1
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reader => R_0
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writer => W_0
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read-under-write => undefined
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reg R_0_addr_reg : UInt<11>, clock with :
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reset => (UInt<1>("h0"), R_0_addr_reg)
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ram.R_0.clk <= clock
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ram.R_0.addr <= R_0_addr_reg
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ram.R_0.en <= RW0E
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RW0O <= cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))
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R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
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ram.W_0.clk <= clock
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ram.W_0.addr <= RW0A
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ram.W_0.en <= and(RW0E, RW0W)
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ram.W_0.data[0] <= bits(RW0I, 0, 0)
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ram.W_0.data[1] <= bits(RW0I, 1, 1)
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ram.W_0.data[2] <= bits(RW0I, 2, 2)
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ram.W_0.data[3] <= bits(RW0I, 3, 3)
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ram.W_0.mask[0] <= bits(RW0M, 0, 0)
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ram.W_0.mask[1] <= bits(RW0M, 1, 1)
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ram.W_0.mask[2] <= bits(RW0M, 2, 2)
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ram.W_0.mask[3] <= bits(RW0M, 3, 3)
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"""
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compile(mem, None, v, true)
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execute(Some(mem), None, true, output)
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}
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class Synflops32x32_2rw extends MacroCompilerSpec {
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val mem = new File(macroDir, "lib-32x32-2rw.json")
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val v = new File(testDir, "syn_flops_32x32_2rw.v")
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val output =
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"""
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circuit SRAM2RW32x32 :
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module SRAM2RW32x32 :
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input CE1 : Clock
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input A1 : UInt<5>
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input I1 : UInt<32>
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output O1 : UInt<32>
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input CSB1 : UInt<1>
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input OEB1 : UInt<1>
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input WEB1 : UInt<1>
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input CE2 : Clock
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input A2 : UInt<5>
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input I2 : UInt<32>
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output O2 : UInt<32>
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input CSB2 : UInt<1>
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input OEB2 : UInt<1>
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input WEB2 : UInt<1>
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mem ram :
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data-type => UInt<32>
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depth => 32
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read-latency => 0
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write-latency => 1
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reader => R_0
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reader => R_1
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writer => W_0
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writer => W_1
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read-under-write => undefined
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reg R_0_addr_reg : UInt<5>, CE1 with :
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reset => (UInt<1>("h0"), R_0_addr_reg)
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ram.R_0.clk <= CE1
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ram.R_0.addr <= R_0_addr_reg
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ram.R_0.en <= and(not(CSB1), not(OEB1))
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O1 <= ram.R_0.data
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R_0_addr_reg <= mux(and(not(CSB1), not(OEB1)), A1, R_0_addr_reg)
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reg R_1_addr_reg : UInt<5>, CE2 with :
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reset => (UInt<1>("h0"), R_1_addr_reg)
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ram.R_1.clk <= CE2
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ram.R_1.addr <= R_1_addr_reg
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ram.R_1.en <= and(not(CSB2), not(OEB2))
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O2 <= ram.R_1.data
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R_1_addr_reg <= mux(and(not(CSB2), not(OEB2)), A2, R_1_addr_reg)
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ram.W_0.clk <= CE1
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ram.W_0.addr <= A1
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ram.W_0.en <= and(not(CSB1), not(WEB1))
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ram.W_0.data <= I1
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ram.W_0.mask <= UInt<1>("h1")
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ram.W_1.clk <= CE2
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ram.W_1.addr <= A2
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ram.W_1.en <= and(not(CSB2), not(WEB2))
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ram.W_1.data <= I2
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ram.W_1.mask <= UInt<1>("h1")
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"""
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compile(mem, None, v, true)
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execute(Some(mem), None, true, output)
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}
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