From 5acf583d88088f3d36f9c2ec7fc903ac1c095749 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Thu, 18 Jun 2020 13:55:33 -0700 Subject: [PATCH 01/13] OpenROAD synthesis complete with fake rams on nangate45 --- vlsi/.gitignore | 3 +- vlsi/Makefile | 20 +++-- vlsi/example-nangate45.yml | 144 ++++++++++++++++++++++++++++++++++++ vlsi/example-vlsi-nangate45 | 29 ++++++++ vlsi/hammer | 2 +- 5 files changed, 188 insertions(+), 10 deletions(-) create mode 100644 vlsi/example-nangate45.yml create mode 100755 vlsi/example-vlsi-nangate45 diff --git a/vlsi/.gitignore b/vlsi/.gitignore index 4cbcfe8f..abe3347f 100644 --- a/vlsi/.gitignore +++ b/vlsi/.gitignore @@ -3,4 +3,5 @@ __pycache__ hammer*.log build src/test/output-*.json -generated-src \ No newline at end of file +generated-src +output.json diff --git a/vlsi/Makefile b/vlsi/Makefile index 42af7ba2..912eecdd 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -19,18 +19,22 @@ include $(base_dir)/variables.mk ######################################################################################### sim_name ?= vcs # needed for GenerateSimFiles, but is unused tech_name ?= asap7 -tech_dir ?= $(if $(filter $(tech_name), asap7), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) +tech_dir ?= $(if $(filter $(tech_name),asap7 nangate45),\ + $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \ + $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json -ifeq ($(tech_name),asap7) - MACROCOMPILER_MODE ?= --mode synflops -else - MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) -endif +MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\ + --mode synflops,\ + -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict) ENV_YML ?= $(vlsi_dir)/env.yml -INPUT_CONFS ?= example.yml -HAMMER_EXEC ?= ./example-vlsi +INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ + example-nangate45.yml,\ + example.yml) +HAMMER_EXEC ?= $(if $(filter $(tech_name),nangate45),\ + example-vlsi-nangate45,\ + example-vlsi) VLSI_TOP ?= $(TOP) VLSI_HARNESS_DUT_NAME ?= dut VLSI_OBJ_DIR ?= $(vlsi_dir)/build diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml new file mode 100644 index 00000000..de4d912f --- /dev/null +++ b/vlsi/example-nangate45.yml @@ -0,0 +1,144 @@ +# Technology Setup +# Technology used is nanagate45 +vlsi.core.technology: nangate45 +# Specify dir with ASAP7 tarball +technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD" + +vlsi.core.max_threads: 12 + +# General Hammer Inputs + +# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info +vlsi.inputs.power_spec_mode: "auto" +vlsi.inputs.power_spec_type: "cpf" + +# Specify clock signals +vlsi.inputs.clocks: [ + {name: "clock", period: "5ns", uncertainty: "0.5ns"} +] + +# Generate Make include to aid in flow +vlsi.core.build_system: make + +# Power Straps +#par.power_straps_mode: generate +#par.generate_power_straps_method: by_tracks +#par.blockage_spacing: 2.0 +#par.generate_power_straps_options: +# by_tracks: +# strap_layers: +# - metal3 +# - metal4 +# - metal5 +# - metal6 +# - metal7 +# - metal8 +# pin_layers: +# - metal7 +# - metal8 +# track_width: 7 # minimum allowed for M2 & M3 +# track_spacing: 0 +# track_spacing_M3: 1 # to avoid M2 shorts at higher density +# track_start: 10 +# power_utilization: 0.05 +# power_utilization_M8: 1.0 +# power_utilization_M9: 1.0 + +# Placement Constraints +# For ASAP7, all numbers must be 4x larger than final GDS +vlsi.inputs.placement_constraints: + - path: "ChipTop" + type: toplevel + x: 0 + y: 0 + width: 1387.38 + height: 1199.1 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 +# - path: "Sha3AccelwBB/dco" +# type: hardmacro +# x: 108 +# y: 108 +# width: 128 +# height: 128 +# orientation: r0 +# top_layer: M9 +# - path: "Sha3AccelwBB/place_obs_bottom" +# type: obstruction +# obs_types: ["place"] +# x: 0 +# y: 0 +# width: 300 +# height: 1.08 # 1 core site tall, necessary to avoid shorts + +# Pin placement constraints +#vlsi.inputs.pin_mode: generated +#vlsi.inputs.pin.generate_mode: semi_auto +#vlsi.inputs.pin.assignments: [ +# {pins: "*", layers: ["metal7", "metal8"]} +#] + +# Paths to extra libraries +#vlsi.technology.extra_libraries_meta: ["append", "deepsubst"] +#vlsi.technology.extra_libraries: +# - library: +# nldm liberty file_deepsubst_meta: "local" +# nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib" +# lef file_deepsubst_meta: "local" +# lef file: "extra_libraries/example/ExampleDCO.lef" +# gds file_deepsubst_meta: "local" +# gds file: "extra_libraries/example/ExampleDCO.gds" +# corner: +# nmos: "slow" +# pmos: "slow" +# temperature: "100 C" +# supplies: +# VDD: "0.63 V" +# GND: "0 V" +# - library: +# nldm liberty file_deepsubst_meta: "local" +# nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib" +# lef file_deepsubst_meta: "local" +# lef file: "extra_libraries/example/ExampleDCO.lef" +# gds file_deepsubst_meta: "local" +# gds file: "extra_libraries/example/ExampleDCO.gds" +# corner: +# nmos: "fast" +# pmos: "fast" +# temperature: "0 C" +# supplies: +# VDD: "0.77 V" +# GND: "0 V" + +# Because the DCO is a dummy layout, we treat it as a physical-only cell +#par.inputs.physical_only_cells_mode: append +#par.inputs.physical_only_cells_list: +# - ExampleDCO + +# SRAM Compiler compiler options +vlsi.core.sram_generator_tool: "sram_compiler" +## You should specify a location for the SRAM generator in the tech plugin +vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/nangate45"] +vlsi.core.sram_generator_tool_path_meta: "append" + +# Tool options. Replace with your tool plugin of choice. +# yosys options +vlsi.core.synthesis_tool: "yosys" +vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"] +vlsi.core.synthesis_tool_path_meta: "append" + +# Innovus options +#vlsi.core.par_tool: "innovus" +#vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] +#vlsi.core.par_tool_path_meta: "append" +#par.innovus.version: "181" +#par.innovus.design_flow_effort: "standard" +#par.inputs.gds_merge: true +## Calibre options +#vlsi.core.drc_tool: "calibre" +#vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"] +#vlsi.core.lvs_tool: "calibre" +#vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"] diff --git a/vlsi/example-vlsi-nangate45 b/vlsi/example-vlsi-nangate45 new file mode 100755 index 00000000..39b9a493 --- /dev/null +++ b/vlsi/example-vlsi-nangate45 @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +import os + +import hammer_vlsi +from hammer_vlsi import CLIDriver, HammerToolHookAction + +from typing import Dict, Callable, Optional, List + +def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: + x.append("") + return True + +def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: + x.append("") + return True + +class ExampleDriver(CLIDriver): + def get_extra_par_hooks(self) -> List[HammerToolHookAction]: + extra_hooks = [ + # make_pre_insertion_hook will execute the custom hook before the specified step + hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), + + # make_replacement_hook will replace the specified step with a custom hook + hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), + ] + return extra_hooks + +if __name__ == '__main__': + ExampleDriver().main() diff --git a/vlsi/hammer b/vlsi/hammer index bd94e1ed..657feaed 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit bd94e1ed7a5f70fe85ea833cb89836efefe53dc7 +Subproject commit 657feaed58014f4ef5b76acaa1e0cc559f182bda From 254304428bfcce91dd9c396c9fdcb7c7a12c135f Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Fri, 19 Jun 2020 12:03:59 -0700 Subject: [PATCH 02/13] refactored openroad stuff into OpenROADTool base class. fixed PR suggestions --- vlsi/Makefile | 22 +++++++++++----------- vlsi/example-nangate45.yml | 3 ++- vlsi/hammer | 2 +- 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 912eecdd..e969ba14 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -20,28 +20,28 @@ include $(base_dir)/variables.mk sim_name ?= vcs # needed for GenerateSimFiles, but is unused tech_name ?= asap7 tech_dir ?= $(if $(filter $(tech_name),asap7 nangate45),\ - $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \ - $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) + $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \ + $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\ - --mode synflops,\ - -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict) + --mode synflops,\ + -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict) ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ - example-nangate45.yml,\ - example.yml) + example-nangate45.yml,\ + example.yml) HAMMER_EXEC ?= $(if $(filter $(tech_name),nangate45),\ - example-vlsi-nangate45,\ - example-vlsi) + example-vlsi-nangate45,\ + example-vlsi) VLSI_TOP ?= $(TOP) VLSI_HARNESS_DUT_NAME ?= dut VLSI_OBJ_DIR ?= $(vlsi_dir)/build -ifneq ($(CUSTOM_VLOG), ) - OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) +ifneq ($(CUSTOM_VLOG),) + OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) else - OBJ_DIR ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) + OBJ_DIR ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) endif ######################################################################################### diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index de4d912f..b4c1288a 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -1,7 +1,8 @@ # Technology Setup -# Technology used is nanagate45 vlsi.core.technology: nangate45 + # Specify dir with ASAP7 tarball +# TODO: figure out how to remove this, or override it within OpenROADTool technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD" vlsi.core.max_threads: 12 diff --git a/vlsi/hammer b/vlsi/hammer index 657feaed..c5a3cdf8 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 657feaed58014f4ef5b76acaa1e0cc559f182bda +Subproject commit c5a3cdf84987a46c91f3f879541060757bf225fb From c617c4db24d6a58deb45399d1c655c57390170e6 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Sat, 20 Jun 2020 13:15:56 -0700 Subject: [PATCH 03/13] openroad floorplanning broken at TritonMacroPlace. needs debugging --- vlsi/Makefile | 6 +- vlsi/{example.yml => example-asap7.yml} | 0 vlsi/example-nangate45.yml | 129 +++++------------------- vlsi/example-vlsi | 16 ++- vlsi/example-vlsi-nangate45 | 29 ------ vlsi/hammer | 2 +- 6 files changed, 43 insertions(+), 139 deletions(-) rename vlsi/{example.yml => example-asap7.yml} (100%) delete mode 100755 vlsi/example-vlsi-nangate45 diff --git a/vlsi/Makefile b/vlsi/Makefile index e969ba14..a9e3d3a5 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -31,10 +31,8 @@ MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\ ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ example-nangate45.yml,\ - example.yml) -HAMMER_EXEC ?= $(if $(filter $(tech_name),nangate45),\ - example-vlsi-nangate45,\ - example-vlsi) + example-asap7.yml) +HAMMER_EXEC ?= example-vlsi VLSI_TOP ?= $(TOP) VLSI_HARNESS_DUT_NAME ?= dut VLSI_OBJ_DIR ?= $(vlsi_dir)/build diff --git a/vlsi/example.yml b/vlsi/example-asap7.yml similarity index 100% rename from vlsi/example.yml rename to vlsi/example-asap7.yml diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index b4c1288a..7d43d068 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -1,15 +1,22 @@ +#---------------------- # Technology Setup +#---------------------- + vlsi.core.technology: nangate45 -# Specify dir with ASAP7 tarball +# the nangate45.tech.json can't reference the $OPENROAD environment variable, +# so we need to set the install dir here. # TODO: figure out how to remove this, or override it within OpenROADTool technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD" vlsi.core.max_threads: 12 +#---------------------- # General Hammer Inputs +#---------------------- -# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info +# Hammer will auto-generate a CPF for simple power designs; +# see hammer/src/hammer-vlsi/defaults.yml for more info vlsi.inputs.power_spec_mode: "auto" vlsi.inputs.power_spec_type: "cpf" @@ -21,125 +28,45 @@ vlsi.inputs.clocks: [ # Generate Make include to aid in flow vlsi.core.build_system: make -# Power Straps -#par.power_straps_mode: generate -#par.generate_power_straps_method: by_tracks -#par.blockage_spacing: 2.0 -#par.generate_power_straps_options: -# by_tracks: -# strap_layers: -# - metal3 -# - metal4 -# - metal5 -# - metal6 -# - metal7 -# - metal8 -# pin_layers: -# - metal7 -# - metal8 -# track_width: 7 # minimum allowed for M2 & M3 -# track_spacing: 0 -# track_spacing_M3: 1 # to avoid M2 shorts at higher density -# track_start: 10 -# power_utilization: 0.05 -# power_utilization_M8: 1.0 -# power_utilization_M9: 1.0 - +#---------------------- # Placement Constraints -# For ASAP7, all numbers must be 4x larger than final GDS +#---------------------- + +# For nangate45, size should be multiple of (0.19,1.4) placement grid vlsi.inputs.placement_constraints: - path: "ChipTop" type: toplevel x: 0 y: 0 - width: 1387.38 - height: 1199.1 + width: 3334.72 + height: 2398.2 margins: left: 0 right: 0 top: 0 bottom: 0 -# - path: "Sha3AccelwBB/dco" -# type: hardmacro -# x: 108 -# y: 108 -# width: 128 -# height: 128 -# orientation: r0 -# top_layer: M9 -# - path: "Sha3AccelwBB/place_obs_bottom" -# type: obstruction -# obs_types: ["place"] -# x: 0 -# y: 0 -# width: 300 -# height: 1.08 # 1 core site tall, necessary to avoid shorts - -# Pin placement constraints -#vlsi.inputs.pin_mode: generated -#vlsi.inputs.pin.generate_mode: semi_auto -#vlsi.inputs.pin.assignments: [ -# {pins: "*", layers: ["metal7", "metal8"]} -#] - -# Paths to extra libraries -#vlsi.technology.extra_libraries_meta: ["append", "deepsubst"] -#vlsi.technology.extra_libraries: -# - library: -# nldm liberty file_deepsubst_meta: "local" -# nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib" -# lef file_deepsubst_meta: "local" -# lef file: "extra_libraries/example/ExampleDCO.lef" -# gds file_deepsubst_meta: "local" -# gds file: "extra_libraries/example/ExampleDCO.gds" -# corner: -# nmos: "slow" -# pmos: "slow" -# temperature: "100 C" -# supplies: -# VDD: "0.63 V" -# GND: "0 V" -# - library: -# nldm liberty file_deepsubst_meta: "local" -# nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib" -# lef file_deepsubst_meta: "local" -# lef file: "extra_libraries/example/ExampleDCO.lef" -# gds file_deepsubst_meta: "local" -# gds file: "extra_libraries/example/ExampleDCO.gds" -# corner: -# nmos: "fast" -# pmos: "fast" -# temperature: "0 C" -# supplies: -# VDD: "0.77 V" -# GND: "0 V" - -# Because the DCO is a dummy layout, we treat it as a physical-only cell -#par.inputs.physical_only_cells_mode: append -#par.inputs.physical_only_cells_list: -# - ExampleDCO # SRAM Compiler compiler options vlsi.core.sram_generator_tool: "sram_compiler" ## You should specify a location for the SRAM generator in the tech plugin -vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/nangate45"] +vlsi.core.sram_generator_tool_path: [ + "hammer/src/hammer-vlsi/technology/nangate45"] vlsi.core.sram_generator_tool_path_meta: "append" +#---------------------- # Tool options. Replace with your tool plugin of choice. -# yosys options +#---------------------- + +# OpenROAD-yosys options vlsi.core.synthesis_tool: "yosys" vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"] vlsi.core.synthesis_tool_path_meta: "append" -# Innovus options -#vlsi.core.par_tool: "innovus" -#vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] -#vlsi.core.par_tool_path_meta: "append" -#par.innovus.version: "181" -#par.innovus.design_flow_effort: "standard" -#par.inputs.gds_merge: true -## Calibre options -#vlsi.core.drc_tool: "calibre" +# OpenROAD-par options +vlsi.core.par_tool: "openroad" +vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"] +vlsi.core.par_tool_path_meta: "append" + +## OpenROAD-drc options (no lvs) +#vlsi.core.drc_tool: "openroad" #vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"] -#vlsi.core.lvs_tool: "calibre" -#vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"] diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index f853a1ed..550b56c5 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -1,4 +1,8 @@ #!/usr/bin/env python3 +# +# NOTE: this ExampleDriver works for asap7 and nangate45. the custom hooks are +# only used for asap7 though. + import os import hammer_vlsi @@ -7,21 +11,24 @@ from hammer_vlsi import CLIDriver, HammerToolHookAction from typing import Dict, Callable, Optional, List def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # TODO # Place custom TCL here ''') return True def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # TODO # Place custom TCL here ''') return True def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # TODO # Place custom TCL here set_db route_design_bottom_routing_layer 2 @@ -34,7 +41,8 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: Scale the final GDS by a factor of 4 hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script """ - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # Write script out to a temporary file and execute it set fp [open "{script_file}" "w"] puts -nonewline $fp "{script_text}" diff --git a/vlsi/example-vlsi-nangate45 b/vlsi/example-vlsi-nangate45 deleted file mode 100755 index 39b9a493..00000000 --- a/vlsi/example-vlsi-nangate45 +++ /dev/null @@ -1,29 +0,0 @@ -#!/usr/bin/env python3 -import os - -import hammer_vlsi -from hammer_vlsi import CLIDriver, HammerToolHookAction - -from typing import Dict, Callable, Optional, List - -def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: - x.append("") - return True - -def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: - x.append("") - return True - -class ExampleDriver(CLIDriver): - def get_extra_par_hooks(self) -> List[HammerToolHookAction]: - extra_hooks = [ - # make_pre_insertion_hook will execute the custom hook before the specified step - hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), - - # make_replacement_hook will replace the specified step with a custom hook - hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), - ] - return extra_hooks - -if __name__ == '__main__': - ExampleDriver().main() diff --git a/vlsi/hammer b/vlsi/hammer index c5a3cdf8..4d431566 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit c5a3cdf84987a46c91f3f879541060757bf225fb +Subproject commit 4d431566a87bac14454c969e7073a63b86e31161 From 74807d6f293aea05a42da576666da52dbef519e4 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Mon, 22 Jun 2020 11:42:54 -0700 Subject: [PATCH 04/13] passes macro_place at 20% utilization --- vlsi/example-nangate45.yml | 2 +- vlsi/hammer | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index 7d43d068..ecc07d59 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -39,7 +39,7 @@ vlsi.inputs.placement_constraints: x: 0 y: 0 width: 3334.72 - height: 2398.2 + height: 3798.2 margins: left: 0 right: 0 diff --git a/vlsi/hammer b/vlsi/hammer index 4d431566..0e79b8c3 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 4d431566a87bac14454c969e7073a63b86e31161 +Subproject commit 0e79b8c31c47988b1dc0dd5d83101ab4a5b26fe0 From bfb09a68b40325b13eb46b5e52ffd01b6349f041 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Wed, 24 Jun 2020 11:22:05 -0700 Subject: [PATCH 05/13] openroad backend works for RocketConfig through drc. no docs --- vlsi/example-nangate45.yml | 7 ++++--- vlsi/hammer | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index ecc07d59..c1c3ba63 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -67,6 +67,7 @@ vlsi.core.par_tool: "openroad" vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"] vlsi.core.par_tool_path_meta: "append" -## OpenROAD-drc options (no lvs) -#vlsi.core.drc_tool: "openroad" -#vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"] +# OpenROAD-drc options (no lvs) +vlsi.core.drc_tool: "openroad" +vlsi.core.drc_tool_path: ["hammer/src/hammer-vlsi/drc"] +vlsi.core.drc_tool_path_meta: "append" diff --git a/vlsi/hammer b/vlsi/hammer index 0e79b8c3..70d9feec 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 0e79b8c31c47988b1dc0dd5d83101ab4a5b26fe0 +Subproject commit 70d9feec73a9633a9462ac5896f9c35201ba0bc3 From 774716ac9dcc046136449f28d0a1950eb5dd07f3 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Wed, 24 Jun 2020 12:05:38 -0700 Subject: [PATCH 06/13] udpated docs --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 70d9feec..528e745c 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 70d9feec73a9633a9462ac5896f9c35201ba0bc3 +Subproject commit 528e745c54c3901a311aade7c928e866de1d42d2 From 19152d3b73f1c2255ce378501f6c01f9363b75e9 Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 6 Jul 2020 20:29:34 -0700 Subject: [PATCH 07/13] Update README.md (#619) --- README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index c2feb678..285d337b 100644 --- a/README.md +++ b/README.md @@ -39,7 +39,9 @@ If used for research, please cite Chipyard by the following publication: journal={IEEE Micro}, title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs}, year={2020}, - pages={}, + volume={40}, + number={4}, + pages={10-21}, doi={10.1109/MM.2020.2996616}, ISSN={1937-4143}, } From ae1e44a9e360f51abb925958fab0686f36eb8d8b Mon Sep 17 00:00:00 2001 From: banahogg Date: Sat, 18 Jul 2020 17:44:52 -0700 Subject: [PATCH 08/13] Update BOOM URL in README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 285d337b..ab542cf3 100644 --- a/README.md +++ b/README.md @@ -78,7 +78,7 @@ These additional publications cover many of the internal components used in Chip [berkeley]: https://berkeley.edu [riscv]: https://riscv.org/ [rocket-chip]: https://github.com/freechipsproject/rocket-chip -[boom]: https://github.com/ucb-bar/riscv-boom +[boom]: https://github.com/riscv-boom/riscv-boom [firemarshal]: https://github.com/firesim/FireMarshal/ [ariane]: https://github.com/pulp-platform/ariane/ [gemmini]: https://github.com/ucb-bar/gemmini From b719919934b3e9663edb5753d97ca5639641b9c6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 Jul 2020 18:30:05 -0700 Subject: [PATCH 09/13] Add RANDOM_SEED variable to set random init for VCS and Verilator simulations --- common.mk | 10 +++++----- generators/tracegen/tracegen.mk | 2 +- sims/vcs/Makefile | 6 ++---- sims/verilator/Makefile | 9 ++++++++- vcs.mk | 8 ++++++++ 5 files changed, 24 insertions(+), 11 deletions(-) diff --git a/common.mk b/common.mk index 71f4440c..9d322f00 100644 --- a/common.mk +++ b/common.mk @@ -141,19 +141,19 @@ verilog: $(sim_vsrcs) ######################################################################################### .PHONY: run-binary run-binary-fast run-binary-debug run-fast run-binary: $(output_dir) $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) ######################################################################################### # helper rules to run simulator as fast as possible ######################################################################################### run-binary-fast: $(output_dir) $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast @@ -167,10 +167,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% $(output_d ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/generators/tracegen/tracegen.mk b/generators/tracegen/tracegen.mk index fc4bd246..fec62288 100644 --- a/generators/tracegen/tracegen.mk +++ b/generators/tracegen/tracegen.mk @@ -9,7 +9,7 @@ $(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh cd $(AXE_DIR) && ./make.sh $(output_dir)/tracegen.out: $(sim) - mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ + mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) $(base_dir)/scripts/check-tracegen.sh $< > $@ diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index df2dbbe6..14ebae59 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -47,13 +47,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(E # vcs simulator rules ######################################################################################### $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - -debug_pp + rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - +define+DEBUG \ - -debug_pp + +define+DEBUG ######################################################################################### # create a vcs vpd rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 667c856c..3d676efd 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -30,6 +30,13 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug WAVEFORM_FLAG=-v$(sim_out_name).vcd +# If verilator seed unspecified, verilator uses srand as random seed +ifdef RANDOM_SEED +SEED_FLAG=+verilator+seed+I$(RANDOM_SEED) +else +SEED_FLAG= +endif + .PHONY: default debug default: $(sim) debug: $(sim_debug) @@ -145,7 +152,7 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule diff --git a/vcs.mk b/vcs.mk index 96cd0636..93e75c19 100644 --- a/vcs.mk +++ b/vcs.mk @@ -1,5 +1,13 @@ WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +# If ntb_random_seed unspecified, vcs uses 1 as constant seed. +# Set ntb_random_seed_automatic to actually get a random seed +ifdef RANDOM_SEED +SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED) +else +SEED_FLAG=+ntb_random_seed_automatic +endif + CLOCK_PERIOD ?= 1.0 RESET_DELAY ?= 777.7 From df07790a5adb8e5c2f98bfc678a4d8203b902067 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Fri, 17 Jul 2020 12:22:22 -0400 Subject: [PATCH 10/13] Bump FireMarshal/QEMU/riscv-isa-sim for OpenSBI --- software/firemarshal | 2 +- toolchains/qemu | 2 +- toolchains/riscv-tools/riscv-isa-sim | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/software/firemarshal b/software/firemarshal index 6c6a08f9..83b86610 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 6c6a08f9790c660823e9f858ca87f93b2502fa44 +Subproject commit 83b866104c6860b5d03989a6cf8439aa6934b398 diff --git a/toolchains/qemu b/toolchains/qemu index 4f591025..fdd76fec 160000 --- a/toolchains/qemu +++ b/toolchains/qemu @@ -1 +1 @@ -Subproject commit 4f59102571fce49af180cfc6d4cdd2b5df7bdb14 +Subproject commit fdd76fecdde1ad444ff4deb7f1c4f7e4a1ef97d6 diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 9443c1db..8d860c19 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 9443c1dbac0301faf3a47c5e6914cc7dcb34983e +Subproject commit 8d860c190640e19e0f23a21d2479b4a36d13d342 From 16d4186ea4e8d275a6bdd55dd0c1ea8f6e145597 Mon Sep 17 00:00:00 2001 From: Sam Steffl Date: Fri, 31 Jul 2020 10:29:53 -0700 Subject: [PATCH 11/13] updated openroad hash --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 528e745c..cbc907df 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 528e745c54c3901a311aade7c928e866de1d42d2 +Subproject commit cbc907dfe8005a8d72f1b2fb7b414ad9dbfe14b1 From d7f3f91f18de038b69b9ba8cbd6a894437c543b0 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 30 Jul 2020 10:58:35 -0700 Subject: [PATCH 12/13] implement fast loadmem feature --- docs/Simulation/Software-RTL-Simulation.rst | 23 +++++++++++++++++++++ generators/testchipip | 2 +- sims/firesim | 2 +- variables.mk | 5 +++++ 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index bdafd60f..93e4dcc6 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -62,6 +62,12 @@ For instance, to run one of the riscv-tools assembly tests. .. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. +The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. + +.. code-block:: shell + + make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. For example: @@ -126,6 +132,23 @@ All ``make`` targets that can be applied to the default example, can also be app Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. +Fast Memory Loading +------------------- + +The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model. + +.. code-block:: shell + + make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000 + +The ``.hex`` file should be a text file with a hexadecimal number on each line. + +.. code-block:: text + + deadbeef + 0123 + +Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. Generating Waveforms ----------------------- diff --git a/generators/testchipip b/generators/testchipip index 8b5c89a5..3366844f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 8b5c89a5f7120e64a7ac5ce5210165426a58f3de +Subproject commit 3366844f50a7969f1997125c07ce8d00e5494cf0 diff --git a/sims/firesim b/sims/firesim index 8064d880..ec9d615f 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 8064d8808b9c936711361532a95affbfc2fcbdca +Subproject commit ec9d615f6db72684cfee16a2b57f50493b63ca1f diff --git a/variables.mk b/variables.mk index 48da498e..1aa129f3 100644 --- a/variables.mk +++ b/variables.mk @@ -163,7 +163,12 @@ output_dir=$(sim_dir)/output/$(long_name) PERMISSIVE_ON=+permissive PERMISSIVE_OFF=+permissive-off BINARY ?= +LOADMEM ?= +LOADMEM_ADDR ?= 81000000 override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles) +ifneq ($(LOADMEM),) +override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) +endif VERBOSE_FLAGS ?= +verbose sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY)))) From 813d1fdb9e37391e9a6e9445bedcb7181be74e23 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 3 Aug 2020 16:09:16 -0700 Subject: [PATCH 13/13] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index ec9d615f..b13e7529 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ec9d615f6db72684cfee16a2b57f50493b63ca1f +Subproject commit b13e75296c44b1f3fa987d15df6a595668842dfe