diff --git a/README.md b/README.md index c2feb678..ab542cf3 100644 --- a/README.md +++ b/README.md @@ -39,7 +39,9 @@ If used for research, please cite Chipyard by the following publication: journal={IEEE Micro}, title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs}, year={2020}, - pages={}, + volume={40}, + number={4}, + pages={10-21}, doi={10.1109/MM.2020.2996616}, ISSN={1937-4143}, } @@ -76,7 +78,7 @@ These additional publications cover many of the internal components used in Chip [berkeley]: https://berkeley.edu [riscv]: https://riscv.org/ [rocket-chip]: https://github.com/freechipsproject/rocket-chip -[boom]: https://github.com/ucb-bar/riscv-boom +[boom]: https://github.com/riscv-boom/riscv-boom [firemarshal]: https://github.com/firesim/FireMarshal/ [ariane]: https://github.com/pulp-platform/ariane/ [gemmini]: https://github.com/ucb-bar/gemmini diff --git a/common.mk b/common.mk index 71f4440c..9d322f00 100644 --- a/common.mk +++ b/common.mk @@ -141,19 +141,19 @@ verilog: $(sim_vsrcs) ######################################################################################### .PHONY: run-binary run-binary-fast run-binary-debug run-fast run-binary: $(output_dir) $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) ######################################################################################### # helper rules to run simulator as fast as possible ######################################################################################### run-binary-fast: $(output_dir) $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast @@ -167,10 +167,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% $(output_d ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index bdafd60f..93e4dcc6 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -62,6 +62,12 @@ For instance, to run one of the riscv-tools assembly tests. .. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. +The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file. + +.. code-block:: shell + + make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. For example: @@ -126,6 +132,23 @@ All ``make`` targets that can be applied to the default example, can also be app Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. +Fast Memory Loading +------------------- + +The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model. + +.. code-block:: shell + + make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000 + +The ``.hex`` file should be a text file with a hexadecimal number on each line. + +.. code-block:: text + + deadbeef + 0123 + +Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000. Generating Waveforms ----------------------- diff --git a/generators/testchipip b/generators/testchipip index 3bfd710c..add28f0b 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 3bfd710ce36817038aae5d11848aec9a3c0c705f +Subproject commit add28f0b61dd337c1d4fa36b48569166743cb1d5 diff --git a/generators/tracegen/tracegen.mk b/generators/tracegen/tracegen.mk index fc4bd246..fec62288 100644 --- a/generators/tracegen/tracegen.mk +++ b/generators/tracegen/tracegen.mk @@ -9,7 +9,7 @@ $(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh cd $(AXE_DIR) && ./make.sh $(output_dir)/tracegen.out: $(sim) - mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ + mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) $(base_dir)/scripts/check-tracegen.sh $< > $@ diff --git a/sims/firesim b/sims/firesim index 8064d880..b13e7529 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 8064d8808b9c936711361532a95affbfc2fcbdca +Subproject commit b13e75296c44b1f3fa987d15df6a595668842dfe diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index df2dbbe6..14ebae59 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -47,13 +47,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(E # vcs simulator rules ######################################################################################### $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - -debug_pp + rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - +define+DEBUG \ - -debug_pp + +define+DEBUG ######################################################################################### # create a vcs vpd rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 667c856c..3d676efd 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -30,6 +30,13 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug WAVEFORM_FLAG=-v$(sim_out_name).vcd +# If verilator seed unspecified, verilator uses srand as random seed +ifdef RANDOM_SEED +SEED_FLAG=+verilator+seed+I$(RANDOM_SEED) +else +SEED_FLAG= +endif + .PHONY: default debug default: $(sim) debug: $(sim_debug) @@ -145,7 +152,7 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule diff --git a/software/firemarshal b/software/firemarshal index 6c6a08f9..83b86610 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 6c6a08f9790c660823e9f858ca87f93b2502fa44 +Subproject commit 83b866104c6860b5d03989a6cf8439aa6934b398 diff --git a/toolchains/qemu b/toolchains/qemu index 4f591025..fdd76fec 160000 --- a/toolchains/qemu +++ b/toolchains/qemu @@ -1 +1 @@ -Subproject commit 4f59102571fce49af180cfc6d4cdd2b5df7bdb14 +Subproject commit fdd76fecdde1ad444ff4deb7f1c4f7e4a1ef97d6 diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 9443c1db..8d860c19 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 9443c1dbac0301faf3a47c5e6914cc7dcb34983e +Subproject commit 8d860c190640e19e0f23a21d2479b4a36d13d342 diff --git a/variables.mk b/variables.mk index e6de6ca0..61602507 100644 --- a/variables.mk +++ b/variables.mk @@ -165,7 +165,12 @@ output_dir=$(sim_dir)/output/$(long_name) PERMISSIVE_ON=+permissive PERMISSIVE_OFF=+permissive-off BINARY ?= +LOADMEM ?= +LOADMEM_ADDR ?= 81000000 override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles) +ifneq ($(LOADMEM),) +override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR) +endif VERBOSE_FLAGS ?= +verbose sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY)))) diff --git a/vcs.mk b/vcs.mk index 96cd0636..93e75c19 100644 --- a/vcs.mk +++ b/vcs.mk @@ -1,5 +1,13 @@ WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +# If ntb_random_seed unspecified, vcs uses 1 as constant seed. +# Set ntb_random_seed_automatic to actually get a random seed +ifdef RANDOM_SEED +SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED) +else +SEED_FLAG=+ntb_random_seed_automatic +endif + CLOCK_PERIOD ?= 1.0 RESET_DELAY ?= 777.7 diff --git a/vlsi/.gitignore b/vlsi/.gitignore index 4cbcfe8f..abe3347f 100644 --- a/vlsi/.gitignore +++ b/vlsi/.gitignore @@ -3,4 +3,5 @@ __pycache__ hammer*.log build src/test/output-*.json -generated-src \ No newline at end of file +generated-src +output.json diff --git a/vlsi/Makefile b/vlsi/Makefile index 42af7ba2..a9e3d3a5 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -19,25 +19,27 @@ include $(base_dir)/variables.mk ######################################################################################### sim_name ?= vcs # needed for GenerateSimFiles, but is unused tech_name ?= asap7 -tech_dir ?= $(if $(filter $(tech_name), asap7), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) +tech_dir ?= $(if $(filter $(tech_name),asap7 nangate45),\ + $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \ + $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json -ifeq ($(tech_name),asap7) - MACROCOMPILER_MODE ?= --mode synflops -else - MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) -endif +MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\ + --mode synflops,\ + -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict) ENV_YML ?= $(vlsi_dir)/env.yml -INPUT_CONFS ?= example.yml -HAMMER_EXEC ?= ./example-vlsi +INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\ + example-nangate45.yml,\ + example-asap7.yml) +HAMMER_EXEC ?= example-vlsi VLSI_TOP ?= $(TOP) VLSI_HARNESS_DUT_NAME ?= dut VLSI_OBJ_DIR ?= $(vlsi_dir)/build -ifneq ($(CUSTOM_VLOG), ) - OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) +ifneq ($(CUSTOM_VLOG),) + OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) else - OBJ_DIR ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) + OBJ_DIR ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) endif ######################################################################################### diff --git a/vlsi/example.yml b/vlsi/example-asap7.yml similarity index 100% rename from vlsi/example.yml rename to vlsi/example-asap7.yml diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml new file mode 100644 index 00000000..c1c3ba63 --- /dev/null +++ b/vlsi/example-nangate45.yml @@ -0,0 +1,73 @@ +#---------------------- +# Technology Setup +#---------------------- + +vlsi.core.technology: nangate45 + +# the nangate45.tech.json can't reference the $OPENROAD environment variable, +# so we need to set the install dir here. +# TODO: figure out how to remove this, or override it within OpenROADTool +technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD" + +vlsi.core.max_threads: 12 + +#---------------------- +# General Hammer Inputs +#---------------------- + +# Hammer will auto-generate a CPF for simple power designs; +# see hammer/src/hammer-vlsi/defaults.yml for more info +vlsi.inputs.power_spec_mode: "auto" +vlsi.inputs.power_spec_type: "cpf" + +# Specify clock signals +vlsi.inputs.clocks: [ + {name: "clock", period: "5ns", uncertainty: "0.5ns"} +] + +# Generate Make include to aid in flow +vlsi.core.build_system: make + +#---------------------- +# Placement Constraints +#---------------------- + +# For nangate45, size should be multiple of (0.19,1.4) placement grid +vlsi.inputs.placement_constraints: + - path: "ChipTop" + type: toplevel + x: 0 + y: 0 + width: 3334.72 + height: 3798.2 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 + +# SRAM Compiler compiler options +vlsi.core.sram_generator_tool: "sram_compiler" +## You should specify a location for the SRAM generator in the tech plugin +vlsi.core.sram_generator_tool_path: [ + "hammer/src/hammer-vlsi/technology/nangate45"] +vlsi.core.sram_generator_tool_path_meta: "append" + +#---------------------- +# Tool options. Replace with your tool plugin of choice. +#---------------------- + +# OpenROAD-yosys options +vlsi.core.synthesis_tool: "yosys" +vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"] +vlsi.core.synthesis_tool_path_meta: "append" + +# OpenROAD-par options +vlsi.core.par_tool: "openroad" +vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"] +vlsi.core.par_tool_path_meta: "append" + +# OpenROAD-drc options (no lvs) +vlsi.core.drc_tool: "openroad" +vlsi.core.drc_tool_path: ["hammer/src/hammer-vlsi/drc"] +vlsi.core.drc_tool_path_meta: "append" diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index f853a1ed..550b56c5 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -1,4 +1,8 @@ #!/usr/bin/env python3 +# +# NOTE: this ExampleDriver works for asap7 and nangate45. the custom hooks are +# only used for asap7 though. + import os import hammer_vlsi @@ -7,21 +11,24 @@ from hammer_vlsi import CLIDriver, HammerToolHookAction from typing import Dict, Callable, Optional, List def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # TODO # Place custom TCL here ''') return True def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # TODO # Place custom TCL here ''') return True def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # TODO # Place custom TCL here set_db route_design_bottom_routing_layer 2 @@ -34,7 +41,8 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: Scale the final GDS by a factor of 4 hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script """ - x.append(''' + if x.get_setting("vlsi.core.technology") == "asap7": + x.append(''' # Write script out to a temporary file and execute it set fp [open "{script_file}" "w"] puts -nonewline $fp "{script_text}" diff --git a/vlsi/hammer b/vlsi/hammer index bd94e1ed..cbc907df 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit bd94e1ed7a5f70fe85ea833cb89836efefe53dc7 +Subproject commit cbc907dfe8005a8d72f1b2fb7b414ad9dbfe14b1