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restructure macros for better submoduling

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This commit is contained in:
Donggyu Kim
2017-07-25 13:48:58 -07:00
committed by edwardcwang
parent 607e810b1d
commit 9de1f5f2c0
28 changed files with 27 additions and 26 deletions
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382
tapeout/src/test/scala/transforms/macros/MacroCompilerSpec.scala
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package barstools.tapeout.transforms.macros.test
import barstools.tapeout.transforms.macros._
import firrtl.ir.{Circuit, NoInfo}
import firrtl.passes.RemoveEmpty
import firrtl.Parser.parse
import java.io.{File, StringWriter}
// TODO: we should think of a less brittle way to run these tests.
abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalatest.Matchers {
val macroDir: String = "tapeout/src/test/resources/macros"
val testDir: String = "test_run_dir/macros"
new File(testDir).mkdirs // Make sure the testDir exists
// Override these to change the prefixing of macroDir and testDir
val memPrefix: String = macroDir
val libPrefix: String = macroDir
val vPrefix: String = testDir
private def args(mem: String, lib: Option[String], v: String, synflops: Boolean) =
List("-m", mem.toString, "-v", v) ++
(lib match { case None => Nil case Some(l) => List("-l", l.toString) }) ++
(if (synflops) List("--syn-flops") else Nil)
// Run the full compiler as if from the command line interface.
// Generates the Verilog; useful in testing since an error will throw an
// exception.
def compile(mem: String, lib: String, v: String, synflops: Boolean) {
compile(mem, Some(lib), v, synflops)
}
def compile(mem: String, lib: Option[String], v: String, synflops: Boolean) {
var mem_full = concat(memPrefix, mem)
var lib_full = concat(libPrefix, lib)
var v_full = concat(vPrefix, v)
MacroCompiler.run(args(mem_full, lib_full, v_full, synflops))
}
// Helper functions to write macro libraries to the given files.
def writeToLib(lib: String, libs: Seq[mdf.macrolib.Macro]) = {
mdf.macrolib.Utils.writeMDFToPath(Some(concat(libPrefix, lib)), libs)
}
def writeToMem(mem: String, mems: Seq[mdf.macrolib.Macro]) = {
mdf.macrolib.Utils.writeMDFToPath(Some(concat(memPrefix, mem)), mems)
}
// Execute the macro compiler and compare FIRRTL outputs.
// TODO: think of a less brittle way to test this?
def execute(memFile: String, libFile: String, synflops: Boolean, output: String): Unit = {
execute(Some(memFile), Some(libFile), synflops, output)
}
def execute(memFile: Option[String], libFile: Option[String], synflops: Boolean, output: String): Unit = {
var mem_full = concat(memPrefix, memFile)
var lib_full = concat(libPrefix, libFile)
require(memFile.isDefined)
val mems: Seq[Macro] = Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(mem_full)).get map (new Macro(_))
val libs: Option[Seq[Macro]] = Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(lib_full)) match {
case Some(x) => Some(x map (new Macro(_)))
case None => None
}
val macros = mems map (_.blackbox)
val circuit = Circuit(NoInfo, macros, macros.last.name)
val passes = Seq(
new MacroCompilerPass(Some(mems), libs),
new SynFlopsPass(synflops, libs getOrElse mems),
RemoveEmpty)
val result = (passes foldLeft circuit)((c, pass) => pass run c)
val gold = RemoveEmpty run parse(output)
(result.serialize) should be (gold.serialize)
}
// Helper method to deal with String + Option[String]
private def concat(a: String, b: String): String = {a + "/" + b}
private def concat(a: String, b: Option[String]): Option[String] = {
b match {
case Some(b2:String) => Some(a + "/" + b2)
case _ => None
}
}
}
trait HasSRAMGenerator {
import mdf.macrolib._
// Generate a "simple" SRAM (active high/positive edge, 1 read-write port).
def generateSRAM(name: String, prefix: String, width: Int, depth: Int, maskGran: Option[Int] = None, extraPorts: Seq[MacroExtraPort] = List()): SRAMMacro = {
val realPrefix = prefix + "_"
SRAMMacro(
macroType=SRAM,
name=name,
width=width,
depth=depth,
family="1rw",
ports=Seq(MacroPort(
address=PolarizedPort(name=realPrefix + "addr", polarity=ActiveHigh),
clock=PolarizedPort(name=realPrefix + "clk", polarity=PositiveEdge),
writeEnable=Some(PolarizedPort(name=realPrefix + "write_en", polarity=ActiveHigh)),
output=Some(PolarizedPort(name=realPrefix + "dout", polarity=ActiveHigh)),
input=Some(PolarizedPort(name=realPrefix + "din", polarity=ActiveHigh)),
maskPort=maskGran match {
case Some(x:Int) => Some(PolarizedPort(name=realPrefix + "mask", polarity=ActiveHigh))
case _ => None
},
maskGran=maskGran,
width=width, depth=depth // These numbers don't matter here.
)),
extraPorts=extraPorts
)
}
}
//~ class RocketChipTest extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "rocketchip.json")
//~ val lib = new File(macroDir, "mylib.json")
//~ val v = new File(testDir, "rocketchip.macro.v")
//~ val output = // TODO: check correctness...
//~ """
//~ circuit T_2172_ext :
//~ module tag_array_ext :
//~ input RW0_clk : Clock
//~ input RW0_addr : UInt<6>
//~ input RW0_wdata : UInt<80>
//~ output RW0_rdata : UInt<80>
//~ input RW0_en : UInt<1>
//~ input RW0_wmode : UInt<1>
//~ input RW0_wmask : UInt<4>
//~ inst mem_0_0 of SRAM1RW64x32
//~ inst mem_0_1 of SRAM1RW64x32
//~ inst mem_0_2 of SRAM1RW64x32
//~ inst mem_0_3 of SRAM1RW64x32
//~ mem_0_0.CE <= RW0_clk
//~ mem_0_0.A <= RW0_addr
//~ node RW0_rdata_0_0 = bits(mem_0_0.O, 19, 0)
//~ mem_0_0.I <= bits(RW0_wdata, 19, 0)
//~ mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1")))
//~ mem_0_0.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_1.CE <= RW0_clk
//~ mem_0_1.A <= RW0_addr
//~ node RW0_rdata_0_1 = bits(mem_0_1.O, 19, 0)
//~ mem_0_1.I <= bits(RW0_wdata, 39, 20)
//~ mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1")))
//~ mem_0_1.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_2.CE <= RW0_clk
//~ mem_0_2.A <= RW0_addr
//~ node RW0_rdata_0_2 = bits(mem_0_2.O, 19, 0)
//~ mem_0_2.I <= bits(RW0_wdata, 59, 40)
//~ mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1")))
//~ mem_0_2.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_3.CE <= RW0_clk
//~ mem_0_3.A <= RW0_addr
//~ node RW0_rdata_0_3 = bits(mem_0_3.O, 19, 0)
//~ mem_0_3.I <= bits(RW0_wdata, 79, 60)
//~ mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1")))
//~ mem_0_3.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ node RW0_rdata_0 = cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))
//~ RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
//~ extmodule SRAM1RW64x32 :
//~ input CE : Clock
//~ input A : UInt<6>
//~ input I : UInt<32>
//~ output O : UInt<32>
//~ input CEB : UInt<1>
//~ input OEB : UInt<1>
//~ input WEB : UInt<1>
//~ defname = SRAM1RW64x32
//~ module T_1090_ext :
//~ input RW0_clk : Clock
//~ input RW0_addr : UInt<9>
//~ input RW0_wdata : UInt<64>
//~ output RW0_rdata : UInt<64>
//~ input RW0_en : UInt<1>
//~ input RW0_wmode : UInt<1>
//~ inst mem_0_0 of SRAM1RW512x32
//~ inst mem_0_1 of SRAM1RW512x32
//~ mem_0_0.CE <= RW0_clk
//~ mem_0_0.A <= RW0_addr
//~ node RW0_rdata_0_0 = bits(mem_0_0.O, 31, 0)
//~ mem_0_0.I <= bits(RW0_wdata, 31, 0)
//~ mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_0.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_0.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_1.CE <= RW0_clk
//~ mem_0_1.A <= RW0_addr
//~ node RW0_rdata_0_1 = bits(mem_0_1.O, 31, 0)
//~ mem_0_1.I <= bits(RW0_wdata, 63, 32)
//~ mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_1.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_1.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0)
//~ RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
//~ module T_406_ext :
//~ input RW0_clk : Clock
//~ input RW0_addr : UInt<9>
//~ input RW0_wdata : UInt<64>
//~ output RW0_rdata : UInt<64>
//~ input RW0_en : UInt<1>
//~ input RW0_wmode : UInt<1>
//~ input RW0_wmask : UInt<8>
//~ inst mem_0_0 of SRAM1RW512x32
//~ inst mem_0_1 of SRAM1RW512x32
//~ inst mem_0_2 of SRAM1RW512x32
//~ inst mem_0_3 of SRAM1RW512x32
//~ inst mem_0_4 of SRAM1RW512x32
//~ inst mem_0_5 of SRAM1RW512x32
//~ inst mem_0_6 of SRAM1RW512x32
//~ inst mem_0_7 of SRAM1RW512x32
//~ mem_0_0.CE <= RW0_clk
//~ mem_0_0.A <= RW0_addr
//~ node RW0_rdata_0_0 = bits(mem_0_0.O, 7, 0)
//~ mem_0_0.I <= bits(RW0_wdata, 7, 0)
//~ mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1")))
//~ mem_0_0.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_1.CE <= RW0_clk
//~ mem_0_1.A <= RW0_addr
//~ node RW0_rdata_0_1 = bits(mem_0_1.O, 7, 0)
//~ mem_0_1.I <= bits(RW0_wdata, 15, 8)
//~ mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1")))
//~ mem_0_1.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_2.CE <= RW0_clk
//~ mem_0_2.A <= RW0_addr
//~ node RW0_rdata_0_2 = bits(mem_0_2.O, 7, 0)
//~ mem_0_2.I <= bits(RW0_wdata, 23, 16)
//~ mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1")))
//~ mem_0_2.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_3.CE <= RW0_clk
//~ mem_0_3.A <= RW0_addr
//~ node RW0_rdata_0_3 = bits(mem_0_3.O, 7, 0)
//~ mem_0_3.I <= bits(RW0_wdata, 31, 24)
//~ mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1")))
//~ mem_0_3.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_4.CE <= RW0_clk
//~ mem_0_4.A <= RW0_addr
//~ node RW0_rdata_0_4 = bits(mem_0_4.O, 7, 0)
//~ mem_0_4.I <= bits(RW0_wdata, 39, 32)
//~ mem_0_4.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_4.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 4, 4)), UInt<1>("h1")))
//~ mem_0_4.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_5.CE <= RW0_clk
//~ mem_0_5.A <= RW0_addr
//~ node RW0_rdata_0_5 = bits(mem_0_5.O, 7, 0)
//~ mem_0_5.I <= bits(RW0_wdata, 47, 40)
//~ mem_0_5.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_5.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 5, 5)), UInt<1>("h1")))
//~ mem_0_5.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_6.CE <= RW0_clk
//~ mem_0_6.A <= RW0_addr
//~ node RW0_rdata_0_6 = bits(mem_0_6.O, 7, 0)
//~ mem_0_6.I <= bits(RW0_wdata, 55, 48)
//~ mem_0_6.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_6.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 6, 6)), UInt<1>("h1")))
//~ mem_0_6.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ mem_0_7.CE <= RW0_clk
//~ mem_0_7.A <= RW0_addr
//~ node RW0_rdata_0_7 = bits(mem_0_7.O, 7, 0)
//~ mem_0_7.I <= bits(RW0_wdata, 63, 56)
//~ mem_0_7.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
//~ mem_0_7.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 7, 7)), UInt<1>("h1")))
//~ mem_0_7.CEB <= not(and(RW0_en, UInt<1>("h1")))
//~ node RW0_rdata_0 = cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))))))
//~ RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
//~ extmodule SRAM1RW512x32 :
//~ input CE : Clock
//~ input A : UInt<9>
//~ input I : UInt<32>
//~ output O : UInt<32>
//~ input CEB : UInt<1>
//~ input OEB : UInt<1>
//~ input WEB : UInt<1>
//~ defname = SRAM1RW512x32
//~ module T_2172_ext :
//~ input W0_clk : Clock
//~ input W0_addr : UInt<6>
//~ input W0_data : UInt<88>
//~ input W0_en : UInt<1>
//~ input W0_mask : UInt<4>
//~ input R0_clk : Clock
//~ input R0_addr : UInt<6>
//~ output R0_data : UInt<88>
//~ input R0_en : UInt<1>
//~ inst mem_0_0 of SRAM2RW64x32
//~ inst mem_0_1 of SRAM2RW64x32
//~ inst mem_0_2 of SRAM2RW64x32
//~ inst mem_0_3 of SRAM2RW64x32
//~ mem_0_0.CE1 <= W0_clk
//~ mem_0_0.A1 <= W0_addr
//~ mem_0_0.I1 <= bits(W0_data, 21, 0)
//~ mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), UInt<1>("h1")))
//~ mem_0_0.CEB1 <= not(and(W0_en, UInt<1>("h1")))
//~ mem_0_1.CE1 <= W0_clk
//~ mem_0_1.A1 <= W0_addr
//~ mem_0_1.I1 <= bits(W0_data, 43, 22)
//~ mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 1, 1)), UInt<1>("h1")))
//~ mem_0_1.CEB1 <= not(and(W0_en, UInt<1>("h1")))
//~ mem_0_2.CE1 <= W0_clk
//~ mem_0_2.A1 <= W0_addr
//~ mem_0_2.I1 <= bits(W0_data, 65, 44)
//~ mem_0_2.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_2.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 2, 2)), UInt<1>("h1")))
//~ mem_0_2.CEB1 <= not(and(W0_en, UInt<1>("h1")))
//~ mem_0_3.CE1 <= W0_clk
//~ mem_0_3.A1 <= W0_addr
//~ mem_0_3.I1 <= bits(W0_data, 87, 66)
//~ mem_0_3.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_3.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 3, 3)), UInt<1>("h1")))
//~ mem_0_3.CEB1 <= not(and(W0_en, UInt<1>("h1")))
//~ mem_0_0.CE2 <= R0_clk
//~ mem_0_0.A2 <= R0_addr
//~ node R0_data_0_0 = bits(mem_0_0.O2, 21, 0)
//~ mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
//~ mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_0.CEB2 <= not(and(R0_en, UInt<1>("h1")))
//~ mem_0_1.CE2 <= R0_clk
//~ mem_0_1.A2 <= R0_addr
//~ node R0_data_0_1 = bits(mem_0_1.O2, 21, 0)
//~ mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
//~ mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_1.CEB2 <= not(and(R0_en, UInt<1>("h1")))
//~ mem_0_2.CE2 <= R0_clk
//~ mem_0_2.A2 <= R0_addr
//~ node R0_data_0_2 = bits(mem_0_2.O2, 21, 0)
//~ mem_0_2.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
//~ mem_0_2.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_2.CEB2 <= not(and(R0_en, UInt<1>("h1")))
//~ mem_0_3.CE2 <= R0_clk
//~ mem_0_3.A2 <= R0_addr
//~ node R0_data_0_3 = bits(mem_0_3.O2, 21, 0)
//~ mem_0_3.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
//~ mem_0_3.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_3.CEB2 <= not(and(R0_en, UInt<1>("h1")))
//~ node R0_data_0 = cat(R0_data_0_3, cat(R0_data_0_2, cat(R0_data_0_1, R0_data_0_0)))
//~ R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0"))
//~ extmodule SRAM2RW64x32 :
//~ input CE1 : Clock
//~ input A1 : UInt<6>
//~ input I1 : UInt<32>
//~ output O1 : UInt<32>
//~ input CEB1 : UInt<1>
//~ input OEB1 : UInt<1>
//~ input WEB1 : UInt<1>
//~ input CE2 : Clock
//~ input A2 : UInt<6>
//~ input I2 : UInt<32>
//~ output O2 : UInt<32>
//~ input CEB2 : UInt<1>
//~ input OEB2 : UInt<1>
//~ input WEB2 : UInt<1>
//~ defname = SRAM2RW64x32
//~ """
//~ compile(mem, Some(lib), v, false)
//~ }

451
tapeout/src/test/scala/transforms/macros/SimpleSplitDepth.scala
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@@ -1,451 +0,0 @@
package barstools.tapeout.transforms.macros.test
import firrtl.Utils.ceilLog2
import mdf.macrolib._
// Test the depth splitting aspect of the memory compiler.
// This file is for simple tests: one read-write port, powers of two sizes, etc.
// For example, implementing a 4096x32 memory using four 1024x32 memories.
trait HasSimpleDepthTestGenerator {
this: MacroCompilerSpec with HasSRAMGenerator =>
// Override these with "override lazy val".
// Why lazy? These are used in the constructor here so overriding non-lazily
// would be too late.
def width: Int
def mem_depth: Int
def lib_depth: Int
def mem_maskGran: Option[Int] = None
def lib_maskGran: Option[Int] = None
def extraPorts: Seq[mdf.macrolib.MacroExtraPort] = List()
require (mem_depth >= lib_depth)
override val memPrefix = testDir
override val libPrefix = testDir
// Convenience variables to check if a mask exists.
val memHasMask = mem_maskGran != None
val libHasMask = lib_maskGran != None
// We need to figure out how many mask bits there are in the mem.
val memMaskBits = if (memHasMask) width / mem_maskGran.get else 0
val libMaskBits = if (libHasMask) width / lib_maskGran.get else 0
// Generate "mrw" vs "rw" tags.
val memTag = (if (memHasMask) "m" else "") + "rw"
val libTag = (if (libHasMask) "m" else "") + "rw"
val mem = s"mem-${mem_depth}x${width}-${memTag}.json"
val lib = s"lib-${lib_depth}x${width}-${libTag}.json"
val v = s"split_depth_${mem_depth}x${width}_${memTag}.v"
val mem_name = "target_memory"
val mem_addr_width = ceilLog2(mem_depth)
val lib_name = "awesome_lib_mem"
val lib_addr_width = ceilLog2(lib_depth)
writeToLib(lib, Seq(generateSRAM(lib_name, "lib", width, lib_depth, lib_maskGran, extraPorts)))
writeToMem(mem, Seq(generateSRAM(mem_name, "outer", width, mem_depth, mem_maskGran)))
// Number of lib instances needed to hold the mem.
// Round up (e.g. 1.5 instances = effectively 2 instances)
val expectedInstances = math.ceil(mem_depth.toFloat / lib_depth).toInt
val selectBits = mem_addr_width - lib_addr_width
val headerMask = if (memHasMask) s"input outer_mask : UInt<${memMaskBits}>" else ""
val header = s"""
circuit $mem_name :
module $mem_name :
input outer_clk : Clock
input outer_addr : UInt<$mem_addr_width>
input outer_din : UInt<$width>
output outer_dout : UInt<$width>
input outer_write_en : UInt<1>
${headerMask}
"""
val footerMask = if (libHasMask) s"input lib_mask : UInt<${libMaskBits}>" else ""
val footer = s"""
extmodule $lib_name :
input lib_clk : Clock
input lib_addr : UInt<$lib_addr_width>
input lib_din : UInt<$width>
output lib_dout : UInt<$width>
input lib_write_en : UInt<1>
${footerMask}
defname = $lib_name
"""
var output = header
if (selectBits > 0) {
output +=
s"""
node outer_addr_sel = bits(outer_addr, ${mem_addr_width - 1}, $lib_addr_width)
"""
}
for (i <- 0 to expectedInstances - 1) {
// We only support simple masks for now (either libMask == memMask or libMask == 1)
val maskStatement = if (libHasMask) {
if (lib_maskGran.get == mem_maskGran.get) {
s"""mem_${i}_0.lib_mask <= bits(outer_mask, 0, 0)"""
} else if (lib_maskGran.get == 1) {
// Construct a mask string.
// Each bit gets the # of bits specified in maskGran.
// Specify in descending order (MSB first)
// This builds an array like m[1], m[1], m[0], m[0]
val maskBitsArr: Seq[String] = ((memMaskBits - 1 to 0 by -1) flatMap (maskBit => {
((0 to mem_maskGran.get - 1) map (_ => s"bits(outer_mask, ${maskBit}, ${maskBit})"))
}))
// Now build it into a recursive string like
// cat(m[1], cat(m[1], cat(m[0], m[0])))
val maskBitsStr: String = maskBitsArr.reverse.tail.foldLeft(maskBitsArr.reverse.head)((prev: String, next: String) => s"cat(${next}, ${prev})")
s"""mem_${i}_0.lib_mask <= ${maskBitsStr}"""
} else "" // TODO: implement when non-bitmasked memories are supported
} else "" // No mask
val enableIdentifier = if (selectBits > 0) s"""eq(outer_addr_sel, UInt<${selectBits}>("h${i.toHexString}"))""" else "UInt<1>(\"h1\")"
output +=
s"""
inst mem_${i}_0 of awesome_lib_mem
mem_${i}_0.lib_clk <= outer_clk
mem_${i}_0.lib_addr <= outer_addr
node outer_dout_${i}_0 = bits(mem_${i}_0.lib_dout, ${width - 1}, 0)
mem_${i}_0.lib_din <= bits(outer_din, ${width - 1}, 0)
${maskStatement}
mem_${i}_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), ${enableIdentifier})
node outer_dout_${i} = outer_dout_${i}_0
"""
}
def generate_outer_dout_tree(i:Int, expectedInstances: Int): String = {
if (i > expectedInstances - 1) {
"UInt<1>(\"h0\")"
} else {
"mux(eq(outer_addr_sel, UInt<%d>(\"h%s\")), outer_dout_%d, %s)".format(
selectBits, i.toHexString, i, generate_outer_dout_tree(i + 1, expectedInstances)
)
}
}
output += " outer_dout <= "
if (selectBits > 0) {
output += generate_outer_dout_tree(0, expectedInstances)
} else {
output += """mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))"""
}
output += footer
}
// Try different widths
class SplitDepth4096x32_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val mem_depth = 4096
override lazy val lib_depth = 1024
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
class SplitDepth4096x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 16
override lazy val mem_depth = 4096
override lazy val lib_depth = 1024
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
class SplitDepth32768x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val mem_depth = 32768
override lazy val lib_depth = 1024
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
class SplitDepth4096x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val mem_depth = 4096
override lazy val lib_depth = 1024
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
class SplitDepth2048x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
class SplitDepth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val mem_depth = 1024
override lazy val lib_depth = 1024
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
// Non power of two
class SplitDepth2000x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val mem_depth = 2000
override lazy val lib_depth = 1024
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
class SplitDepth2049x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val mem_depth = 2049
override lazy val lib_depth = 1024
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
// Masked RAMs
// Test for mem mask == lib mask (i.e. mask is a write enable bit)
class SplitDepth2048x32_mrw_lib32 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val mem_maskGran = Some(32)
override lazy val lib_maskGran = Some(32)
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
class SplitDepth2048x8_mrw_lib8 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 8
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val mem_maskGran = Some(8)
override lazy val lib_maskGran = Some(8)
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
// Non-bit level mask
class SplitDepth2048x64_mrw_mem32_lib8 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 64
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val mem_maskGran = Some(32)
override lazy val lib_maskGran = Some(8)
it should "be enabled when non-bitmasked memories are supported" is (pending)
//compile(mem, lib, v, false)
//execute(mem, lib, false, output)
}
// Bit level mask
class SplitDepth2048x32_mrw_mem16_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val mem_maskGran = Some(16)
override lazy val lib_maskGran = Some(1)
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
class SplitDepth2048x32_mrw_mem8_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val mem_maskGran = Some(8)
override lazy val lib_maskGran = Some(1)
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
class SplitDepth2048x32_mrw_mem4_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val mem_maskGran = Some(4)
override lazy val lib_maskGran = Some(1)
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
class SplitDepth2048x32_mrw_mem2_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val mem_maskGran = Some(2)
override lazy val lib_maskGran = Some(1)
compile(mem, lib, v, false)
execute(mem, lib, false, output)
}
// Non-powers of 2 mask sizes
class SplitDepth2048x32_mrw_mem3_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val mem_maskGran = Some(3)
override lazy val lib_maskGran = Some(1)
it should "be enabled when non-power of two masks are supported" is (pending)
//compile(mem, lib, v, false)
//execute(mem, lib, false, output)
}
class SplitDepth2048x32_mrw_mem7_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val mem_maskGran = Some(7)
override lazy val lib_maskGran = Some(1)
it should "be enabled when non-power of two masks are supported" is (pending)
//compile(mem, lib, v, false)
//execute(mem, lib, false, output)
}
class SplitDepth2048x32_mrw_mem9_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
override lazy val width = 32
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val mem_maskGran = Some(9)
override lazy val lib_maskGran = Some(1)
it should "be enabled when non-power of two masks are supported" is (pending)
//compile(mem, lib, v, false)
//execute(mem, lib, false, output)
}
//~ class SplitDepth2048x8_r_mw extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-2048x8-r-mw.json")
//~ val lib = new File(macroDir, "lib-1024x8-r-mw.json")
//~ val v = new File(testDir, "split_depth_2048x8_r_mw.v")
//~ val output =
//~ """
//~ circuit name_of_sram_module :
//~ module name_of_sram_module :
//~ input clock : Clock
//~ input W0A : UInt<11>
//~ input W0I : UInt<8>
//~ input W0E : UInt<1>
//~ input W0M : UInt<1>
//~ input clock : Clock
//~ input R0A : UInt<11>
//~ output R0O : UInt<8>
//~ node W0A_sel = bits(W0A, 10, 10)
//~ node R0A_sel = bits(R0A, 10, 10)
//~ inst mem_0_0 of vendor_sram
//~ mem_0_0.clock <= clock
//~ mem_0_0.W0A <= W0A
//~ mem_0_0.W0I <= bits(W0I, 7, 0)
//~ mem_0_0.W0M <= bits(W0M, 0, 0)
//~ mem_0_0.W0W <= and(UInt<1>("h1"), eq(W0A_sel, UInt<1>("h0")))
//~ mem_0_0.W0E <= and(W0E, eq(W0A_sel, UInt<1>("h0")))
//~ mem_0_0.clock <= clock
//~ mem_0_0.R0A <= R0A
//~ node R0O_0_0 = bits(mem_0_0.R0O, 7, 0)
//~ node R0O_0 = R0O_0_0
//~ inst mem_1_0 of vendor_sram
//~ mem_1_0.clock <= clock
//~ mem_1_0.W0A <= W0A
//~ mem_1_0.W0I <= bits(W0I, 7, 0)
//~ mem_1_0.W0M <= bits(W0M, 0, 0)
//~ mem_1_0.W0W <= and(UInt<1>("h1"), eq(W0A_sel, UInt<1>("h1")))
//~ mem_1_0.W0E <= and(W0E, eq(W0A_sel, UInt<1>("h1")))
//~ mem_1_0.clock <= clock
//~ mem_1_0.R0A <= R0A
//~ node R0O_1_0 = bits(mem_1_0.R0O, 7, 0)
//~ node R0O_1 = R0O_1_0
//~ R0O <= mux(eq(R0A_sel, UInt<1>("h0")), R0O_0, mux(eq(R0A_sel, UInt<1>("h1")), R0O_1, UInt<1>("h0")))
//~ extmodule vendor_sram :
//~ input clock : Clock
//~ input R0A : UInt<10>
//~ output R0O : UInt<8>
//~ input clock : Clock
//~ input W0A : UInt<10>
//~ input W0I : UInt<8>
//~ input W0E : UInt<1>
//~ input W0W : UInt<1>
//~ input W0M : UInt<1>
//~ defname = vendor_sram
//~ """
//~ compile(mem, lib, v, false)
//~ execute(mem, lib, false, output)
//~ }
// Try an extra port
class SplitDepth2048x8_extraPort extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
import mdf.macrolib._
override lazy val width = 8
override lazy val mem_depth = 2048
override lazy val lib_depth = 1024
override lazy val extraPorts = List(
MacroExtraPort(name="extra_port", width=8, portType=Constant, value=0xff)
)
val outputCustom =
"""
circuit target_memory :
module target_memory :
input outer_clk : Clock
input outer_addr : UInt<11>
input outer_din : UInt<8>
output outer_dout : UInt<8>
input outer_write_en : UInt<1>
node outer_addr_sel = bits(outer_addr, 10, 10)
inst mem_0_0 of awesome_lib_mem
mem_0_0.extra_port <= UInt<8>("hff")
mem_0_0.lib_clk <= outer_clk
mem_0_0.lib_addr <= outer_addr
node outer_dout_0_0 = bits(mem_0_0.lib_dout, 7, 0)
mem_0_0.lib_din <= bits(outer_din, 7, 0)
mem_0_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h0")))
node outer_dout_0 = outer_dout_0_0
inst mem_1_0 of awesome_lib_mem
mem_1_0.extra_port <= UInt<8>("hff")
mem_1_0.lib_clk <= outer_clk
mem_1_0.lib_addr <= outer_addr
node outer_dout_1_0 = bits(mem_1_0.lib_dout, 7, 0)
mem_1_0.lib_din <= bits(outer_din, 7, 0)
mem_1_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h1")))
node outer_dout_1 = outer_dout_1_0
outer_dout <= mux(eq(outer_addr_sel, UInt<1>("h0")), outer_dout_0, mux(eq(outer_addr_sel, UInt<1>("h1")), outer_dout_1, UInt<1>("h0")))
extmodule awesome_lib_mem :
input lib_clk : Clock
input lib_addr : UInt<10>
input lib_din : UInt<8>
output lib_dout : UInt<8>
input lib_write_en : UInt<1>
input extra_port : UInt<8>
defname = awesome_lib_mem
"""
compile(mem, lib, v, false)
execute(mem, lib, false, outputCustom)
}

468
tapeout/src/test/scala/transforms/macros/SimpleSplitWidth.scala
View File

@@ -1,468 +0,0 @@
//~ package barstools.tapeout.transforms.macros.test
//~ import java.io.File
//~ class SplitWidth2048x16_mrw extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
//~ val lib = new File(macroDir, "lib-2048x8-mrw.json")
//~ val v = new File(testDir, "split_width_2048x16_mrw.v")
//~ val output =
//~ """
//~ circuit name_of_sram_module :
//~ module name_of_sram_module :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<16>
//~ output RW0O : UInt<16>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<2>
//~ inst mem_0_0 of vendor_sram
//~ inst mem_0_1 of vendor_sram
//~ mem_0_0.clock <= clock
//~ mem_0_0.RW0A <= RW0A
//~ node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
//~ mem_0_0.RW0I <= bits(RW0I, 7, 0)
//~ mem_0_0.RW0M <= bits(RW0M, 0, 0)
//~ mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_1.clock <= clock
//~ mem_0_1.RW0A <= RW0A
//~ node RW0O_0_1 = bits(mem_0_1.RW0O, 7, 0)
//~ mem_0_1.RW0I <= bits(RW0I, 15, 8)
//~ mem_0_1.RW0M <= bits(RW0M, 1, 1)
//~ mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
//~ node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
//~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
//~ extmodule vendor_sram :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<8>
//~ output RW0O : UInt<8>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<1>
//~ defname = vendor_sram
//~ """
//~ compile(mem, Some(lib), v, false)
//~ execute(Some(mem), Some(lib), false, output)
//~ }
//~ class SplitWidth2048x16_mrw_Uneven extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
//~ val lib = new File(macroDir, "lib-2048x10-rw.json")
//~ val v = new File(testDir, "split_width_2048x16_mrw_uneven.v")
//~ val output =
//~ """
//~ circuit name_of_sram_module :
//~ module name_of_sram_module :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<16>
//~ output RW0O : UInt<16>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<2>
//~ inst mem_0_0 of vendor_sram
//~ inst mem_0_1 of vendor_sram
//~ mem_0_0.clock <= clock
//~ mem_0_0.RW0A <= RW0A
//~ node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
//~ mem_0_0.RW0I <= bits(RW0I, 7, 0)
//~ mem_0_0.RW0W <= and(and(RW0W, bits(RW0M, 0, 0)), UInt<1>("h1"))
//~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_1.clock <= clock
//~ mem_0_1.RW0A <= RW0A
//~ node RW0O_0_1 = bits(mem_0_1.RW0O, 7, 0)
//~ mem_0_1.RW0I <= bits(RW0I, 15, 8)
//~ mem_0_1.RW0W <= and(and(RW0W, bits(RW0M, 1, 1)), UInt<1>("h1"))
//~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
//~ node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
//~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
//~ extmodule vendor_sram :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<10>
//~ output RW0O : UInt<10>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ defname = vendor_sram
//~ """
//~ compile(mem, Some(lib), v, false)
//~ execute(Some(mem), Some(lib), false, output)
//~ }
//~ class SplitWidth2048x16_mrw_VeryUneven extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-2048x16-mrw-2.json")
//~ val lib = new File(macroDir, "lib-2048x10-rw.json")
//~ val v = new File(testDir, "split_width_2048x16_mrw_very_uneven.v")
//~ val output =
//~ """
//~ circuit name_of_sram_module :
//~ module name_of_sram_module :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<16>
//~ output RW0O : UInt<16>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<8>
//~ inst mem_0_0 of vendor_sram
//~ inst mem_0_1 of vendor_sram
//~ inst mem_0_2 of vendor_sram
//~ inst mem_0_3 of vendor_sram
//~ inst mem_0_4 of vendor_sram
//~ inst mem_0_5 of vendor_sram
//~ inst mem_0_6 of vendor_sram
//~ inst mem_0_7 of vendor_sram
//~ mem_0_0.clock <= clock
//~ mem_0_0.RW0A <= RW0A
//~ node RW0O_0_0 = bits(mem_0_0.RW0O, 1, 0)
//~ mem_0_0.RW0I <= bits(RW0I, 1, 0)
//~ mem_0_0.RW0W <= and(and(RW0W, bits(RW0M, 0, 0)), UInt<1>("h1"))
//~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_1.clock <= clock
//~ mem_0_1.RW0A <= RW0A
//~ node RW0O_0_1 = bits(mem_0_1.RW0O, 1, 0)
//~ mem_0_1.RW0I <= bits(RW0I, 3, 2)
//~ mem_0_1.RW0W <= and(and(RW0W, bits(RW0M, 1, 1)), UInt<1>("h1"))
//~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_2.clock <= clock
//~ mem_0_2.RW0A <= RW0A
//~ node RW0O_0_2 = bits(mem_0_2.RW0O, 1, 0)
//~ mem_0_2.RW0I <= bits(RW0I, 5, 4)
//~ mem_0_2.RW0W <= and(and(RW0W, bits(RW0M, 2, 2)), UInt<1>("h1"))
//~ mem_0_2.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_3.clock <= clock
//~ mem_0_3.RW0A <= RW0A
//~ node RW0O_0_3 = bits(mem_0_3.RW0O, 1, 0)
//~ mem_0_3.RW0I <= bits(RW0I, 7, 6)
//~ mem_0_3.RW0W <= and(and(RW0W, bits(RW0M, 3, 3)), UInt<1>("h1"))
//~ mem_0_3.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_4.clock <= clock
//~ mem_0_4.RW0A <= RW0A
//~ node RW0O_0_4 = bits(mem_0_4.RW0O, 1, 0)
//~ mem_0_4.RW0I <= bits(RW0I, 9, 8)
//~ mem_0_4.RW0W <= and(and(RW0W, bits(RW0M, 4, 4)), UInt<1>("h1"))
//~ mem_0_4.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_5.clock <= clock
//~ mem_0_5.RW0A <= RW0A
//~ node RW0O_0_5 = bits(mem_0_5.RW0O, 1, 0)
//~ mem_0_5.RW0I <= bits(RW0I, 11, 10)
//~ mem_0_5.RW0W <= and(and(RW0W, bits(RW0M, 5, 5)), UInt<1>("h1"))
//~ mem_0_5.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_6.clock <= clock
//~ mem_0_6.RW0A <= RW0A
//~ node RW0O_0_6 = bits(mem_0_6.RW0O, 1, 0)
//~ mem_0_6.RW0I <= bits(RW0I, 13, 12)
//~ mem_0_6.RW0W <= and(and(RW0W, bits(RW0M, 6, 6)), UInt<1>("h1"))
//~ mem_0_6.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_7.clock <= clock
//~ mem_0_7.RW0A <= RW0A
//~ node RW0O_0_7 = bits(mem_0_7.RW0O, 1, 0)
//~ mem_0_7.RW0I <= bits(RW0I, 15, 14)
//~ mem_0_7.RW0W <= and(and(RW0W, bits(RW0M, 7, 7)), UInt<1>("h1"))
//~ mem_0_7.RW0E <= and(RW0E, UInt<1>("h1"))
//~ node RW0O_0 = cat(RW0O_0_7, cat(RW0O_0_6, cat(RW0O_0_5, cat(RW0O_0_4, cat(RW0O_0_3, cat(RW0O_0_2, cat(RW0O_0_1, RW0O_0_0)))))))
//~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
//~ extmodule vendor_sram :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<10>
//~ output RW0O : UInt<10>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ defname = vendor_sram
//~ """
//~ compile(mem, Some(lib), v, false)
//~ execute(Some(mem), Some(lib), false, output)
//~ }
//~ class SplitWidth2048x16_mrw_ReadEnable extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
//~ val lib = new File(macroDir, "lib-2048x8-mrw-re.json")
//~ val v = new File(testDir, "split_width_2048x16_mrw_read_enable.v")
//~ val output =
//~ """
//~ circuit name_of_sram_module :
//~ module name_of_sram_module :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<16>
//~ output RW0O : UInt<16>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<2>
//~ inst mem_0_0 of vendor_sram
//~ inst mem_0_1 of vendor_sram
//~ mem_0_0.clock <= clock
//~ mem_0_0.RW0A <= RW0A
//~ node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
//~ mem_0_0.RW0I <= bits(RW0I, 7, 0)
//~ mem_0_0.RW0R <= not(and(not(RW0W), UInt<1>("h1")))
//~ mem_0_0.RW0M <= bits(RW0M, 0, 0)
//~ mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_1.clock <= clock
//~ mem_0_1.RW0A <= RW0A
//~ node RW0O_0_1 = bits(mem_0_1.RW0O, 7, 0)
//~ mem_0_1.RW0I <= bits(RW0I, 15, 8)
//~ mem_0_1.RW0R <= not(and(not(RW0W), UInt<1>("h1")))
//~ mem_0_1.RW0M <= bits(RW0M, 1, 1)
//~ mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
//~ node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
//~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
//~ extmodule vendor_sram :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<8>
//~ output RW0O : UInt<8>
//~ input RW0E : UInt<1>
//~ input RW0R : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<1>
//~ defname = vendor_sram
//~ """
//~ compile(mem, Some(lib), v, false)
//~ execute(Some(mem), Some(lib), false, output)
//~ }
//~ class SplitWidth2048x16_n28 extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
//~ val lib = new File(macroDir, "lib-2048x16-n28.json")
//~ val v = new File(testDir, "split_width_2048x16_n28.v")
//~ val output =
//~ """
//~ circuit name_of_sram_module :
//~ module name_of_sram_module :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<16>
//~ output RW0O : UInt<16>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<2>
//~ inst mem_0_0 of vendor_sram_16
//~ mem_0_0.clock <= clock
//~ mem_0_0.RW0A <= RW0A
//~ node RW0O_0_0 = bits(mem_0_0.RW0O, 15, 0)
//~ mem_0_0.RW0I <= bits(RW0I, 15, 0)
//~ mem_0_0.RW0M <= cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), bits(RW0M, 0, 0))))))))))))))))
//~ mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
//~ node RW0O_0 = RW0O_0_0
//~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
//~ extmodule vendor_sram_16 :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<16>
//~ output RW0O : UInt<16>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<16>
//~ defname = vendor_sram_16
//~ """
//~ compile(mem, Some(lib), v, false)
//~ execute(Some(mem), Some(lib), false, output)
//~ }
//~ class SplitWidth2048x20_mrw_UnevenMask extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-2048x20-mrw.json")
//~ val lib = new File(macroDir, "lib-2048x8-mrw.json")
//~ val v = new File(testDir, "split_width_2048x20_mrw_uneven_mask.v")
//~ val output =
//~ """
//~ circuit name_of_sram_module :
//~ module name_of_sram_module :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<20>
//~ output RW0O : UInt<20>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<2>
//~ inst mem_0_0 of vendor_sram
//~ inst mem_0_1 of vendor_sram
//~ inst mem_0_2 of vendor_sram
//~ inst mem_0_3 of vendor_sram
//~ mem_0_0.clock <= clock
//~ mem_0_0.RW0A <= RW0A
//~ node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
//~ mem_0_0.RW0I <= bits(RW0I, 7, 0)
//~ mem_0_0.RW0M <= bits(RW0M, 0, 0)
//~ mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_1.clock <= clock
//~ mem_0_1.RW0A <= RW0A
//~ node RW0O_0_1 = bits(mem_0_1.RW0O, 1, 0)
//~ mem_0_1.RW0I <= bits(RW0I, 9, 8)
//~ mem_0_1.RW0M <= bits(RW0M, 0, 0)
//~ mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_2.clock <= clock
//~ mem_0_2.RW0A <= RW0A
//~ node RW0O_0_2 = bits(mem_0_2.RW0O, 7, 0)
//~ mem_0_2.RW0I <= bits(RW0I, 17, 10)
//~ mem_0_2.RW0M <= bits(RW0M, 1, 1)
//~ mem_0_2.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_2.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_3.clock <= clock
//~ mem_0_3.RW0A <= RW0A
//~ node RW0O_0_3 = bits(mem_0_3.RW0O, 1, 0)
//~ mem_0_3.RW0I <= bits(RW0I, 19, 18)
//~ mem_0_3.RW0M <= bits(RW0M, 1, 1)
//~ mem_0_3.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_3.RW0E <= and(RW0E, UInt<1>("h1"))
//~ node RW0O_0 = cat(RW0O_0_3, cat(RW0O_0_2, cat(RW0O_0_1, RW0O_0_0)))
//~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
//~ extmodule vendor_sram :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<8>
//~ output RW0O : UInt<8>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<1>
//~ defname = vendor_sram
//~ """
//~ compile(mem, Some(lib), v, false)
//~ execute(Some(mem), Some(lib), false, output)
//~ }
//~ class SplitWidth24x52 extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-24x52-r-w.json")
//~ val lib = new File(macroDir, "lib-32x32-2rw.json")
//~ val v = new File(testDir, "split_width_24x52.v")
//~ val output =
//~ """
//~ circuit entries_info_ext :
//~ module entries_info_ext :
//~ input R0_clk : Clock
//~ input R0_addr : UInt<5>
//~ output R0_data : UInt<52>
//~ input R0_en : UInt<1>
//~ input W0_clk : Clock
//~ input W0_addr : UInt<5>
//~ input W0_data : UInt<52>
//~ input W0_en : UInt<1>
//~ inst mem_0_0 of SRAM2RW32x32
//~ inst mem_0_1 of SRAM2RW32x32
//~ mem_0_0.CE1 <= W0_clk
//~ mem_0_0.A1 <= W0_addr
//~ mem_0_0.I1 <= bits(W0_data, 31, 0)
//~ mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_0.CSB1 <= not(and(W0_en, UInt<1>("h1")))
//~ mem_0_1.CE1 <= W0_clk
//~ mem_0_1.A1 <= W0_addr
//~ mem_0_1.I1 <= bits(W0_data, 51, 32)
//~ mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_1.CSB1 <= not(and(W0_en, UInt<1>("h1")))
//~ mem_0_0.CE2 <= R0_clk
//~ mem_0_0.A2 <= R0_addr
//~ node R0_data_0_0 = bits(mem_0_0.O2, 31, 0)
//~ mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
//~ mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_0.CSB2 <= not(and(R0_en, UInt<1>("h1")))
//~ mem_0_1.CE2 <= R0_clk
//~ mem_0_1.A2 <= R0_addr
//~ node R0_data_0_1 = bits(mem_0_1.O2, 19, 0)
//~ mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
//~ mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
//~ mem_0_1.CSB2 <= not(and(R0_en, UInt<1>("h1")))
//~ node R0_data_0 = cat(R0_data_0_1, R0_data_0_0)
//~ R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0"))
//~ extmodule SRAM2RW32x32 :
//~ input CE1 : Clock
//~ input A1 : UInt<5>
//~ input I1 : UInt<32>
//~ output O1 : UInt<32>
//~ input CSB1 : UInt<1>
//~ input OEB1 : UInt<1>
//~ input WEB1 : UInt<1>
//~ input CE2 : Clock
//~ input A2 : UInt<5>
//~ input I2 : UInt<32>
//~ output O2 : UInt<32>
//~ input CSB2 : UInt<1>
//~ input OEB2 : UInt<1>
//~ input WEB2 : UInt<1>
//~ defname = SRAM2RW32x32
//~ """
//~ compile(mem, Some(lib), v, false)
//~ execute(Some(mem), Some(lib), false, output)
//~ }
//~ class SplitWidth32x160 extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-32x160-mrw.json")
//~ val lib = new File(macroDir, "lib-32x80-mrw.json")
//~ val v = new File(testDir, "split_width_32x160.v")
//~ val output =
//~ """
//~ circuit name_of_sram_module :
//~ module name_of_sram_module :
//~ input clock : Clock
//~ input RW0A : UInt<5>
//~ input RW0I : UInt<160>
//~ output RW0O : UInt<160>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<8>
//~ inst mem_0_0 of vendor_sram
//~ inst mem_0_1 of vendor_sram
//~ mem_0_0.clock <= clock
//~ mem_0_0.RW0A <= RW0A
//~ node RW0O_0_0 = bits(mem_0_0.RW0O, 79, 0)
//~ mem_0_0.RW0I <= bits(RW0I, 79, 0)
//~ mem_0_0.RW0M <= cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), bits(RW0M, 0, 0))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
//~ mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
//~ mem_0_1.clock <= clock
//~ mem_0_1.RW0A <= RW0A
//~ node RW0O_0_1 = bits(mem_0_1.RW0O, 79, 0)
//~ mem_0_1.RW0I <= bits(RW0I, 159, 80)
//~ mem_0_1.RW0M <= cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), bits(RW0M, 4, 4))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
//~ mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
//~ mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
//~ node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
//~ RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
//~ extmodule vendor_sram :
//~ input clock : Clock
//~ input RW0A : UInt<5>
//~ input RW0I : UInt<80>
//~ output RW0O : UInt<80>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<80>
//~ defname = vendor_sram
//~ """
//~ compile(mem, Some(lib), v, false)
//~ execute(Some(mem), Some(lib), false, output)
//~ }

333
tapeout/src/test/scala/transforms/macros/SynFlops.scala
View File

@@ -1,333 +0,0 @@
//~ package barstools.tapeout.transforms.macros
//~ import java.io.File
//~ class Synflops2048x16_mrw extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-2048x16-mrw.json")
//~ val v = new File(testDir, "syn_flops_2048x16_mrw.v")
//~ val output =
//~ """
//~ circuit name_of_sram_module :
//~ module name_of_sram_module :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<16>
//~ output RW0O : UInt<16>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<2>
//~ mem ram :
//~ data-type => UInt<8>[2]
//~ depth => 2048
//~ read-latency => 0
//~ write-latency => 1
//~ reader => R_0
//~ writer => W_0
//~ read-under-write => undefined
//~ reg R_0_addr_reg : UInt<11>, clock with :
//~ reset => (UInt<1>("h0"), R_0_addr_reg)
//~ ram.R_0.clk <= clock
//~ ram.R_0.addr <= R_0_addr_reg
//~ ram.R_0.en <= RW0E
//~ RW0O <= cat(ram.R_0.data[1], ram.R_0.data[0])
//~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
//~ ram.W_0.clk <= clock
//~ ram.W_0.addr <= RW0A
//~ ram.W_0.en <= and(RW0E, RW0W)
//~ ram.W_0.data[0] <= bits(RW0I, 7, 0)
//~ ram.W_0.data[1] <= bits(RW0I, 15, 8)
//~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
//~ ram.W_0.mask[1] <= bits(RW0M, 1, 1)
//~ """
//~ compile(mem, None, v, true)
//~ execute(Some(mem), None, true, output)
//~ }
//~ class Synflops2048x8_r_mw extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "mem-2048x8-r-mw.json")
//~ val v = new File(testDir, "syn_flops_2048x8_r_mw.v")
//~ val output =
//~ """
//~ circuit name_of_sram_module :
//~ module name_of_sram_module :
//~ input clock : Clock
//~ input W0A : UInt<11>
//~ input W0I : UInt<8>
//~ input W0E : UInt<1>
//~ input W0M : UInt<1>
//~ input clock : Clock
//~ input R0A : UInt<11>
//~ output R0O : UInt<8>
//~ mem ram :
//~ data-type => UInt<8>[1]
//~ depth => 2048
//~ read-latency => 0
//~ write-latency => 1
//~ reader => R_0
//~ writer => W_0
//~ read-under-write => undefined
//~ reg R_0_addr_reg : UInt<11>, clock with :
//~ reset => (UInt<1>("h0"), R_0_addr_reg)
//~ ram.R_0.clk <= clock
//~ ram.R_0.addr <= R_0_addr_reg
//~ ram.R_0.en <= UInt<1>("h1")
//~ R0O <= ram.R_0.data[0]
//~ R_0_addr_reg <= mux(UInt<1>("h1"), R0A, R_0_addr_reg)
//~ ram.W_0.clk <= clock
//~ ram.W_0.addr <= W0A
//~ ram.W_0.en <= W0E
//~ ram.W_0.data[0] <= bits(W0I, 7, 0)
//~ ram.W_0.mask[0] <= bits(W0M, 0, 0)
//~ """
//~ compile(mem, None, v, true)
//~ execute(Some(mem), None, true, output)
//~ }
//~ class Synflops2048x10_rw extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "lib-2048x10-rw.json")
//~ val v = new File(testDir, "syn_flops_2048x10_rw.v")
//~ val output =
//~ """
//~ circuit vendor_sram :
//~ module vendor_sram :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<10>
//~ output RW0O : UInt<10>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ mem ram :
//~ data-type => UInt<10>
//~ depth => 2048
//~ read-latency => 0
//~ write-latency => 1
//~ reader => R_0
//~ writer => W_0
//~ read-under-write => undefined
//~ reg R_0_addr_reg : UInt<11>, clock with :
//~ reset => (UInt<1>("h0"), R_0_addr_reg)
//~ ram.R_0.clk <= clock
//~ ram.R_0.addr <= R_0_addr_reg
//~ ram.R_0.en <= RW0E
//~ RW0O <= ram.R_0.data
//~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
//~ ram.W_0.clk <= clock
//~ ram.W_0.addr <= RW0A
//~ ram.W_0.en <= and(RW0E, RW0W)
//~ ram.W_0.data <= RW0I
//~ ram.W_0.mask <= UInt<1>("h1")
//~ """
//~ compile(mem, None, v, true)
//~ execute(Some(mem), None, true, output)
//~ }
//~ class Synflops2048x8_mrw_re extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "lib-2048x8-mrw-re.json")
//~ val v = new File(testDir, "syn_flops_2048x8_mrw_re.v")
//~ val output =
//~ """
//~ circuit vendor_sram :
//~ module vendor_sram :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<8>
//~ output RW0O : UInt<8>
//~ input RW0E : UInt<1>
//~ input RW0R : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<1>
//~ mem ram :
//~ data-type => UInt<8>[1]
//~ depth => 2048
//~ read-latency => 0
//~ write-latency => 1
//~ reader => R_0
//~ writer => W_0
//~ read-under-write => undefined
//~ reg R_0_addr_reg : UInt<11>, clock with :
//~ reset => (UInt<1>("h0"), R_0_addr_reg)
//~ ram.R_0.clk <= clock
//~ ram.R_0.addr <= R_0_addr_reg
//~ ram.R_0.en <= and(RW0E, not(RW0R))
//~ RW0O <= ram.R_0.data[0]
//~ R_0_addr_reg <= mux(and(RW0E, not(RW0R)), RW0A, R_0_addr_reg)
//~ ram.W_0.clk <= clock
//~ ram.W_0.addr <= RW0A
//~ ram.W_0.en <= and(RW0E, RW0W)
//~ ram.W_0.data[0] <= bits(RW0I, 7, 0)
//~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
//~ """
//~ compile(mem, None, v, true)
//~ execute(Some(mem), None, true, output)
//~ }
//~ class Synflops2048x16_n28 extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "lib-2048x16-n28.json")
//~ val v = new File(testDir, "syn_flops_2048x16_n28.v")
//~ val output =
//~ """
//~ circuit vendor_sram_4 :
//~ module vendor_sram_16 :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<16>
//~ output RW0O : UInt<16>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<16>
//~ mem ram :
//~ data-type => UInt<1>[16]
//~ depth => 2048
//~ read-latency => 0
//~ write-latency => 1
//~ reader => R_0
//~ writer => W_0
//~ read-under-write => undefined
//~ reg R_0_addr_reg : UInt<11>, clock with :
//~ reset => (UInt<1>("h0"), R_0_addr_reg)
//~ ram.R_0.clk <= clock
//~ ram.R_0.addr <= R_0_addr_reg
//~ ram.R_0.en <= RW0E
//~ RW0O <= cat(ram.R_0.data[15], cat(ram.R_0.data[14], cat(ram.R_0.data[13], cat(ram.R_0.data[12], cat(ram.R_0.data[11], cat(ram.R_0.data[10], cat(ram.R_0.data[9], cat(ram.R_0.data[8], cat(ram.R_0.data[7], cat(ram.R_0.data[6], cat(ram.R_0.data[5], cat(ram.R_0.data[4], cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))))))))))))))
//~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
//~ ram.W_0.clk <= clock
//~ ram.W_0.addr <= RW0A
//~ ram.W_0.en <= and(RW0E, RW0W)
//~ ram.W_0.data[0] <= bits(RW0I, 0, 0)
//~ ram.W_0.data[1] <= bits(RW0I, 1, 1)
//~ ram.W_0.data[2] <= bits(RW0I, 2, 2)
//~ ram.W_0.data[3] <= bits(RW0I, 3, 3)
//~ ram.W_0.data[4] <= bits(RW0I, 4, 4)
//~ ram.W_0.data[5] <= bits(RW0I, 5, 5)
//~ ram.W_0.data[6] <= bits(RW0I, 6, 6)
//~ ram.W_0.data[7] <= bits(RW0I, 7, 7)
//~ ram.W_0.data[8] <= bits(RW0I, 8, 8)
//~ ram.W_0.data[9] <= bits(RW0I, 9, 9)
//~ ram.W_0.data[10] <= bits(RW0I, 10, 10)
//~ ram.W_0.data[11] <= bits(RW0I, 11, 11)
//~ ram.W_0.data[12] <= bits(RW0I, 12, 12)
//~ ram.W_0.data[13] <= bits(RW0I, 13, 13)
//~ ram.W_0.data[14] <= bits(RW0I, 14, 14)
//~ ram.W_0.data[15] <= bits(RW0I, 15, 15)
//~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
//~ ram.W_0.mask[1] <= bits(RW0M, 1, 1)
//~ ram.W_0.mask[2] <= bits(RW0M, 2, 2)
//~ ram.W_0.mask[3] <= bits(RW0M, 3, 3)
//~ ram.W_0.mask[4] <= bits(RW0M, 4, 4)
//~ ram.W_0.mask[5] <= bits(RW0M, 5, 5)
//~ ram.W_0.mask[6] <= bits(RW0M, 6, 6)
//~ ram.W_0.mask[7] <= bits(RW0M, 7, 7)
//~ ram.W_0.mask[8] <= bits(RW0M, 8, 8)
//~ ram.W_0.mask[9] <= bits(RW0M, 9, 9)
//~ ram.W_0.mask[10] <= bits(RW0M, 10, 10)
//~ ram.W_0.mask[11] <= bits(RW0M, 11, 11)
//~ ram.W_0.mask[12] <= bits(RW0M, 12, 12)
//~ ram.W_0.mask[13] <= bits(RW0M, 13, 13)
//~ ram.W_0.mask[14] <= bits(RW0M, 14, 14)
//~ ram.W_0.mask[15] <= bits(RW0M, 15, 15)
//~ module vendor_sram_4 :
//~ input clock : Clock
//~ input RW0A : UInt<11>
//~ input RW0I : UInt<4>
//~ output RW0O : UInt<4>
//~ input RW0E : UInt<1>
//~ input RW0W : UInt<1>
//~ input RW0M : UInt<4>
//~ mem ram :
//~ data-type => UInt<1>[4]
//~ depth => 2048
//~ read-latency => 0
//~ write-latency => 1
//~ reader => R_0
//~ writer => W_0
//~ read-under-write => undefined
//~ reg R_0_addr_reg : UInt<11>, clock with :
//~ reset => (UInt<1>("h0"), R_0_addr_reg)
//~ ram.R_0.clk <= clock
//~ ram.R_0.addr <= R_0_addr_reg
//~ ram.R_0.en <= RW0E
//~ RW0O <= cat(ram.R_0.data[3], cat(ram.R_0.data[2], cat(ram.R_0.data[1], ram.R_0.data[0])))
//~ R_0_addr_reg <= mux(RW0E, RW0A, R_0_addr_reg)
//~ ram.W_0.clk <= clock
//~ ram.W_0.addr <= RW0A
//~ ram.W_0.en <= and(RW0E, RW0W)
//~ ram.W_0.data[0] <= bits(RW0I, 0, 0)
//~ ram.W_0.data[1] <= bits(RW0I, 1, 1)
//~ ram.W_0.data[2] <= bits(RW0I, 2, 2)
//~ ram.W_0.data[3] <= bits(RW0I, 3, 3)
//~ ram.W_0.mask[0] <= bits(RW0M, 0, 0)
//~ ram.W_0.mask[1] <= bits(RW0M, 1, 1)
//~ ram.W_0.mask[2] <= bits(RW0M, 2, 2)
//~ ram.W_0.mask[3] <= bits(RW0M, 3, 3)
//~ """
//~ compile(mem, None, v, true)
//~ execute(Some(mem), None, true, output)
//~ }
//~ class Synflops32x32_2rw extends MacroCompilerSpec {
//~ val mem = new File(macroDir, "lib-32x32-2rw.json")
//~ val v = new File(testDir, "syn_flops_32x32_2rw.v")
//~ val output =
//~ """
//~ circuit SRAM2RW32x32 :
//~ module SRAM2RW32x32 :
//~ input CE1 : Clock
//~ input A1 : UInt<5>
//~ input I1 : UInt<32>
//~ output O1 : UInt<32>
//~ input CSB1 : UInt<1>
//~ input OEB1 : UInt<1>
//~ input WEB1 : UInt<1>
//~ input CE2 : Clock
//~ input A2 : UInt<5>
//~ input I2 : UInt<32>
//~ output O2 : UInt<32>
//~ input CSB2 : UInt<1>
//~ input OEB2 : UInt<1>
//~ input WEB2 : UInt<1>
//~ mem ram :
//~ data-type => UInt<32>
//~ depth => 32
//~ read-latency => 0
//~ write-latency => 1
//~ reader => R_0
//~ reader => R_1
//~ writer => W_0
//~ writer => W_1
//~ read-under-write => undefined
//~ reg R_0_addr_reg : UInt<5>, CE1 with :
//~ reset => (UInt<1>("h0"), R_0_addr_reg)
//~ ram.R_0.clk <= CE1
//~ ram.R_0.addr <= R_0_addr_reg
//~ ram.R_0.en <= and(not(CSB1), not(OEB1))
//~ O1 <= ram.R_0.data
//~ R_0_addr_reg <= mux(and(not(CSB1), not(OEB1)), A1, R_0_addr_reg)
//~ reg R_1_addr_reg : UInt<5>, CE2 with :
//~ reset => (UInt<1>("h0"), R_1_addr_reg)
//~ ram.R_1.clk <= CE2
//~ ram.R_1.addr <= R_1_addr_reg
//~ ram.R_1.en <= and(not(CSB2), not(OEB2))
//~ O2 <= ram.R_1.data
//~ R_1_addr_reg <= mux(and(not(CSB2), not(OEB2)), A2, R_1_addr_reg)
//~ ram.W_0.clk <= CE1
//~ ram.W_0.addr <= A1
//~ ram.W_0.en <= and(not(CSB1), not(WEB1))
//~ ram.W_0.data <= I1
//~ ram.W_0.mask <= UInt<1>("h1")
//~ ram.W_1.clk <= CE2
//~ ram.W_1.addr <= A2
//~ ram.W_1.en <= and(not(CSB2), not(WEB2))
//~ ram.W_1.data <= I2
//~ ram.W_1.mask <= UInt<1>("h1")
//~ """
//~ compile(mem, None, v, true)
//~ execute(Some(mem), None, true, output)
//~ }