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restructure macros for better submoduling

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This commit is contained in:
Donggyu Kim
2017-07-25 13:48:58 -07:00
committed by edwardcwang
parent 607e810b1d
commit 9de1f5f2c0
28 changed files with 27 additions and 26 deletions
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186
macros/src/test/resources/mylib.json Normal file
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[
{
"type": "sram",
"name": "SRAM1RW1024x8",
"width": 8,
"depth": 1024,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW512x32",
"width": 32,
"depth": 512,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW64x128",
"width": 128,
"depth": 64,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW64x32",
"width": 32,
"depth": 64,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW64x8",
"width": 8,
"depth": 64,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW512x8",
"width": 8,
"depth": 512,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM2RW64x32",
"width": 32,
"depth": 64,
"ports": [
{
"address port name": "A1",
"address port polarity": "active high",
"clock port name": "CE1",
"clock port polarity": "positive edge",
"write enable port name": "WEB1",
"write enable port polarity": "active low",
"read enable port name": "OEB1",
"read enable port polarity": "active low",
"chip enable port name": "CEB1",
"chip enable port polarity": "active low",
"output port name": "O1",
"output port polarity": "active high",
"input port name": "I1",
"input port polarity": "active high"
},
{
"address port name": "A2",
"address port polarity": "active high",
"clock port name": "CE2",
"clock port polarity": "positive edge",
"write enable port name": "WEB2",
"write enable port polarity": "active low",
"read enable port name": "OEB2",
"read enable port polarity": "active low",
"chip enable port name": "CEB2",
"chip enable port polarity": "active low",
"output port name": "O2",
"output port polarity": "active high",
"input port name": "I2",
"input port polarity": "active high"
}
]
}
]