restructure macros for better submoduling

2017-07-25 13:48:58 -07:00
parent 607e810b1d
commit 9de1f5f2c0
28 changed files with 27 additions and 26 deletions
--- a/macros/src/test/resources/lib-32x80-mrw.json
+++ b/macros/src/test/resources/lib-32x80-mrw.json
@@ -0,0 +1,27 @@
+[
+  {
+    "type": "sram",
+    "name": "vendor_sram",
+    "depth": 32,
+    "width": 80,
+    "ports": [
+      {
+        "clock port name": "clock",
+        "mask granularity": 1,
+        "output port name": "RW0O",
+        "input port name": "RW0I",
+        "address port name": "RW0A",
+        "mask port name": "RW0M",
+        "chip enable port name": "RW0E",
+        "write enable port name": "RW0W",
+        "clock port polarity": "positive edge",
+        "output port polarity": "active high",
+        "input port polarity": "active high",
+        "address port polarity": "active high",
+        "mask port polarity": "active high",
+        "chip enable port polarity": "active high",
+        "write enable port polarity": "active high"
+      }
+    ]
+  }
+]