restructure macros for better submoduling
This commit is contained in:
Donggyu Kim
429
macros/src/main/scala/MacroCompiler.scala
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429
macros/src/main/scala/MacroCompiler.scala
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@@ -0,0 +1,429 @@
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// See LICENSE for license details.
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package barstools.macros
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import firrtl._
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import firrtl.ir._
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import firrtl.PrimOps
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import firrtl.Utils._
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import firrtl.annotations._
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import firrtl.CompilerUtils.getLoweringTransforms
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import mdf.macrolib.{PolarizedPort, PortPolarity}
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import scala.collection.mutable.{ArrayBuffer, HashMap}
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import java.io.{File, FileWriter}
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import Utils._
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object MacroCompilerAnnotation {
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def apply(c: String, mem: String, lib: Option[String], synflops: Boolean) = {
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Annotation(CircuitName(c), classOf[MacroCompilerTransform],
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s"${mem} %s ${synflops}".format(lib map (_.toString) getOrElse ""))
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}
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private val matcher = "([^ ]+) ([^ ]*) (true|false)".r
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def unapply(a: Annotation) = a match {
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case Annotation(CircuitName(c), t, matcher(mem, lib, synflops)) if t == classOf[MacroCompilerTransform] =>
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Some((c, Some(mem), if (lib.isEmpty) None else Some(lib), synflops.toBoolean))
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case _ => None
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}
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}
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class MacroCompilerPass(mems: Option[Seq[Macro]],
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libs: Option[Seq[Macro]]) extends firrtl.passes.Pass {
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def compile(mem: Macro, lib: Macro): Option[(Module, ExtModule)] = {
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val pairedPorts = mem.sortedPorts zip lib.sortedPorts
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// Parallel mapping
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val pairs = ArrayBuffer[(BigInt, BigInt)]()
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var last = 0
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for (i <- 0 until mem.src.width) {
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if (i <= last + 1) {
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/* Palmer: Every memory is going to have to fit at least a single bit. */
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// continue
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} else if ((i - last) % lib.src.width.toInt == 0) {
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/* Palmer: It's possible that we rolled over a memory's width here,
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if so generate one. */
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pairs += ((last, i-1))
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last = i
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} else {
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/* Palmer: FIXME: This is a mess, I must just be super confused. */
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for ((memPort, libPort) <- pairedPorts) {
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(memPort.src.maskGran, libPort.src.maskGran) match {
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case (_, Some(p)) if p == 1 => // continue
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case (Some(p), _) if i % p == 0 =>
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pairs += ((last, i-1))
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last = i
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case (_, None) => // continue
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case (_, Some(p)) if p == lib.src.width => // continue
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case _ =>
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System.err println "Bit-mask (or unmasked) target memories are supported only"
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return None
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}
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}
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}
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}
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pairs += ((last, mem.src.width.toInt - 1))
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// Serial mapping
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val stmts = ArrayBuffer[Statement]()
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val selects = HashMap[String, Expression]()
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val outputs = HashMap[String, ArrayBuffer[(Expression, Expression)]]()
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/* Palmer: If we've got a parallel memory then we've got to take the
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* address bits into account. */
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if (mem.src.depth > lib.src.depth) {
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mem.src.ports foreach { port =>
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val high = ceilLog2(mem.src.depth)
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val low = ceilLog2(lib.src.depth)
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val ref = WRef(port.address.name)
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val name = s"${ref.name}_sel"
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selects(ref.name) = WRef(name, UIntType(IntWidth(high-low)))
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stmts += DefNode(NoInfo, name, bits(ref, high-1, low))
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}
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}
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for ((off, i) <- (0 until mem.src.depth by lib.src.depth).zipWithIndex) {
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for (j <- pairs.indices) {
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val name = s"mem_${i}_${j}"
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stmts += WDefInstance(NoInfo, name, lib.src.name, lib.tpe)
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// connect extra ports
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stmts ++= lib.extraPorts map { case (portName, portValue) =>
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Connect(NoInfo, WSubField(WRef(name), portName), portValue)
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}
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}
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for ((memPort, libPort) <- pairedPorts) {
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val addrMatch = selects get memPort.src.address.name match {
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case None => one
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case Some(addr) =>
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val index = UIntLiteral(i, IntWidth(bitWidth(addr.tpe)))
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DoPrim(PrimOps.Eq, Seq(addr, index), Nil, index.tpe)
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}
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def andAddrMatch(e: Expression) = and(e, addrMatch)
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val cats = ArrayBuffer[Expression]()
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for (((low, high), j) <- pairs.zipWithIndex) {
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val inst = WRef(s"mem_${i}_${j}", lib.tpe)
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def connectPorts2(mem: Expression,
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lib: String,
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polarity: Option[PortPolarity]): Statement =
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Connect(NoInfo, WSubField(inst, lib), portToExpression(mem, polarity))
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def connectPorts(mem: Expression,
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lib: String,
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polarity: PortPolarity): Statement =
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connectPorts2(mem, lib, Some(polarity))
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// Clock port mapping
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/* Palmer: FIXME: I don't handle memories with read/write clocks yet. */
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stmts += connectPorts(WRef(memPort.src.clock.name),
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libPort.src.clock.name,
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libPort.src.clock.polarity)
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// Adress port mapping
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/* Palmer: The address port to a memory is just the low-order bits of
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* the top address. */
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stmts += connectPorts(WRef(memPort.src.address.name),
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libPort.src.address.name,
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libPort.src.address.polarity)
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// Output port mapping
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(memPort.src.output, libPort.src.output) match {
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case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) =>
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/* Palmer: In order to produce the output of a memory we need to cat
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* together a bunch of narrower memories, which can only be
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* done after generating all the memories. This saves up the
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* output statements for later. */
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val name = s"${mem}_${i}_${j}"
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val exp = portToExpression(bits(WSubField(inst, lib), high-low, 0), Some(lib_polarity))
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stmts += DefNode(NoInfo, name, exp)
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cats += WRef(name)
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case (None, Some(lib)) =>
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/* Palmer: If the inner memory has an output port but the outer
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* one doesn't then it's safe to just leave the outer
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* port floating. */
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case (None, None) =>
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/* Palmer: If there's no output ports at all (ie, read-only
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* port on the memory) then just don't worry about it,
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* there's nothing to do. */
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case (Some(PolarizedPort(mem, _)), None) =>
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System.err println "WARNING: Unable to match output ports on memory"
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System.err println s" outer output port: ${mem}"
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return None
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}
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// Input port mapping
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(memPort.src.input, libPort.src.input) match {
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case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) =>
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/* Palmer: The input port to a memory just needs to happen in parallel,
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* this does a part select to narrow the memory down. */
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stmts += connectPorts(bits(WRef(mem), high, low), lib, lib_polarity)
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case (None, Some(lib)) =>
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/* Palmer: If the inner memory has an input port but the other
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* one doesn't then it's safe to just leave the inner
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* port floating. This should be handled by the
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* default value of the write enable, so nothing should
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* every make it into the memory. */
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case (None, None) =>
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/* Palmer: If there's no input ports at all (ie, read-only
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* port on the memory) then just don't worry about it,
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* there's nothing to do. */
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case (Some(PolarizedPort(mem, _)), None) =>
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System.err println "WARNING: Unable to match input ports on memory"
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System.err println s" outer input port: ${mem}"
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return None
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}
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// Mask port mapping
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val memMask = memPort.src.maskPort match {
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case Some(PolarizedPort(mem, _)) =>
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/* Palmer: The bits from the outer memory's write mask that will be
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* used as the write mask for this inner memory. */
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if (libPort.src.effectiveMaskGran == libPort.src.width) {
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bits(WRef(mem), low / memPort.src.effectiveMaskGran)
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} else {
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require(libPort.src.effectiveMaskGran == 1, "only single-bit mask supported for now")
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require(isPowerOfTwo(memPort.src.effectiveMaskGran), "only powers of two masks supported for now")
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require(isPowerOfTwo(libPort.src.effectiveMaskGran), "only powers of two masks supported for now")
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cat(((low to high) map (i => bits(WRef(mem), i / memPort.src.effectiveMaskGran))).reverse)
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}
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case None =>
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/* Palmer: If there is no input port on the source memory port
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* then we don't ever want to turn on this write
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* enable. Otherwise, we just _always_ turn on the
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* write enable port on the inner memory. */
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if (libPort.src.maskPort.isEmpty) one
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else {
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val width = libPort.src.width / libPort.src.effectiveMaskGran
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val value = (BigInt(1) << width.toInt) - 1
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UIntLiteral(value, IntWidth(width))
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}
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}
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// Write enable port mapping
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val memWriteEnable = memPort.src.writeEnable match {
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case Some(PolarizedPort(mem, _)) =>
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/* Palmer: The outer memory's write enable port, or a constant 1 if
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* there isn't a write enable port. */
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WRef(mem)
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case None =>
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/* Palmer: If there is no input port on the source memory port
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* then we don't ever want to turn on this write
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* enable. Otherwise, we just _always_ turn on the
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* write enable port on the inner memory. */
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if (memPort.src.input.isEmpty) zero else one
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}
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// Chip enable port mapping
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val memChipEnable = memPort.src.chipEnable match {
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case Some(PolarizedPort(mem, _)) => WRef(mem)
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case None => one
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}
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// Read enable port mapping
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/* Palmer: It's safe to ignore read enables, but we pass them through
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* to the vendor memory if there's a port on there that
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* implements the read enables. */
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(memPort.src.readEnable, libPort.src.readEnable) match {
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case (_, None) =>
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case (Some(PolarizedPort(mem, _)), Some(PolarizedPort(lib, lib_polarity))) =>
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stmts += connectPorts(andAddrMatch(WRef(mem)), lib, lib_polarity)
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case (None, Some(PolarizedPort(lib, lib_polarity))) =>
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stmts += connectPorts(andAddrMatch(not(memWriteEnable)), lib, lib_polarity)
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}
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/* Palmer: This is actually the memory compiler: it figures out how to
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* implement the outer memory's collection of ports using what
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* the inner memory has availiable. */
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((libPort.src.maskPort, libPort.src.writeEnable, libPort.src.chipEnable): @unchecked) match {
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case (Some(PolarizedPort(mask, mask_polarity)), Some(PolarizedPort(we, we_polarity)), Some(PolarizedPort(en, en_polarity))) =>
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/* Palmer: This is the simple option: every port exists. */
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stmts += connectPorts(memMask, mask, mask_polarity)
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stmts += connectPorts(andAddrMatch(memWriteEnable), we, we_polarity)
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stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity)
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case (Some(PolarizedPort(mask, mask_polarity)), Some(PolarizedPort(we, we_polarity)), None) =>
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/* Palmer: If we don't have a chip enable but do have mask ports. */
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stmts += connectPorts(memMask, mask, mask_polarity)
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stmts += connectPorts(andAddrMatch(and(memWriteEnable, memChipEnable)),
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we, mask_polarity)
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case (None, Some(PolarizedPort(we, we_polarity)), chipEnable) if bitWidth(memMask.tpe) == 1 =>
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/* Palmer: If we're expected to provide mask ports without a
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* memory that actually has them then we can use the
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* write enable port instead of the mask port. */
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stmts += connectPorts(andAddrMatch(and(memWriteEnable, memMask)),
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we, we_polarity)
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chipEnable match {
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case Some(PolarizedPort(en, en_polarity)) => {
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stmts += connectPorts(andAddrMatch(memChipEnable), en, en_polarity)
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}
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case _ => // TODO: do we care about the case where mem has chipEnable but lib doesn't?
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}
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case (None, Some(PolarizedPort(we, we_polarity)), Some(PolarizedPort(en, en_polarity))) =>
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// TODO
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System.err.println("cannot emulate multi-bit mask ports with write enable")
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return None
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case (None, None, None) =>
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/* Palmer: There's nothing to do here since there aren't any
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* ports to match up. */
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}
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}
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// Cat macro outputs for selection
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memPort.src.output match {
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case Some(PolarizedPort(mem, _)) if cats.nonEmpty =>
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val name = s"${mem}_${i}"
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stmts += DefNode(NoInfo, name, cat(cats.toSeq.reverse))
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(outputs getOrElseUpdate (mem, ArrayBuffer[(Expression, Expression)]())) +=
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(addrMatch -> WRef(name))
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case _ =>
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}
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}
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}
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// Connect mem outputs
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mem.src.ports foreach { port =>
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port.output match {
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case Some(PolarizedPort(mem, _)) => outputs get mem match {
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case Some(select) =>
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val output = (select foldRight (zero: Expression)) {
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case ((cond, tval), fval) => Mux(cond, tval, fval, fval.tpe) }
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stmts += Connect(NoInfo, WRef(mem), output)
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case None =>
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}
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case None =>
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}
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}
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Some((mem.module(Block(stmts.toSeq)), lib.blackbox))
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}
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def run(c: Circuit): Circuit = {
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val modules = (mems, libs) match {
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case (Some(mems), Some(libs)) => (mems foldLeft c.modules){ (modules, mem) =>
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val (best, cost) = (libs foldLeft (None: Option[(Module, ExtModule)], BigInt(Long.MaxValue))){
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case ((best, area), lib) if mem.src.ports.size != lib.src.ports.size =>
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/* Palmer: FIXME: This just assumes the Chisel and vendor ports are in the same
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* order, but I'm starting with what actually gets generated. */
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System.err println s"INFO: unable to compile ${mem.src.name} using ${lib.src.name} port count must match"
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(best, area)
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case ((best, area), lib) =>
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/* Palmer: A quick cost function (that must be kept in sync with
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* memory_cost()) that attempts to avoid compiling unncessary
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* memories. This is a lower bound on the cost of compiling a
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* memory: it assumes 100% bit-cell utilization when mapping. */
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// val cost = 100 * (mem.depth * mem.width) / (lib.depth * lib.width) +
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// (mem.depth * mem.width)
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// Donggyu: I re-define cost
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val cost = (((mem.src.depth - 1) / lib.src.depth) + 1) *
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(((mem.src.width - 1) / lib.src.width) + 1) *
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(lib.src.depth * lib.src.width + 1) // weights on # cells
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System.err.println(s"Cost of ${lib.src.name} for ${mem.src.name}: ${cost}")
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if (cost > area) (best, area)
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else compile(mem, lib) match {
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case None => (best, area)
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case Some(p) => (Some(p), cost)
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}
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}
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best match {
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case None => modules
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case Some((mod, bb)) =>
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(modules filterNot (m => m.name == mod.name || m.name == bb.name)) ++ Seq(mod, bb)
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}
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}
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case _ => c.modules
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}
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c.copy(modules = modules)
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}
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}
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class MacroCompilerTransform extends Transform {
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def inputForm = HighForm
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def outputForm = HighForm
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def execute(state: CircuitState) = getMyAnnotations(state) match {
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case Seq(MacroCompilerAnnotation(state.circuit.main, memFile, libFile, synflops)) =>
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require(memFile.isDefined)
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// Read, eliminate None, get only SRAM, make firrtl macro
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val mems: Option[Seq[Macro]] = mdf.macrolib.Utils.readMDFFromPath(memFile) match {
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case Some(x:Seq[mdf.macrolib.Macro]) =>
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Some(Utils.filterForSRAM(Some(x)) getOrElse(List()) map {new Macro(_)})
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case _ => None
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}
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val libs: Option[Seq[Macro]] = mdf.macrolib.Utils.readMDFFromPath(libFile) match {
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case Some(x:Seq[mdf.macrolib.Macro]) =>
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Some(Utils.filterForSRAM(Some(x)) getOrElse(List()) map {new Macro(_)})
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case _ => None
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}
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val transforms = Seq(
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new MacroCompilerPass(mems, libs),
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new SynFlopsPass(synflops, libs getOrElse mems.get),
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firrtl.passes.SplitExpressions
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)
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((transforms foldLeft state)((s, xform) => xform runTransform s))
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}
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}
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class MacroCompiler extends Compiler {
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def emitter = new VerilogEmitter
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def transforms =
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Seq(new MacroCompilerTransform) ++
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getLoweringTransforms(firrtl.HighForm, firrtl.LowForm) // ++
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// Seq(new LowFirrtlOptimization) // Todo: This is dangerous
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}
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object MacroCompiler extends App {
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sealed trait MacroParam
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case object Macros extends MacroParam
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case object Library extends MacroParam
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case object Verilog extends MacroParam
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type MacroParamMap = Map[MacroParam, String]
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val usage = Seq(
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"Options:",
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" -m, --macro-list: The set of macros to compile",
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" -l, --library: The set of macros that have blackbox instances",
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" -v, --verilog: Verilog output",
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" --syn-flop: Produces synthesizable flop-based memories (for all memories and library memory macros); likely useful for simulation purposes") mkString "\n"
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def parseArgs(map: MacroParamMap, synflops: Boolean, args: List[String]): (MacroParamMap, Boolean) =
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args match {
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case Nil => (map, synflops)
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case ("-m" | "--macro-list") :: value :: tail =>
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parseArgs(map + (Macros -> value), synflops, tail)
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case ("-l" | "--library") :: value :: tail =>
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parseArgs(map + (Library -> value), synflops, tail)
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case ("-v" | "--verilog") :: value :: tail =>
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parseArgs(map + (Verilog -> value), synflops, tail)
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case "--syn-flops" :: tail =>
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parseArgs(map, true, tail)
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case arg :: tail =>
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println(s"Unknown field $arg\n")
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throw new Exception(usage)
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}
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def run(args: List[String]) {
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val (params, synflops) = parseArgs(Map[MacroParam, String](), false, args)
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try {
|
||||
val macros = Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
|
||||
|
||||
// Open the writer for the output Verilog file.
|
||||
val verilogWriter = new FileWriter(new File(params.get(Verilog).get))
|
||||
|
||||
if (macros.nonEmpty) {
|
||||
val circuit = Circuit(NoInfo, macros, macros.last.name)
|
||||
val annotations = AnnotationMap(Seq(MacroCompilerAnnotation(
|
||||
circuit.main, params.get(Macros).get, params.get(Library), synflops)))
|
||||
val state = CircuitState(circuit, HighForm, Some(annotations))
|
||||
|
||||
// Run the compiler.
|
||||
val result = new MacroCompiler().compileAndEmit(state)
|
||||
|
||||
// Extract Verilog circuit and write it.
|
||||
verilogWriter.write(result.getEmittedCircuit.value)
|
||||
}
|
||||
|
||||
// Close the writer.
|
||||
verilogWriter.close()
|
||||
|
||||
} catch {
|
||||
case e: java.util.NoSuchElementException =>
|
||||
throw new Exception(usage)
|
||||
case e: Throwable =>
|
||||
throw e
|
||||
}
|
||||
}
|
||||
|
||||
run(args.toList)
|
||||
}
|
||||
Reference in New Issue
Block a user