From c0d4e848bae02d3e6a7211094831c0bef16caaf0 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 27 May 2019 22:53:05 +0000 Subject: [PATCH 001/160] WIP --- .gitmodules | 6 + build.sbt | 84 ++++-- common.mk | 12 +- .../firechip/src/main/scala/Generator.scala | 124 +++++++++ .../firechip/src/main/scala/SimConfigs.scala | 54 ++++ .../src/main/scala/TargetConfigs.scala | 205 ++++++++++++++ .../src/main/scala/TargetLandTestSuites.scala | 45 ++++ .../src/main/scala/TargetMixins.scala | 131 +++++++++ .../firechip/src/main/scala/Targets.scala | 176 ++++++++++++ .../src/test/scala/ScalaTestSuite.scala | 138 ++++++++++ generators/icenet | 1 + sims/firesim | 1 + tests/big-blkdev.c | 79 ++++++ tests/nic-loopback.c | 98 +++++++ tests/nic.h | 8 +- tests/pingd.c | 254 ++++++++++++++++++ variables.mk | 12 + 17 files changed, 1399 insertions(+), 29 deletions(-) create mode 100755 generators/firechip/src/main/scala/Generator.scala create mode 100644 generators/firechip/src/main/scala/SimConfigs.scala create mode 100644 generators/firechip/src/main/scala/TargetConfigs.scala create mode 100644 generators/firechip/src/main/scala/TargetLandTestSuites.scala create mode 100644 generators/firechip/src/main/scala/TargetMixins.scala create mode 100755 generators/firechip/src/main/scala/Targets.scala create mode 100644 generators/firechip/src/test/scala/ScalaTestSuite.scala create mode 160000 generators/icenet create mode 160000 sims/firesim create mode 100644 tests/big-blkdev.c create mode 100644 tests/nic-loopback.c create mode 100644 tests/pingd.c diff --git a/.gitmodules b/.gitmodules index 698c53b9..a3fa357f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -31,3 +31,9 @@ [submodule "generators/hwacha"] path = generators/hwacha url = git@github.com:ucb-bar/hwacha.git +[submodule "sims/firesim"] + path = sims/firesim + url = https://github.com/firesim/firesim.git +[submodule "generators/icenet"] + path = generators/icenet + url = https://github.com/firesim/icenet.git diff --git a/build.sbt b/build.sbt index 6a06fcba..6e52c683 100644 --- a/build.sbt +++ b/build.sbt @@ -9,9 +9,9 @@ lazy val commonSettings = Seq( case _ => MergeStrategy.first}}, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.5" % "test", - libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.1", + libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, - libraryDependencies += "edu.berkeley.cs" %% "firrtl-interpreter" % "1.2-SNAPSHOT", + //libraryDependencies += "edu.berkeley.cs" %% "firrtl-interpreter" % "1.2-SNAPSHOT", libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), resolvers ++= Seq( @@ -19,18 +19,14 @@ lazy val commonSettings = Seq( Resolver.sonatypeRepo("releases"), Resolver.mavenLocal)) -lazy val rebarFirrtl = (project in file("tools/firrtl")) - .settings(commonSettings) +val rocketChipDir = file("generators/rocket-chip") -lazy val rocketchip = RootProject(file("generators/rocket-chip")) - -lazy val rebarrocketchip = project - .dependsOn(rocketchip) - .settings(commonSettings) - -lazy val testchipip = (project in file("generators/testchipip")) - .dependsOn(rebarrocketchip) - .settings(commonSettings) +lazy val firesimAsLibrary = sys.env.get("FIRESIM_IS_TOP") == None +lazy val firesimDir = if (firesimAsLibrary) { + file("sims/firesim/sim/") +} else { + file("../../sim/") +} // Checks for -DROCKET_USE_MAVEN. // If it's there, use a maven dependency. @@ -45,6 +41,42 @@ def conditionalDependsOn(prj: Project): Project = { } } +// Subproject definitions begin + +// Biancolin: get to the bottom of these +//lazy val rebarFirrtl = (project in file("tools/firrtl")) +// .settings(commonSettings) +// Overlaps with the dependency-injected version +// lazy val rocketchip = RootProject(rocketChipDir) + +// NB: FIRRTL dependency is unmanaged (and dropped in sim/lib) +lazy val chisel = (project in rocketChipDir / "chisel3") + + // Contains annotations & firrtl passes you may wish to use in rocket-chip without +// introducing a circular dependency between RC and MIDAS +lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") + + // Rocket-chip dependencies (subsumes making RC a RootProject) +lazy val hardfloat = (project in rocketChipDir / "hardfloat") + .settings(commonSettings).dependsOn(midasTargetUtils) + +lazy val rocketMacros = (project in rocketChipDir / "macros") + .settings(commonSettings) + +// HACK: I'm strugging to override settings in rocket-chip's build.sbt (i want +// the subproject to register a new library dependendency on midas's targetutils library) +// So instead, avoid the existing build.sbt altogether and specify the project's root at src/ +lazy val rebarRocketchip = (project in rocketChipDir / "src") + .settings( + commonSettings, + scalaSource in Compile := baseDirectory.value / "main" / "scala", + resourceDirectory in Compile := baseDirectory.value / "main" / "resources") + .dependsOn(chisel, hardfloat, rocketMacros) + +lazy val testchipip = (project in file("generators/testchipip")) + .dependsOn(rebarRocketchip) + .settings(commonSettings) + lazy val example = conditionalDependsOn(project in file("generators/example")) .dependsOn(boom, hwacha, sifive_blocks) .settings(commonSettings) @@ -52,26 +84,38 @@ lazy val example = conditionalDependsOn(project in file("generators/example")) lazy val utilities = conditionalDependsOn(project in file("generators/utilities")) .settings(commonSettings) -lazy val hwacha = (project in file ("generators/hwacha")) - .dependsOn(rebarrocketchip) +lazy val icenet = (project in file("generators/icenet")) + .dependsOn(rebarRocketchip, testchipip) + .settings(commonSettings) + +lazy val hwacha = (project in file("generators/hwacha")) + .dependsOn(rebarRocketchip) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) - .dependsOn(rebarrocketchip) + .dependsOn(rebarRocketchip) .settings(commonSettings) lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) - .dependsOn(rebarFirrtl) .settings(commonSettings) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) .settings(commonSettings) -lazy val `barstools-macros` = (project in file("./tools/barstools/macros/")) - .dependsOn(mdf, rebarrocketchip, rebarFirrtl) +lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) + .dependsOn(mdf, rebarRocketchip) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) - .dependsOn(rebarrocketchip) + .dependsOn(rebarRocketchip) .settings(commonSettings) + +// Library components of FireSim +lazy val midas = ProjectRef(firesimDir, "midas") +lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") + +lazy val firechip = (project in file("generators/firechip")) + .dependsOn(boom, icenet, testchipip, sifive_blocks, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .settings(commonSettings) + diff --git a/common.mk b/common.mk index f7e46608..37e2523e 100644 --- a/common.mk +++ b/common.mk @@ -8,23 +8,25 @@ SHELL=/bin/bash ######################################################################################### lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null) -PACKAGES=rocket-chip testchipip boom hwacha sifive-blocks example -SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) +PACKAGES=$(addprefix generators/, rocket-chip testchipip boom hwacha sifive-blocks example) \ + $(addprefix sims/firesim/sim/, . firesim-lib midas midas/targetutils) +SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) ######################################################################################### # rocket and testchipip classes ######################################################################################### -ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" +# NB: target/ lives under source ----V , due to how we're handling midas dependency injection +ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/src/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes" ######################################################################################### # jar creation variables and rules ######################################################################################### -FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar +FIRRTL_JAR := $(base_dir)/lib/firrtl.jar $(FIRRTL_JAR): $(call lookup_scala_srcs, $(REBAR_FIRRTL_DIR)/src/main/scala) $(MAKE) -C $(REBAR_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(REBAR_FIRRTL_DIR) build-scala - mkdir -p $(dir $@) + mkdir -p $(@D) cp -p $(REBAR_FIRRTL_DIR)/utils/bin/firrtl.jar $@ touch $@ diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala new file mode 100755 index 00000000..56ae824e --- /dev/null +++ b/generators/firechip/src/main/scala/Generator.scala @@ -0,0 +1,124 @@ +//See LICENSE for license details. + +package firesim.firesim + +import java.io.{File} + +import chisel3.experimental.RawModule +import chisel3.internal.firrtl.{Circuit, Port} + +import freechips.rocketchip.diplomacy.{ValName, AutoBundle} +import freechips.rocketchip.devices.debug.DebugIO +import freechips.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts} +import freechips.rocketchip.system.DefaultTestSuites._ +import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.subsystem.RocketTilesKey +import freechips.rocketchip.tile.XLen + +import boom.system.{BoomTilesKey, BoomTestSuites} + +import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities} + +trait HasTestSuites { + val rv64RegrTestNames = collection.mutable.LinkedHashSet( + "rv64ud-v-fcvt", + "rv64ud-p-fdiv", + "rv64ud-v-fadd", + "rv64uf-v-fadd", + "rv64um-v-mul", + // "rv64mi-p-breakpoint", // Not implemented in BOOM + // "rv64uc-v-rvc", // Not implemented in BOOM + "rv64ud-v-structural", + "rv64si-p-wfi", + "rv64um-v-divw", + "rv64ua-v-lrsc", + "rv64ui-v-fence_i", + "rv64ud-v-fcvt_w", + "rv64uf-v-fmin", + "rv64ui-v-sb", + "rv64ua-v-amomax_d", + "rv64ud-v-move", + "rv64ud-v-fclass", + "rv64ua-v-amoand_d", + "rv64ua-v-amoxor_d", + "rv64si-p-sbreak", + "rv64ud-v-fmadd", + "rv64uf-v-ldst", + "rv64um-v-mulh", + "rv64si-p-dirty") + + val rv32RegrTestNames = collection.mutable.LinkedHashSet( + "rv32mi-p-ma_addr", + "rv32mi-p-csr", + "rv32ui-p-sh", + "rv32ui-p-lh", + "rv32uc-p-rvc", + "rv32mi-p-sbreak", + "rv32ui-p-sll") + + def addTestSuites(targetName: String, params: Parameters) { + val coreParams = + if (params(RocketTilesKey).nonEmpty) { + params(RocketTilesKey).head.core + } else { + params(BoomTilesKey).head.core + } + val xlen = params(XLen) + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv32ud)) + } else { + TestGeneration.addSuite(rv32udBenchmarks) + TestGeneration.addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv64ud)) + } + } + if (coreParams.useAtomics) TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (params(BoomTilesKey).nonEmpty) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u) + else if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + TestGeneration.addSuite(FastBlockdevTests) + TestGeneration.addSuite(SlowBlockdevTests) + if (!targetName.contains("NoNIC")) + TestGeneration.addSuite(NICLoopbackTests) + } +} + +// Mixed into an App or into a TestSuite +trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSuites { + /** Output software test Makefrags, which provide targets for integration testing. */ + def generateTestSuiteMakefrags { + addTestSuites(names.topModuleClass, targetParams) + writeOutputFile(s"$longName.d", TestGeneration.generateMakefrag) // Subsystem-specific test suites + } + + // Output miscellaneous files produced as a side-effect of elaboration + def generateArtefacts { + ElaborationArtefacts.files.foreach { case (extension, contents) => + writeOutputFile(s"${longName}.${extension}", contents ()) + } + } +} + +object FireSimGenerator extends App with IsFireSimGeneratorLike { + lazy val generatorArgs = GeneratorArgs(args) + lazy val genDir = new File(names.targetDir) + elaborateAndCompileWithMidas + generateTestSuiteMakefrags + generateHostVerilogHeader + generateArtefacts + generateTclEnvFile +} diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala new file mode 100644 index 00000000..1118fe07 --- /dev/null +++ b/generators/firechip/src/main/scala/SimConfigs.scala @@ -0,0 +1,54 @@ +//See LICENSE for license details. +package firesim.firesim + +import freechips.rocketchip.config.{Parameters, Config, Field} + +import midas.{EndpointKey} +import midas.widgets.{EndpointMap} +import midas.models._ + +import firesim.endpoints._ +import firesim.configs._ + +/******************************************************************************* +* Full PLATFORM_CONFIG Configurations. These set simulator parameters. +* +* In general, if you're adding or removing features from any of these, you +* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager +* will store this name as part of the tags for the AGFI, so that later you can +* reconstruct what is in a particular AGFI. These tags are also used to +* determine which driver to build. +*******************************************************************************/ +class FireSimConfig extends Config( + new WithSerialWidget ++ + new WithUARTWidget ++ + new WithSimpleNICWidget ++ + new WithBlockDevWidget ++ + new WithDefaultMemModel ++ + new WithTracerVWidget ++ + new BasePlatformConfig) + +class FireSimClockDivConfig extends Config( + new WithDefaultMemModel(clockDivision = 2) ++ + new FireSimConfig) + +class FireSimDDR3Config extends Config( + new FCFS16GBQuadRank ++ + new FireSimConfig) + +class FireSimDDR3LLC4MBConfig extends Config( + new FCFS16GBQuadRankLLC4MB ++ + new FireSimConfig) + +class FireSimDDR3FRFCFSConfig extends Config( + new FRFCFS16GBQuadRank ++ + new FireSimConfig) + +class FireSimDDR3FRFCFSLLC4MBConfig extends Config( + new FRFCFS16GBQuadRankLLC4MB ++ + new FireSimConfig) + +class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config( + new FRFCFS16GBQuadRankLLC4MB3Div ++ + new FireSimConfig) + diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala new file mode 100644 index 00000000..5c1cade1 --- /dev/null +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -0,0 +1,205 @@ +package firesim.firesim + +import java.io.File + +import chisel3.util.{log2Up} +import freechips.rocketchip.config.{Parameters, Config} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.devices.tilelink.BootROMParams +import freechips.rocketchip.devices.debug.DebugModuleParams +import boom.system.BoomTilesKey +import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig} +import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} +import icenet._ + +class WithBootROM extends Config((site, here, up) => { + case BootROMParams => { + val rebarBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") + val firesimBootROM = new File(s"./target-rtl/testchipip/bootrom/bootrom.rv${site(XLen)}.img") + + val bootROMPath = if (rebarBootROM.exists()) { + rebarBootROM.getAbsolutePath() + } else { + firesimBootROM.getAbsolutePath() + } + BootROMParams(contentFileName = bootROMPath) + } +}) + +class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => { + case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq) +}) + +class WithUARTKey extends Config((site, here, up) => { + case PeripheryUARTKey => List(UARTParams( + address = BigInt(0x54000000L), + nTxEntries = 256, + nRxEntries = 256)) +}) + +class WithNICKey extends Config((site, here, up) => { + case NICKey => NICConfig( + inBufFlits = 8192, + ctrlQueueDepth = 64) +}) + +class WithRocketL2TLBs(entries: Int) extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( + core = tile.core.copy( + nL2TLBEntries = entries + ) + )) +}) + +class WithPerfCounters extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( + core = tile.core.copy(nPerfCounters = 29) + )) +}) + +class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( + core = tile.core.copy(nL2TLBEntries = entries) + )) +}) + +// Disables clock-gating; doesn't play nice with our FAME-1 pass +class WithoutClockGating extends Config((site, here, up) => { + case DebugModuleParams => up(DebugModuleParams, site).copy(clockGate = false) +}) + +// Testing configurations +// This enables printfs used in testing +class WithScalaTestFeatures extends Config((site, here, up) => { + case PrintTracePort => true +}) + +/******************************************************************************* +* Full TARGET_CONFIG configurations. These set parameters of the target being +* simulated. +* +* In general, if you're adding or removing features from any of these, you +* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager +* will store this name as part of the tags for the AGFI, so that later you can +* reconstruct what is in a particular AGFI. These tags are also used to +* determine which driver to build. +*******************************************************************************/ +class FireSimRocketChipConfig extends Config( + new WithBootROM ++ + new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ + new WithExtMemSize(0x400000000L) ++ // 16GB + new WithoutTLMonitors ++ + new WithUARTKey ++ + new WithNICKey ++ + new WithBlockDevice ++ + new WithRocketL2TLBs(1024) ++ + new WithPerfCounters ++ + new WithoutClockGating ++ + new freechips.rocketchip.system.DefaultConfig) + +class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { + case RocketTilesKey => List.tabulate(n)(i => up(RocketTilesKey).head.copy(hartId = i)) +}) + +// single core config +class FireSimRocketChipSingleCoreConfig extends Config(new FireSimRocketChipConfig) + +// dual core config +class FireSimRocketChipDualCoreConfig extends Config( + new WithNDuplicatedRocketCores(2) ++ + new FireSimRocketChipSingleCoreConfig) + +// quad core config +class FireSimRocketChipQuadCoreConfig extends Config( + new WithNDuplicatedRocketCores(4) ++ + new FireSimRocketChipSingleCoreConfig) + +// hexa core config +class FireSimRocketChipHexaCoreConfig extends Config( + new WithNDuplicatedRocketCores(6) ++ + new FireSimRocketChipSingleCoreConfig) + +// octa core config +class FireSimRocketChipOctaCoreConfig extends Config( + new WithNDuplicatedRocketCores(8) ++ + new FireSimRocketChipSingleCoreConfig) + +class FireSimBoomConfig extends Config( + new WithBootROM ++ + new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ + new WithExtMemSize(0x400000000L) ++ // 16GB + new WithoutTLMonitors ++ + new WithUARTKey ++ + new WithNICKey ++ + new WithBlockDevice ++ + new WithBoomL2TLBs(1024) ++ + new WithoutClockGating ++ + // Using a small config because it has 64-bit system bus, and compiles quickly + new boom.system.SmallBoomConfig) + +// A safer implementation than the one in BOOM in that it +// duplicates whatever BOOMTileKey.head is present N times. This prevents +// accidentally (and silently) blowing away configurations that may change the +// tile in the "up" view +class WithNDuplicatedBoomCores(n: Int) extends Config((site, here, up) => { + case BoomTilesKey => List.tabulate(n)(i => up(BoomTilesKey).head.copy(hartId = i)) + case MaxHartIdBits => log2Up(site(BoomTilesKey).size) +}) + +class FireSimBoomDualCoreConfig extends Config( + new WithNDuplicatedBoomCores(2) ++ + new FireSimBoomConfig) + +class FireSimBoomQuadCoreConfig extends Config( + new WithNDuplicatedBoomCores(4) ++ + new FireSimBoomConfig) + +//********************************************************************************** +//* Supernode Configurations +//*********************************************************************************/ +class WithNumNodes(n: Int) extends Config((pname, site, here) => { + case NumNodes => n +}) + +class SupernodeFireSimRocketChipConfig extends Config( + new WithNumNodes(4) ++ + new WithExtMemSize(0x200000000L) ++ // 8GB + new FireSimRocketChipConfig) + +class SupernodeFireSimRocketChipSingleCoreConfig extends Config( + new WithNumNodes(4) ++ + new WithExtMemSize(0x200000000L) ++ // 8GB + new FireSimRocketChipSingleCoreConfig) + +class SupernodeSixNodeFireSimRocketChipSingleCoreConfig extends Config( + new WithNumNodes(6) ++ + new WithExtMemSize(0x40000000L) ++ // 1GB + new FireSimRocketChipSingleCoreConfig) + +class SupernodeEightNodeFireSimRocketChipSingleCoreConfig extends Config( + new WithNumNodes(8) ++ + new WithExtMemSize(0x40000000L) ++ // 1GB + new FireSimRocketChipSingleCoreConfig) + +class SupernodeFireSimRocketChipDualCoreConfig extends Config( + new WithNumNodes(4) ++ + new WithExtMemSize(0x200000000L) ++ // 8GB + new FireSimRocketChipDualCoreConfig) + +class SupernodeFireSimRocketChipQuadCoreConfig extends Config( + new WithNumNodes(4) ++ + new WithExtMemSize(0x200000000L) ++ // 8GB + new FireSimRocketChipQuadCoreConfig) + +class SupernodeFireSimRocketChipHexaCoreConfig extends Config( + new WithNumNodes(4) ++ + new WithExtMemSize(0x200000000L) ++ // 8GB + new FireSimRocketChipHexaCoreConfig) + +class SupernodeFireSimRocketChipOctaCoreConfig extends Config( + new WithNumNodes(4) ++ + new WithExtMemSize(0x200000000L) ++ // 8GB + new FireSimRocketChipOctaCoreConfig) + diff --git a/generators/firechip/src/main/scala/TargetLandTestSuites.scala b/generators/firechip/src/main/scala/TargetLandTestSuites.scala new file mode 100644 index 00000000..b20fa8dd --- /dev/null +++ b/generators/firechip/src/main/scala/TargetLandTestSuites.scala @@ -0,0 +1,45 @@ +//See LICENSE for license details. +package firesim.firesim + +import scala.collection.mutable.LinkedHashSet + +import freechips.rocketchip.system.{TestGeneration, RocketTestSuite} + +/* This imports tests from FireChip to test devices that aren't natively + * tested by the riscv assembly tests. + * Firesim's target-specific makefrag gives the recipes for building the + * binaries. + */ + +class BlockdevTestSuite(prefix: String, val names: LinkedHashSet[String]) extends RocketTestSuite { + val envName = "" + // fc_test_dir is is defined in firesim's Makefrag + val dir = "$(fc_test_dir)" + val makeTargetName = prefix + "-blkdev-tests" + def kind = "blockdev" + // Blockdev tests need an image, which complicates this + def additionalArgs = "+blkdev-in-mem0=128 +nic-loopback0" + override def toString = s"$makeTargetName = \\\n" + + // Make variable with the binaries of the suite + names.map(n => s"\t$n.riscv").mkString(" \\\n") + "\n\n" + + // Variables with binary specific arguments + names.map(n => s"$n.riscv_ARGS=$additionalArgs").mkString(" \n") + + postScript +} + +object FastBlockdevTests extends BlockdevTestSuite("fast", LinkedHashSet("blkdev")) +object SlowBlockdevTests extends BlockdevTestSuite("slow", LinkedHashSet("big-blkdev")) + +class NICTestSuite(prefix: String, val names: LinkedHashSet[String]) extends RocketTestSuite { + val envName = "" + val dir = "$(fc_test_dir)" + val makeTargetName = prefix + "-nic-tests" + def kind = "nic" + def additionalArgs = "+netbw0=100 +linklatency0=6405 +netburst0=8 +slotid=0 +nic-loopback0" + override def toString = s"$makeTargetName = \\\n" + + names.map(n => s"\t$n.riscv").mkString(" \\\n") + "\n\n" + + names.map(n => s"$n.riscv_ARGS=$additionalArgs").mkString(" \n") + + postScript +} + +object NICLoopbackTests extends NICTestSuite("loopback", LinkedHashSet("nic-loopback")) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala new file mode 100644 index 00000000..1c38ce2e --- /dev/null +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -0,0 +1,131 @@ +package firesim.firesim + +import chisel3._ +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.util._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.rocket.TracedInstruction +import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} +import boom.system.BoomSubsystem + +import midas.models.AXI4BundleWithEdge +import midas.targetutils.ExcludeInstanceAsserts + +/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */ +trait HasDefaultBusConfiguration { + this: BaseSubsystem => + // The sbus masters the cbus; here we convert TL-UH -> TL-UL + sbus.crossToBus(cbus, NoCrossing) + + // The cbus masters the pbus; which might be clocked slower + cbus.crossToBus(pbus, SynchronousCrossing()) + + // The fbus masters the sbus; both are TL-UH or TL-C + FlipRendering { implicit p => + sbus.crossFromBus(fbus, SynchronousCrossing()) + } + + // The sbus masters the mbus; here we convert TL-C -> TL-UH + private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) + private val (in, out, halt) = coherenceManager(this) + if (nBanks != 0) { + sbus.coupleTo("coherence_manager") { in :*= _ } + mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } + } +} + + +/** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges + * associated with each port. This drives FASED functional model sizing + */ +trait CanHaveFASEDOptimizedMasterAXI4MemPort { this: BaseSubsystem => + val module: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + + val memAXI4Node = p(ExtMem).map { case MemoryPortParams(memPortParams, nMemoryChannels) => + val portName = "axi4" + val device = new MemoryDevice + + val memAXI4Node = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel => + val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) + val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) + + AXI4SlavePortParameters( + slaves = Seq(AXI4SlaveParameters( + address = base.flatMap(_.intersect(filter)), + resources = device.reg, + regionType = RegionType.UNCACHED, // cacheable + executable = true, + supportsWrite = TransferSizes(1, mbus.blockBytes), + supportsRead = TransferSizes(1, mbus.blockBytes), + interleavedId = Some(0))), // slave does not interleave read responses + beatBytes = memPortParams.beatBytes) + }) + + memAXI4Node := mbus.toDRAMController(Some(portName)) { + AXI4UserYanker() := AXI4IdIndexer(memPortParams.idBits) := TLToAXI4() + } + + memAXI4Node + } +} + +/** Actually generates the corresponding IO in the concrete Module */ +trait CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp extends LazyModuleImp { + val outer: CanHaveFASEDOptimizedMasterAXI4MemPort + + val mem_axi4 = outer.memAXI4Node.map(x => IO(HeterogeneousBag(AXI4BundleWithEdge.fromNode(x.in)))) + (mem_axi4 zip outer.memAXI4Node) foreach { case (io, node) => + (io zip node.in).foreach { case (io, (bundle, _)) => io <> bundle } + } + + def connectSimAXIMem() { + (mem_axi4 zip outer.memAXI4Node).foreach { case (io, node) => + (io zip node.in).foreach { case (io, (_, edge)) => + val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)) + Module(mem.module).io.axi4.head <> io + } + } + } +} + +/* Wires out tile trace ports to the top; and wraps them in a Bundle that the + * TracerV endpoint can match on. + */ +object PrintTracePort extends Field[Boolean](false) + +trait HasTraceIO { + this: HasTiles => + val module: HasTraceIOImp + + // Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp + val traceNexus = BundleBridgeNexus[Vec[TracedInstruction]] + val tileTraceNodes = tiles.map(tile => tile.traceNode) + tileTraceNodes foreach { traceNexus := _ } +} + +trait HasTraceIOImp extends LazyModuleImp { + val outer: HasTraceIO + + val traceIO = IO(Output(new TraceOutputTop( + DeclockedTracedInstruction.fromNode(outer.traceNexus.in)))) + (traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) => + port := DeclockedTracedInstruction.fromVec(tileTrace) + }) + + // Enabled to test TracerV trace capture + if (p(PrintTracePort)) { + val traceprint = Wire(UInt(512.W)) + traceprint := traceIO.asUInt + printf("TRACEPORT: %x\n", traceprint) + } +} + +// Prevent MIDAS from synthesizing assertions in the dummy TLB included in BOOM +trait ExcludeInvalidBoomAssertions extends LazyModuleImp { + ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb")) +} + diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala new file mode 100755 index 00000000..3a565c65 --- /dev/null +++ b/generators/firechip/src/main/scala/Targets.scala @@ -0,0 +1,176 @@ +package firesim.firesim + +import chisel3._ +import freechips.rocketchip._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.util.{HeterogeneousBag} +import freechips.rocketchip.amba.axi4.AXI4Bundle +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.diplomacy.LazyModule +import boom.system.{BoomSubsystem, BoomSubsystemModuleImp} +import icenet._ +import testchipip._ +import testchipip.SerialAdapter.SERIAL_IF_WIDTH +import sifive.blocks.devices.uart._ +import midas.models.AXI4BundleWithEdge +import java.io.File + +/******************************************************************************* +* Top level DESIGN configurations. These describe the basic instantiations of +* the designs being simulated. +* +* In general, if you're adding or removing features from any of these, you +* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager +* will store this name as part of the tags for the AGFI, so that later you can +* reconstruct what is in a particular AGFI. These tags are also used to +* determine which driver to build. +*******************************************************************************/ + +class FireSim(implicit p: Parameters) extends RocketSubsystem + with HasDefaultBusConfiguration + with CanHaveFASEDOptimizedMasterAXI4MemPort + with HasPeripheryBootROM + with HasNoDebug + with HasPeripherySerial + with HasPeripheryUART + with HasPeripheryIceNIC + with HasPeripheryBlockDevice + with HasTraceIO +{ + override lazy val module = new FireSimModuleImp(this) +} + +class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) + with HasRTCModuleImp + with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with HasPeripheryBootROMModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with HasPeripheryUARTModuleImp + with HasPeripheryIceNICModuleImpValidOnly + with HasPeripheryBlockDeviceModuleImp + with HasTraceIOImp + + +class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem + with HasDefaultBusConfiguration + with CanHaveFASEDOptimizedMasterAXI4MemPort + with HasPeripheryBootROM + with HasNoDebug + with HasPeripherySerial + with HasPeripheryUART + with HasPeripheryBlockDevice + with HasTraceIO +{ + override lazy val module = new FireSimNoNICModuleImp(this) +} + +class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemModuleImp(l) + with HasRTCModuleImp + with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with HasPeripheryBootROMModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with HasPeripheryUARTModuleImp + with HasPeripheryBlockDeviceModuleImp + with HasTraceIOImp + + +class FireBoom(implicit p: Parameters) extends BoomSubsystem + with HasDefaultBusConfiguration + with CanHaveFASEDOptimizedMasterAXI4MemPort + with HasPeripheryBootROM + with HasNoDebug + with HasPeripherySerial + with HasPeripheryUART + with HasPeripheryIceNIC + with HasPeripheryBlockDevice + with HasTraceIO +{ + override lazy val module = new FireBoomModuleImp(this) +} + +class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomSubsystemModuleImp(l) + with HasRTCModuleImp + with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with HasPeripheryBootROMModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with HasPeripheryUARTModuleImp + with HasPeripheryIceNICModuleImpValidOnly + with HasPeripheryBlockDeviceModuleImp + with HasTraceIOImp + with ExcludeInvalidBoomAssertions + +class FireBoomNoNIC(implicit p: Parameters) extends BoomSubsystem + with HasDefaultBusConfiguration + with CanHaveFASEDOptimizedMasterAXI4MemPort + with HasPeripheryBootROM + with HasNoDebug + with HasPeripherySerial + with HasPeripheryUART + with HasPeripheryBlockDevice + with HasTraceIO +{ + override lazy val module = new FireBoomNoNICModuleImp(this) +} + +class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomSubsystemModuleImp(l) + with HasRTCModuleImp + with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with HasPeripheryBootROMModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with HasPeripheryUARTModuleImp + with HasPeripheryBlockDeviceModuleImp + with HasTraceIOImp + with ExcludeInvalidBoomAssertions + +case object NumNodes extends Field[Int] + +class SupernodeIO( + nNodes: Int, + serialWidth: Int, + bagPrototype: HeterogeneousBag[AXI4BundleWithEdge])(implicit p: Parameters) + extends Bundle { + + val serial = Vec(nNodes, new SerialIO(serialWidth)) + val mem_axi = Vec(nNodes, bagPrototype.cloneType) + val bdev = Vec(nNodes, new BlockDeviceIO) + val net = Vec(nNodes, new NICIOvonly) + val uart = Vec(nNodes, new UARTPortIO) + + override def cloneType = new SupernodeIO(nNodes, serialWidth, bagPrototype).asInstanceOf[this.type] +} + + +class FireSimSupernode(implicit p: Parameters) extends Module { + val nNodes = p(NumNodes) + val nodes = Seq.fill(nNodes) { + Module(LazyModule(new FireSim).module) + } + + val io = IO(new SupernodeIO(nNodes, SERIAL_IF_WIDTH, nodes(0).mem_axi4.get)) + + io.mem_axi.zip(nodes.map(_.mem_axi4)).foreach { + case (out, mem_axi4) => out <> mem_axi4.get + } + io.serial <> nodes.map(_.serial) + io.bdev <> nodes.map(_.bdev) + io.net <> nodes.map(_.net) + io.uart <> nodes.map(_.uart(0)) + nodes.foreach{ case n => { + n.debug.clockeddmi.get.dmi.req.valid := false.B + n.debug.clockeddmi.get.dmi.resp.ready := false.B + n.debug.clockeddmi.get.dmiClock := clock + n.debug.clockeddmi.get.dmiReset := reset.toBool + n.debug.clockeddmi.get.dmi.req.bits.data := DontCare + n.debug.clockeddmi.get.dmi.req.bits.addr := DontCare + n.debug.clockeddmi.get.dmi.req.bits.op := DontCare + } } +} + diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala new file mode 100644 index 00000000..588c7c2a --- /dev/null +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -0,0 +1,138 @@ +//See LICENSE for license details. +package firesim.firesim + +import java.io.File + +import scala.concurrent.{Future, Await, ExecutionContext} +import scala.sys.process.{stringSeqToProcess, ProcessLogger} +import scala.io.Source + +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite} +import freechips.rocketchip.system.TestGeneration._ +import freechips.rocketchip.system.DefaultTestSuites._ + +import firesim.util.GeneratorArgs + +abstract class FireSimTestSuite( + topModuleClass: String, + targetConfigs: String, + platformConfigs: String, + N: Int = 8 + ) extends firesim.midasexamples.TestSuiteCommon with HasFireSimGeneratorUtilities { + import scala.concurrent.duration._ + import ExecutionContext.Implicits.global + + lazy val generatorArgs = GeneratorArgs( + midasFlowKind = "midas", + targetDir = "generated-src", + topModuleProject = "firesim.firesim", + topModuleClass = topModuleClass, + targetConfigProject = "firesim.firesim", + targetConfigs = targetConfigs ++ "_WithScalaTestFeatures", + platformConfigProject = "firesim.firesim", + platformConfigs = platformConfigs) + + // From HasFireSimGeneratorUtilities + // For the firesim utilities to use the same directory as the test suite + override lazy val testDir = genDir + + // From TestSuiteCommon + val targetTuple = generatorArgs.tupleName + val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", + s"TARGET_CONFIG=${generatorArgs.targetConfigs}", + s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") + override lazy val platform = hostParams(midas.Platform) + + def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { + make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"), + s"EMUL=${backend}") + ++ additionalArgs):_*) + } + + def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { + behavior of s"${name} running on ${backend} in MIDAS-level simulation" + compileMlSimulator(backend, debug) + if (isCmdAvailable(backend)) { + it should s"pass" in { + assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0) + } + } + } + + //def runReplay(backend: String, replayBackend: String, name: String) = { + // val dir = (new File(outDir, backend)).getAbsolutePath + // (Seq("make", s"replay-$replayBackend", + // s"SAMPLE=${dir}/${name}.sample", s"output_dir=$dir") ++ makeArgs).! + //} + + def runSuite(backend: String, debug: Boolean = false)(suite: RocketTestSuite) { + // compile emulators + behavior of s"${suite.makeTargetName} running on $backend" + if (isCmdAvailable(backend)) { + val postfix = suite match { + case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv" + case _ => "" + } + val results = suite.names.toSeq sliding (N, N) map { t => + val subresults = t map (name => + Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug))) + Await result (Future sequence subresults, Duration.Inf) + } + results.flatten foreach { case (name, exitcode) => + it should s"pass $name" in { assert(exitcode == 0) } + } + //replayBackends foreach { replayBackend => + // if (platformParams(midas.EnableSnapshot) && isCmdAvailable("vcs")) { + // assert((Seq("make", s"vcs-$replayBackend") ++ makeArgs).! == 0) // compile vcs + // suite.names foreach { name => + // it should s"replay $name in $replayBackend" in { + // assert(runReplay(backend, replayBackend, s"$name$postfix") == 0) + // } + // } + // } else { + // suite.names foreach { name => + // ignore should s"replay $name in $backend" + // } + // } + //} + } else { + ignore should s"pass $backend" + } + } + + // Checks the collected trace log matches the behavior of a chisel printf + def diffTracelog(verilatedLog: String) { + behavior of "captured instruction trace" + it should s"match the chisel printf in ${verilatedLog}" in { + def getLines(file: File, dropLines: Int = 0): Seq[String] = { + val lines = Source.fromFile(file).getLines.toList + lines.filter(_.startsWith("TRACEPORT")).drop(dropLines) + } + val resetLength = 50 + val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")) + val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength + 1) + assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length") + assert(verilatedOutput.nonEmpty) + for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) { + assert(vPrint == sPrint) + } + } + } + + clean + mkdirs + elaborateAndCompileWithMidas + generateTestSuiteMakefrags + runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0""")) + diffTracelog("rv64ui-p-simple.out") + runSuite("verilator")(benchmarks) + runSuite("verilator")(FastBlockdevTests) +} + +class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig") +class RocketF1ClockDivTests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimClockDivConfig") +class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig") +class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") { + runSuite("verilator")(NICLoopbackTests) +} diff --git a/generators/icenet b/generators/icenet new file mode 160000 index 00000000..bba264d6 --- /dev/null +++ b/generators/icenet @@ -0,0 +1 @@ +Subproject commit bba264d68d366180f6f9b55061ee9408425d8229 diff --git a/sims/firesim b/sims/firesim new file mode 160000 index 00000000..ccfd85aa --- /dev/null +++ b/sims/firesim @@ -0,0 +1 @@ +Subproject commit ccfd85aa287bd158b87ab9160cb599ec7534553b diff --git a/tests/big-blkdev.c b/tests/big-blkdev.c new file mode 100644 index 00000000..d065217a --- /dev/null +++ b/tests/big-blkdev.c @@ -0,0 +1,79 @@ +#include +#include + +#include "mmio.h" +#include "blkdev.h" + +#define SECTOR_WORDS (BLKDEV_SECTOR_SIZE / sizeof(uint64_t)) +#define TEST_SECTORS 128 + +unsigned long sector_buf[SECTOR_WORDS]; + +void write_sector(unsigned int secnum) +{ + int req_tag, resp_tag; + + for (int i = 0; i < SECTOR_WORDS; i++) + sector_buf[i] = (secnum << 6) | i; + + while (reg_read8(BLKDEV_NREQUEST) == 0); + req_tag = blkdev_send_request((unsigned long) sector_buf, secnum, 1, 1); + while (reg_read8(BLKDEV_NCOMPLETE) == 0); + resp_tag = reg_read8(BLKDEV_COMPLETE); + + if (req_tag != resp_tag) { + printf("Response tag %d does not match request tag %d\n", + req_tag, resp_tag); + exit(EXIT_FAILURE); + } +} + +void check_sector(unsigned int secnum) +{ + int req_tag, resp_tag; + + while (reg_read8(BLKDEV_NREQUEST) == 0); + req_tag = blkdev_send_request((unsigned long) sector_buf, secnum, 1, 0); + while (reg_read8(BLKDEV_NCOMPLETE) == 0); + resp_tag = reg_read8(BLKDEV_COMPLETE); + + if (req_tag != resp_tag) { + printf("Response tag %d does not match request tag %d\n", + req_tag, resp_tag); + exit(EXIT_FAILURE); + } + + for (int i = 0; i < SECTOR_WORDS; i++) { + unsigned long expected = (secnum << 6) | i; + unsigned long actual = sector_buf[i]; + if (actual != expected) { + printf("Word %d in sector %x does not match expected\n", + i, secnum); + printf("Expected %lx, got %lx\n", + expected, actual); + exit(EXIT_FAILURE); + } + } +} + +int main(void) +{ + unsigned int nsectors = blkdev_nsectors(); + unsigned int stride = nsectors / TEST_SECTORS; + + printf("Writing %u of %u sectors\n", TEST_SECTORS, nsectors); + + for (int i = 0; i < TEST_SECTORS; i++) { + int sector = i * stride; + write_sector(sector); + } + + printf("Checking sectors\n", nsectors); + + for (int i = 0; i < TEST_SECTORS; i++) { + int sector = i * stride; + check_sector(sector); + } + + return 0; +} diff --git a/tests/nic-loopback.c b/tests/nic-loopback.c new file mode 100644 index 00000000..1d3c7b96 --- /dev/null +++ b/tests/nic-loopback.c @@ -0,0 +1,98 @@ +#include "mmio.h" +#include +#include +#include + +#include "nic.h" +#include "encoding.h" + +#define NPACKETS 10 +#define TEST_OFFSET 3 +#define TEST_LEN 356 +#define ARRAY_LEN 360 +#define NTRIALS 3 + +uint32_t src[NPACKETS][ARRAY_LEN]; +uint32_t dst[NPACKETS][ARRAY_LEN]; +uint64_t lengths[NPACKETS]; + +static inline void send_recv() +{ + uint64_t send_packet, recv_addr; + int ncomps, send_comps_left = NPACKETS, recv_comps_left = NPACKETS; + int recv_idx = 0; + + for (int i = 0; i < NPACKETS; i++) { + uint64_t pkt_size = TEST_LEN * sizeof(uint32_t); + uint64_t src_addr = (uint64_t) &src[i][TEST_OFFSET]; + send_packet = (pkt_size << 48) | src_addr; + recv_addr = (uint64_t) dst[i]; + reg_write64(SIMPLENIC_SEND_REQ, send_packet); + reg_write64(SIMPLENIC_RECV_REQ, recv_addr); + } + + while (send_comps_left > 0 || recv_comps_left > 0) { + ncomps = nic_send_comp_avail(); + asm volatile ("fence"); + for (int i = 0; i < ncomps; i++) + reg_read16(SIMPLENIC_SEND_COMP); + send_comps_left -= ncomps; + + ncomps = nic_recv_comp_avail(); + asm volatile ("fence"); + for (int i = 0; i < ncomps; i++) { + lengths[recv_idx] = reg_read16(SIMPLENIC_RECV_COMP); + recv_idx++; + } + recv_comps_left -= ncomps; + } +} + +void run_test(void) +{ + unsigned long start, end; + int i, j; + + memset(dst, 0, sizeof(dst)); + asm volatile ("fence"); + + start = rdcycle(); + send_recv(); + end = rdcycle(); + + printf("send/recv %lu cycles\n", end - start); + + for (i = 0; i < NPACKETS; i++) { + if (lengths[i] != TEST_LEN * sizeof(uint32_t)) { + printf("recv got wrong # bytes\n"); + exit(EXIT_FAILURE); + } + + for (j = 0; j < TEST_LEN; j++) { + if (dst[i][j] != src[i][j + TEST_OFFSET]) { + printf("Data mismatch @ %d, %d: %x != %x\n", + i, j, dst[i][j], src[i][j + TEST_OFFSET]); + exit(EXIT_FAILURE); + } + } + } +} + +int main(void) +{ + int i, j; + + for (i = 0; i < NPACKETS; i++) { + for (j = 0; j < ARRAY_LEN; j++) + src[i][j] = i * ARRAY_LEN + j; + } + + for (i = 0; i < NTRIALS; i++) { + printf("Trial %d\n", i); + run_test(); + } + + printf("All correct\n"); + + return 0; +} diff --git a/tests/nic.h b/tests/nic.h index 55a86a2d..bee4c395 100644 --- a/tests/nic.h +++ b/tests/nic.h @@ -8,22 +8,22 @@ static inline int nic_send_req_avail(void) { - return reg_read16(SIMPLENIC_COUNTS) & 0xf; + return reg_read32(SIMPLENIC_COUNTS) & 0xff; } static inline int nic_recv_req_avail(void) { - return (reg_read16(SIMPLENIC_COUNTS) >> 4) & 0xf; + return (reg_read32(SIMPLENIC_COUNTS) >> 8) & 0xff; } static inline int nic_send_comp_avail(void) { - return (reg_read16(SIMPLENIC_COUNTS) >> 8) & 0xf; + return (reg_read32(SIMPLENIC_COUNTS) >> 16) & 0xff; } static inline int nic_recv_comp_avail(void) { - return (reg_read16(SIMPLENIC_COUNTS) >> 12) & 0xf; + return (reg_read32(SIMPLENIC_COUNTS) >> 24) & 0xff; } static void nic_send(void *data, unsigned long len) diff --git a/tests/pingd.c b/tests/pingd.c new file mode 100644 index 00000000..9e02cafe --- /dev/null +++ b/tests/pingd.c @@ -0,0 +1,254 @@ +#include "mmio.h" +#include "nic.h" + +#include +#include +#include +#include + +#define ETH_MAX_WORDS 190 +#define NET_IP_ALIGN 2 +#define ETH_HEADER_SIZE 14 +#define MAC_ADDR_SIZE 6 +#define IP_ADDR_SIZE 4 + +#define IPV4_ETHTYPE 0x0800 +#define ARP_ETHTYPE 0x0806 +#define ICMP_PROT 1 +#define ECHO_REPLY 0 +#define ECHO_REQUEST 8 +#define ARP_REQUEST 1 +#define ARP_REPLY 2 +#define HTYPE_ETH 1 + +static inline uint16_t ntohs(uint16_t nint) +{ + return ((nint & 0xff) << 8) | ((nint >> 8) & 0xff); +} + +static inline uint16_t htons(uint16_t nint) +{ + return ntohs(nint); +} + +struct eth_header { + uint8_t padding[NET_IP_ALIGN]; + uint8_t dst_mac[MAC_ADDR_SIZE]; + uint8_t src_mac[MAC_ADDR_SIZE]; + uint16_t ethtype; +}; + +struct arp_header { + uint16_t htype; + uint16_t ptype; + uint8_t hlen; + uint8_t plen; + uint16_t oper; + uint8_t sha[MAC_ADDR_SIZE]; + uint8_t spa[IP_ADDR_SIZE]; + uint8_t tha[MAC_ADDR_SIZE]; + uint8_t tpa[IP_ADDR_SIZE]; +}; + +struct ipv4_header { + uint8_t ver_ihl; + uint8_t dscp_ecn; + uint16_t length; + uint16_t ident; + uint16_t flags_frag_off; + uint8_t ttl; + uint8_t prot; + uint16_t cksum; + uint32_t src_addr; + uint32_t dst_addr; +}; + +struct icmp_header { + uint8_t type; + uint8_t code; + uint16_t cksum; + uint32_t rest; +}; + +static int checksum(uint16_t *data, int len) +{ + int i; + uint32_t sum = 0; + + for (i = 0; i < len; i++) + sum += ntohs(data[i]); + + while ((sum >> 16) != 0) + sum = (sum & 0xffff) + (sum >> 16); + + sum = ~sum & 0xffff; + + return sum; +} + +#define ceil_div(n, d) (((n) - 1) / (d) + 1) + +static int process_arp(void *buf, uint8_t *mac) +{ + struct eth_header *eth = buf; + struct arp_header *arp; + size_t size = ETH_HEADER_SIZE + sizeof(*arp); + uint8_t tmp_addr[IP_ADDR_SIZE]; + + // Verify arp packet + arp = buf + sizeof(*eth); + if (ntohs(arp->oper) != ARP_REQUEST) { + printf("Wrong arp operation: %d\n", ntohs(arp->oper)); + return -1; + } + + if (ntohs(arp->htype) != HTYPE_ETH) { + printf("Wrong ARP HTYPE\n"); + return -1; + } + + if (ntohs(arp->ptype) != IPV4_ETHTYPE) { + printf("Wrong ARP PTYPE\n"); + return -1; + } + + if (arp->hlen != 6) { + printf("Wrong ARP HLEN: %d\n", arp->hlen); + return -1; + } + + if (arp->plen != 4) { + printf("Wrong ARP PLEN: %d\n", arp->plen); + return -1; + } + + // Make the source the destination, and add our mac address + memcpy(eth->dst_mac, eth->src_mac, MAC_ADDR_SIZE); + memcpy(eth->src_mac, mac, MAC_ADDR_SIZE); + + // create ARP reply + arp->oper = htons(ARP_REPLY); + + // Make tha the sha, and fill in sha with actual mac address + memcpy(arp->tha, arp->sha, MAC_ADDR_SIZE); + memcpy(arp->sha, mac, MAC_ADDR_SIZE); + + // Swap spa and tpa in arp packet + memcpy(tmp_addr, arp->tpa, IP_ADDR_SIZE); + memcpy(arp->tpa, arp->spa, IP_ADDR_SIZE); + memcpy(arp->spa, tmp_addr, IP_ADDR_SIZE); + + size = ceil_div(size + NET_IP_ALIGN, 8) * 8; + nic_send(buf, size); + + return 0; +} +static int process_icmp(void *buf, uint8_t *mac) +{ + struct eth_header *eth = buf; + struct ipv4_header *ipv4; + struct icmp_header *icmp; + int ihl, icmp_size; + ssize_t size; + uint32_t tmp_addr; + + // verify IPv4 + ipv4 = buf + sizeof(*eth); + ihl = ipv4->ver_ihl & 0xf; + + if (checksum((uint16_t *) ipv4, ihl << 1) != 0) { + printf("Bad IP header checksum %04x\n", ipv4->cksum); + return -1; + } + + if (ipv4->prot != ICMP_PROT) { + printf("Wrong IP protocol %d\n", ipv4->prot); + return -1; + } + + // verify ICMP + icmp = (buf + sizeof(*eth) + (ihl << 2)); + + if (icmp->type != ECHO_REQUEST) { + printf("Wrong ICMP type %d\n", icmp->type); + return -1; + } + + if (icmp->code != 0) { + printf("Wrong ICMP code %d\n", icmp->code); + return -1; + } + + icmp_size = ntohs(ipv4->length) - (ihl << 2); + if (checksum((uint16_t *) icmp, icmp_size >> 1) != 0) { + printf("Bad ICMP checksum %04x\n", icmp->cksum); + return -1; + } + + // Set the destination and source MACs + memcpy(eth->dst_mac, eth->src_mac, MAC_ADDR_SIZE); + memcpy(eth->src_mac, mac, MAC_ADDR_SIZE); + + // Swap the source and destination IP addresses + tmp_addr = ipv4->dst_addr; + ipv4->dst_addr = ipv4->src_addr; + ipv4->src_addr = tmp_addr; + + // compute the IPv4 header checksum + ipv4->cksum = 0; + ipv4->cksum = htons(checksum((uint16_t *) ipv4, ihl << 1)); + + // set the ICMP type to reply and compute checksum + icmp->cksum = 0; + icmp->type = ECHO_REPLY; + icmp->cksum = htons(checksum((uint16_t *) icmp, icmp_size >> 1)); + size = ntohs(ipv4->length) + ETH_HEADER_SIZE; + + size = ceil_div(size + NET_IP_ALIGN, 8) * 8; + nic_send(buf, size); + + return 0; +} + +static int process_packet(void *buf, uint8_t *mac) +{ + struct eth_header *eth; + + // read the ICMP request + nic_recv(buf); + eth = buf; + printf("Got packet: [ethtype=%04x]\n", ntohs(eth->ethtype)); + // Check ethernet type + switch (ntohs(eth->ethtype)) { + case IPV4_ETHTYPE: + return process_icmp(buf, mac); + case ARP_ETHTYPE: + return process_arp(buf, mac); + default: + printf("Wrong ethtype %x\n", ntohs(eth->ethtype)); + return -1; + } +} + +uint64_t buffer[ETH_MAX_WORDS]; + +int main(void) +{ + uint64_t macaddr_long; + uint8_t *macaddr; + + macaddr_long = nic_macaddr(); + macaddr = (uint8_t *) &macaddr_long; + + printf("macaddr - %02x", macaddr[0]); + for (int i = 1; i < MAC_ADDR_SIZE; i++) + printf(":%02x", macaddr[i]); + printf("\n"); + + for (;;) { + if (process_packet(buffer, macaddr)) + return -1; + } + + return 0; +} diff --git a/variables.mk b/variables.mk index 0808003c..ea48c81d 100644 --- a/variables.mk +++ b/variables.mk @@ -86,6 +86,18 @@ ifeq ($(SUB_PROJECT),hwacha) TB ?= TestDriver TOP ?= ExampleRocketSystem endif +# Stand-in firechip variables +ifeq ($(SUB_PROJECT),firechip) + SBT_PROJECT ?= $(SUB_PROJECT) + MODEL ?= TestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= firesim.firesim + CONFIG ?= FireSimRocketChipConfig + CONFIG_PACKAGE ?= firesim.firesim + GENERATOR_PACKAGE ?= firesim.firesim + TB ?= TestDriver + TOP ?= ExampleRocketSystem +endif ######################################################################################### # path to rocket-chip and testchipip From 2a58f387ed5abecdbda2547ca6dcf95c88fdb8c8 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 28 May 2019 01:50:39 +0000 Subject: [PATCH 002/160] Fix some test suite handling --- build.sbt | 4 ++-- generators/firechip/src/main/scala/TargetConfigs.scala | 2 +- generators/firechip/src/test/scala/ScalaTestSuite.scala | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/build.sbt b/build.sbt index 6e52c683..99d2ea3f 100644 --- a/build.sbt +++ b/build.sbt @@ -21,11 +21,11 @@ lazy val commonSettings = Seq( val rocketChipDir = file("generators/rocket-chip") -lazy val firesimAsLibrary = sys.env.get("FIRESIM_IS_TOP") == None +lazy val firesimAsLibrary = sys.env.get("FIRESIM_STANDALONE") == None lazy val firesimDir = if (firesimAsLibrary) { file("sims/firesim/sim/") } else { - file("../../sim/") + file("../../") } // Checks for -DROCKET_USE_MAVEN. diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 5c1cade1..6e20364d 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -17,7 +17,7 @@ import icenet._ class WithBootROM extends Config((site, here, up) => { case BootROMParams => { val rebarBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") - val firesimBootROM = new File(s"./target-rtl/testchipip/bootrom/bootrom.rv${site(XLen)}.img") + val firesimBootROM = new File(s"./target-rtl/firechip/generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") val bootROMPath = if (rebarBootROM.exists()) { rebarBootROM.getAbsolutePath() diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 588c7c2a..54848ac8 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -19,7 +19,7 @@ abstract class FireSimTestSuite( targetConfigs: String, platformConfigs: String, N: Int = 8 - ) extends firesim.midasexamples.TestSuiteCommon with HasFireSimGeneratorUtilities { + ) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { import scala.concurrent.duration._ import ExecutionContext.Implicits.global From a53abf18564703910298220b9de5594f920a2750 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 28 May 2019 22:51:39 +0000 Subject: [PATCH 003/160] Bring up FireSim tests --- build.sbt | 15 +++++++++++++- scripts/firesim-setup.sh | 16 +++++++++++++++ tests/Makefile | 2 +- tests/blkdev.c | 43 +++++++--------------------------------- tests/blkdev.h | 38 +++++++++++++++++++++++++++++++++++ 5 files changed, 76 insertions(+), 38 deletions(-) create mode 100755 scripts/firesim-setup.sh create mode 100644 tests/blkdev.h diff --git a/build.sbt b/build.sbt index 99d2ea3f..96fb588d 100644 --- a/build.sbt +++ b/build.sbt @@ -1,3 +1,5 @@ +import Tests._ + lazy val commonSettings = Seq( organization := "edu.berkeley.cs", version := "1.0", @@ -41,6 +43,14 @@ def conditionalDependsOn(prj: Project): Project = { } } +// Fork each scala test for now, to work around persistent mutable state +// in Rocket-Chip based generators +def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => + val options = ForkOptions() + new Group(test.name, Seq(test), SubProcess(options)) + } toSeq + + // Subproject definitions begin // Biancolin: get to the bottom of these @@ -117,5 +127,8 @@ lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) .dependsOn(boom, icenet, testchipip, sifive_blocks, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") - .settings(commonSettings) + .settings( + commonSettings, + testGrouping in Test := isolateAllTests( (definedTests in Test).value ) + ) diff --git a/scripts/firesim-setup.sh b/scripts/firesim-setup.sh new file mode 100755 index 00000000..e7596a96 --- /dev/null +++ b/scripts/firesim-setup.sh @@ -0,0 +1,16 @@ +#!/usr/bin/env bash + +# Sets up FireSim for use as a library within REBAR + +set -e +set -o pipefail + +RDIR=$(pwd) +scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" +sims_dir=$(scripts_dir)/../sims/ + +cd $sims_dir +git submodule update --init firesim +cd firesim +./build-setup.sh $@ --library +cd $RDIR diff --git a/tests/Makefile b/tests/Makefile index edabb264..80142ad7 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -3,7 +3,7 @@ OBJDUMP=riscv64-unknown-elf-objdump CFLAGS=-mcmodel=medany -std=gnu99 -O2 -fno-common -fno-builtin-printf -Wall LDFLAGS=-static -nostdlib -nostartfiles -lgcc -PROGRAMS = pwm blkdev accum charcount +PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd default: $(addsuffix .riscv,$(PROGRAMS)) diff --git a/tests/blkdev.c b/tests/blkdev.c index 7716b46a..994a341b 100644 --- a/tests/blkdev.c +++ b/tests/blkdev.c @@ -2,30 +2,7 @@ #include #include "mmio.h" - -#define BLKDEV_BASE 0x10015000 -#define BLKDEV_ADDR BLKDEV_BASE -#define BLKDEV_OFFSET (BLKDEV_BASE + 8) -#define BLKDEV_LEN (BLKDEV_BASE + 12) -#define BLKDEV_WRITE (BLKDEV_BASE + 16) -#define BLKDEV_REQUEST (BLKDEV_BASE + 17) -#define BLKDEV_NREQUEST (BLKDEV_BASE + 18) -#define BLKDEV_COMPLETE (BLKDEV_BASE + 19) -#define BLKDEV_NCOMPLETE (BLKDEV_BASE + 20) -#define BLKDEV_NSECTORS (BLKDEV_BASE + 24) -#define BLKDEV_MAX_REQUEST_LENGTH (BLKDEV_BASE + 28) -#define BLKDEV_SECTOR_SIZE 512 -#define BLKDEV_SECTOR_SHIFT 9 - -size_t blkdev_nsectors(void) -{ - return reg_read32(BLKDEV_NSECTORS); -} - -size_t blkdev_max_req_len(void) -{ - return reg_read32(BLKDEV_MAX_REQUEST_LENGTH); -} +#include "blkdev.h" void blkdev_read(void *addr, unsigned long offset, size_t nsectors) { @@ -38,12 +15,9 @@ void blkdev_read(void *addr, unsigned long offset, size_t nsectors) printf("sending %d reads\n", ntags); for (i = 0; i < ntags; i++) { - reg_write64(BLKDEV_ADDR, (unsigned long) addr); - reg_write32(BLKDEV_OFFSET, offset); - reg_write32(BLKDEV_LEN, nsectors_per_tag); - reg_write8(BLKDEV_WRITE, 0); - - req_tag = reg_read8(BLKDEV_REQUEST); + req_tag = blkdev_send_request( + (unsigned long) addr, offset, + nsectors_per_tag, 0); addr += (nsectors_per_tag << BLKDEV_SECTOR_SHIFT); offset += nsectors_per_tag; } @@ -67,12 +41,9 @@ void blkdev_write(unsigned long offset, void *addr, size_t nsectors) printf("sending %d writes\n", ntags); for (i = 0; i < ntags; i++) { - reg_write64(BLKDEV_ADDR, (unsigned long) addr); - reg_write32(BLKDEV_OFFSET, offset); - reg_write32(BLKDEV_LEN, nsectors_per_tag); - reg_write8(BLKDEV_WRITE, 1); - - req_tag = reg_read8(BLKDEV_REQUEST); + req_tag = blkdev_send_request( + (unsigned long) addr, offset, + nsectors_per_tag, 1); addr += (nsectors_per_tag << BLKDEV_SECTOR_SHIFT); offset += nsectors_per_tag; } diff --git a/tests/blkdev.h b/tests/blkdev.h new file mode 100644 index 00000000..be7ec064 --- /dev/null +++ b/tests/blkdev.h @@ -0,0 +1,38 @@ +#define BLKDEV_BASE 0x10015000 +#define BLKDEV_ADDR BLKDEV_BASE +#define BLKDEV_OFFSET (BLKDEV_BASE + 8) +#define BLKDEV_LEN (BLKDEV_BASE + 12) +#define BLKDEV_WRITE (BLKDEV_BASE + 16) +#define BLKDEV_REQUEST (BLKDEV_BASE + 17) +#define BLKDEV_NREQUEST (BLKDEV_BASE + 18) +#define BLKDEV_COMPLETE (BLKDEV_BASE + 19) +#define BLKDEV_NCOMPLETE (BLKDEV_BASE + 20) +#define BLKDEV_NSECTORS (BLKDEV_BASE + 24) +#define BLKDEV_MAX_REQUEST_LENGTH (BLKDEV_BASE + 28) +#define BLKDEV_SECTOR_SIZE 512 +#define BLKDEV_SECTOR_SHIFT 9 + +static inline size_t blkdev_nsectors(void) +{ + return reg_read32(BLKDEV_NSECTORS); +} + +static inline size_t blkdev_max_req_len(void) +{ + return reg_read32(BLKDEV_MAX_REQUEST_LENGTH); +} + +static inline unsigned int blkdev_send_request( + unsigned long addr, + unsigned int offset, + unsigned int len, + unsigned char write) +{ + reg_write64(BLKDEV_ADDR, addr); + reg_write32(BLKDEV_OFFSET, offset); + reg_write32(BLKDEV_LEN, len); + reg_write8(BLKDEV_WRITE, write); + + asm volatile ("fence"); + return reg_read8(BLKDEV_REQUEST); +} From baf7a6c30d7a4b8be18738c73050be5a0f322466 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 29 May 2019 00:50:40 +0000 Subject: [PATCH 004/160] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index ccfd85aa..0205a85d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ccfd85aa287bd158b87ab9160cb599ec7534553b +Subproject commit 0205a85d18bb819fb44e1d0b35a493ba05b042ad From 401a2b9da45985d4dde7d60a6c0c8bc0bc612547 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 29 May 2019 15:31:33 +0000 Subject: [PATCH 005/160] Update setup scripts --- scripts/firesim-setup.sh | 4 +++- scripts/init-submodules-no-riscv-tools.sh | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/scripts/firesim-setup.sh b/scripts/firesim-setup.sh index e7596a96..53dee5ab 100755 --- a/scripts/firesim-setup.sh +++ b/scripts/firesim-setup.sh @@ -7,8 +7,10 @@ set -o pipefail RDIR=$(pwd) scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" -sims_dir=$(scripts_dir)/../sims/ +sims_dir=$scripts_dir/../sims/ +# Reenable the FireSim submodule +git config --unset submodule.sims/firesim.update || true cd $sims_dir git submodule update --init firesim cd firesim diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 27005cbb..ee5a6bb0 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -13,6 +13,8 @@ RDIR=$(pwd) git config --global submodule.riscv-tools.update none git config --global submodule.esp-tools.update none git config --global submodule.experimental-blocks.update none +# Disable updates to the FireSim submodule until explicitly requested +git config submodule.sims/firesim.update none git submodule update --init --recursive #--jobs 8 # unignore riscv-tools,catapult-shell2 globally git config --global --unset submodule.riscv-tools.update From 0cb1608e2c31c4e1fcf29077c6d407ecb1e779c9 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 29 May 2019 15:34:56 +0000 Subject: [PATCH 006/160] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 0205a85d..17ea4596 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 0205a85d18bb819fb44e1d0b35a493ba05b042ad +Subproject commit 17ea459654fb8a41173c3d04369cbd849ac44ce0 From f4fb0c42b1e547dfa815b225b482166b92743de5 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 29 May 2019 22:26:04 +0000 Subject: [PATCH 007/160] Fix a number of build.sbt related problems --- build.sbt | 21 +++++++------------ common.mk | 4 ++-- .../firechip/src/main/scala/Generator.scala | 9 ++++++++ scripts/init-submodules-no-riscv-tools.sh | 11 ++++++++++ variables.mk | 6 +++--- 5 files changed, 32 insertions(+), 19 deletions(-) diff --git a/build.sbt b/build.sbt index 96fb588d..1e283547 100644 --- a/build.sbt +++ b/build.sbt @@ -50,15 +50,8 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => new Group(test.name, Seq(test), SubProcess(options)) } toSeq - // Subproject definitions begin -// Biancolin: get to the bottom of these -//lazy val rebarFirrtl = (project in file("tools/firrtl")) -// .settings(commonSettings) -// Overlaps with the dependency-injected version -// lazy val rocketchip = RootProject(rocketChipDir) - // NB: FIRRTL dependency is unmanaged (and dropped in sim/lib) lazy val chisel = (project in rocketChipDir / "chisel3") @@ -76,7 +69,7 @@ lazy val rocketMacros = (project in rocketChipDir / "macros") // HACK: I'm strugging to override settings in rocket-chip's build.sbt (i want // the subproject to register a new library dependendency on midas's targetutils library) // So instead, avoid the existing build.sbt altogether and specify the project's root at src/ -lazy val rebarRocketchip = (project in rocketChipDir / "src") +lazy val rocketchip = (project in rocketChipDir / "src") .settings( commonSettings, scalaSource in Compile := baseDirectory.value / "main" / "scala", @@ -84,7 +77,7 @@ lazy val rebarRocketchip = (project in rocketChipDir / "src") .dependsOn(chisel, hardfloat, rocketMacros) lazy val testchipip = (project in file("generators/testchipip")) - .dependsOn(rebarRocketchip) + .dependsOn(rocketchip) .settings(commonSettings) lazy val example = conditionalDependsOn(project in file("generators/example")) @@ -95,15 +88,15 @@ lazy val utilities = conditionalDependsOn(project in file("generators/utilities" .settings(commonSettings) lazy val icenet = (project in file("generators/icenet")) - .dependsOn(rebarRocketchip, testchipip) + .dependsOn(rocketchip, testchipip) .settings(commonSettings) lazy val hwacha = (project in file("generators/hwacha")) - .dependsOn(rebarRocketchip) + .dependsOn(rocketchip) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) - .dependsOn(rebarRocketchip) + .dependsOn(rocketchip) .settings(commonSettings) lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) @@ -113,12 +106,12 @@ lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) .settings(commonSettings) lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) - .dependsOn(mdf, rebarRocketchip) + .dependsOn(mdf, rocketchip) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) - .dependsOn(rebarRocketchip) + .dependsOn(rocketchip) .settings(commonSettings) // Library components of FireSim diff --git a/common.mk b/common.mk index 37e2523e..4efd9846 100644 --- a/common.mk +++ b/common.mk @@ -62,11 +62,11 @@ $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRR # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs MACROCOMPILER_MODE ?= --mode synflops $(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) - cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)" + cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)" HARNESS_MACROCOMPILER_MODE = --mode synflops $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) - cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" + cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" ######################################################################################### # helper rule to just make verilog files diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index 56ae824e..06febd3a 100755 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -122,3 +122,12 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike { generateArtefacts generateTclEnvFile } + +// For now, provide a separate generator app when not specifically building for FireSim +object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites { + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs + generateFirrtl + generateAnno + generateTestSuiteMakefrags + generateArtefacts +} diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index ee5a6bb0..64452d40 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -6,6 +6,7 @@ set -o pipefail unamestr=$(uname) RDIR=$(pwd) +scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" # ignore riscv-tools for submodule init recursive # you must do this globally (otherwise riscv-tools deep @@ -19,3 +20,13 @@ git submodule update --init --recursive #--jobs 8 # unignore riscv-tools,catapult-shell2 globally git config --global --unset submodule.riscv-tools.update git config --global --unset submodule.experimental-blocks.update + +# Renable firesim and init only the required submodules to provide +# all required scala deps, without doing a full build-setup +git config --unset submodule.sims/firesim.update +cd $scripts_dir/../sims/ +git submodule update --init firesim +cd firesim/sim +git submodule update --init midas +cd $RDIR +git config submodule.sims/firesim.update none diff --git a/variables.mk b/variables.mk index ea48c81d..a9039343 100644 --- a/variables.mk +++ b/variables.mk @@ -64,7 +64,7 @@ ifeq ($(SUB_PROJECT),boom) endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) - SBT_PROJECT ?= rebarrocketchip + SBT_PROJECT ?= rocketchip MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= freechips.rocketchip.system @@ -91,12 +91,12 @@ ifeq ($(SUB_PROJECT),firechip) SBT_PROJECT ?= $(SUB_PROJECT) MODEL ?= TestHarness VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= firesim.firesim + MODEL_PACKAGE ?= freechips.rocketchip.system CONFIG ?= FireSimRocketChipConfig CONFIG_PACKAGE ?= firesim.firesim GENERATOR_PACKAGE ?= firesim.firesim TB ?= TestDriver - TOP ?= ExampleRocketSystem + TOP ?= FireSimNoNIC endif ######################################################################################### From d9a82e914cfc77bfdc5f2fb381c304ae4c290a66 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 29 May 2019 22:29:24 +0000 Subject: [PATCH 008/160] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 17ea4596..ddad6761 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 17ea459654fb8a41173c3d04369cbd849ac44ce0 +Subproject commit ddad676138290c6d5e72881ec91815d5447b030b From 19e092b26a1a1aeb566ebb537859e02f0dd21ead Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 1 Jun 2019 15:14:25 -0700 Subject: [PATCH 009/160] Bump boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 2f8c419f..0246aceb 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 2f8c419ff8fa7d848d0d92d4977885cb1e1fa5b3 +Subproject commit 0246aceb0443531a5f0d6525afcbe5fbe15b7c1d From eb93ace725e7db0324f16ddea85dc78d79436a0c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 2 Jun 2019 23:25:51 -0700 Subject: [PATCH 010/160] check if commit is on master --- .circleci/check-commit.sh | 40 +++++++++++++++++++++++++++++++++++++++ .circleci/config.yml | 19 +++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100755 .circleci/check-commit.sh diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh new file mode 100755 index 00000000..7b0ec9e5 --- /dev/null +++ b/.circleci/check-commit.sh @@ -0,0 +1,40 @@ +#!/bin/bash + +# check to see that submodule commits are present on the master branch + +# turn echo on and error on earliest command +set -ex + +# enter bhd repo +cd $HOME/project + +# initialize submodules and get the hashes +git submodule update --init +status=$(git submodule status) + +search () { + for submodule in "${submodules[@]}" + do + echo "Running check on submodule $submodule in $dir" + hash=$(echo "$status" | grep $submodule | awk '{print$1}' | grep -o "[[:alnum:]]*") + echo "Searching for $hash in origin/master of $submodule" + git -C $dir/$submodule log origin/master | grep "$hash" # needs init'ed submodules + done +} + +submodules=("boom" "hwacha" "rocket-chip" "sifive-blocks" "testchipip") +dir="generators" + +search + +submodules=("esp-tools" "riscv-tools") +dir="toolchains" + +search + +submodules=("barstools" "chisel3" "firrtl" "torture") +dir="tools" + +search + +echo "Done checking all submodules" diff --git a/.circleci/config.yml b/.circleci/config.yml index d2354fde..0f982233 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -5,6 +5,22 @@ version: 2 # set of jobs to run jobs: + commit-on-master-check: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Check commits of each submodule + command: | + .circleci/check-commit.sh + install-riscv-toolchain: docker: - image: riscvboom/riscvboom-images:0.0.5 @@ -470,6 +486,9 @@ workflows: version: 2 build-and-test-rebar-integration: jobs: + # check to make sure commits are on master + - commit-on-master-check + # Make the toolchains - install-riscv-toolchain From bbaa8d58b058c76c10a4457c18e3a84b2a6a19ac Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 3 Jun 2019 09:41:56 -0700 Subject: [PATCH 011/160] switch to git branch --- .circleci/check-commit.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 7b0ec9e5..ea7e30f5 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -18,7 +18,7 @@ search () { echo "Running check on submodule $submodule in $dir" hash=$(echo "$status" | grep $submodule | awk '{print$1}' | grep -o "[[:alnum:]]*") echo "Searching for $hash in origin/master of $submodule" - git -C $dir/$submodule log origin/master | grep "$hash" # needs init'ed submodules + git -C $dir/$submodule branch -r --contains "$hash" | grep "origin/master" # needs init'ed submodules done } From 51960f4345e23fe7365301944c31d40d9fc07116 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 3 Jun 2019 19:11:45 -0700 Subject: [PATCH 012/160] remove deprecated CHISEL_ARGS --- common.mk | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/common.mk b/common.mk index f7e46608..ff67066a 100644 --- a/common.mk +++ b/common.mk @@ -37,11 +37,9 @@ $(sim_dotf): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/ ######################################################################################### # create firrtl file rule and variables ######################################################################################### -CHISEL_ARGS ?= - $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) mkdir -p $(build_dir) - cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(CHISEL_ARGS) $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" + cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" ######################################################################################### # create verilog files rules and variables From af8f0b0507efa547be5062cd9203173ddaac5df5 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 10 Jun 2019 13:56:38 -0700 Subject: [PATCH 013/160] update naming in accordance with boom --- generators/example/src/main/scala/Top.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 5ee73906..a3fa99f8 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -16,13 +16,13 @@ import sifive.blocks.devices.gpio._ // BOOM and/or Rocket Top Level Systems // ------------------------------- -class BoomRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem +class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem with HasNoDebug with HasPeripherySerial { override lazy val module = new BoomRocketTopModule(this) } -class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) +class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.BoomRocketSystemModule(l) with HasNoDebugModuleImp with HasPeripherySerialModuleImp with DontTouch From a906f05962042e413c1d2ddd0747e51f511079cc Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 11 Jun 2019 17:55:32 -0700 Subject: [PATCH 014/160] use hart0 for the test suite --- generators/example/src/main/scala/Generator.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/example/src/main/scala/Generator.scala b/generators/example/src/main/scala/Generator.scala index c5df8cb1..684b2834 100644 --- a/generators/example/src/main/scala/Generator.scala +++ b/generators/example/src/main/scala/Generator.scala @@ -57,11 +57,11 @@ object Generator extends GeneratorApp { import freechips.rocketchip.system.DefaultTestSuites._ val xlen = params(XLen) - // TODO: for now only generate tests for the first rocket/boom tile in the subsystem // TODO: support heterogenous systems? + // TODO: generate tests for hart0 of the system since asm tests run on hart0 by default // rocket specific tests - params(RocketTilesKey).headOption.map { tileParams => + params(RocketTilesKey).find(_.hartId == 0).map { tileParams => val coreParams = tileParams.core val vm = coreParams.useVM val env = if (vm) List("p","v") else List("p") @@ -95,7 +95,7 @@ object Generator extends GeneratorApp { } // boom specific tests - params(BoomTilesKey).headOption.map { tileParams => + params(BoomTilesKey).find(_.hartId == 0).map { tileParams => val coreParams = tileParams.core val vm = coreParams.useVM val env = if (vm) List("p","v") else List("p") From ba6352afca7c0b873d5fcfbac0142020b4e7cc4b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 12 Jun 2019 14:25:32 -0700 Subject: [PATCH 015/160] update boom hash --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 0246aceb..22c5f9ec 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 0246aceb0443531a5f0d6525afcbe5fbe15b7c1d +Subproject commit 22c5f9ec3f0325b9bdbf1a98b5752b6ac843eb19 From 4a667c3df94a9e6309e09ad207677ec5d1b74944 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 12 Jun 2019 14:54:49 -0700 Subject: [PATCH 016/160] correct naming in defaults --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index f3fc05b1..76632f48 100644 --- a/variables.mk +++ b/variables.mk @@ -48,7 +48,7 @@ ifeq ($(SUB_PROJECT),boom) CONFIG_PACKAGE ?= boom.system GENERATOR_PACKAGE ?= boom.system TB ?= TestDriver - TOP ?= ExampleBoomAndRocketSystem + TOP ?= BoomRocketSystem endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) From 9d117b8584b3a741899719822cbae6f57cfe1781 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 14 Jun 2019 15:07:31 -0700 Subject: [PATCH 017/160] use generator functions from boom | bump boom --- generators/boom | 2 +- .../example/src/main/scala/Generator.scala | 134 ++---------------- 2 files changed, 10 insertions(+), 126 deletions(-) diff --git a/generators/boom b/generators/boom index 22c5f9ec..cee609e1 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 22c5f9ec3f0325b9bdbf1a98b5752b6ac843eb19 +Subproject commit cee609e1b144427ffaf8cc3b3bade2b0bce97b1d diff --git a/generators/example/src/main/scala/Generator.scala b/generators/example/src/main/scala/Generator.scala index 684b2834..92658038 100644 --- a/generators/example/src/main/scala/Generator.scala +++ b/generators/example/src/main/scala/Generator.scala @@ -1,140 +1,24 @@ package example -import scala.collection.mutable.LinkedHashSet - import chisel3._ -import chisel3.experimental._ -import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} - -import freechips.rocketchip.subsystem.{RocketTilesKey} -import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.util.{GeneratorApp} -import freechips.rocketchip.tile.{XLen} -import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} -import boom.system.{BoomTilesKey, BoomTestSuites} +import boom.system.{BoomTilesKey, TestSuiteHelper} object Generator extends GeneratorApp { - val rv64RegrTestNames = LinkedHashSet( - "rv64ud-v-fcvt", - "rv64ud-p-fdiv", - "rv64ud-v-fadd", - "rv64uf-v-fadd", - "rv64um-v-mul", - "rv64mi-p-breakpoint", - "rv64uc-v-rvc", - "rv64ud-v-structural", - "rv64si-p-wfi", - "rv64um-v-divw", - "rv64ua-v-lrsc", - "rv64ui-v-fence_i", - "rv64ud-v-fcvt_w", - "rv64uf-v-fmin", - "rv64ui-v-sb", - "rv64ua-v-amomax_d", - "rv64ud-v-move", - "rv64ud-v-fclass", - "rv64ua-v-amoand_d", - "rv64ua-v-amoxor_d", - "rv64si-p-sbreak", - "rv64ud-v-fmadd", - "rv64uf-v-ldst", - "rv64um-v-mulh", - "rv64si-p-dirty") - - val rv32RegrTestNames = LinkedHashSet( - "rv32mi-p-ma_addr", - "rv32mi-p-csr", - "rv32ui-p-sh", - "rv32ui-p-lh", - "rv32uc-p-rvc", - "rv32mi-p-sbreak", - "rv32ui-p-sll") - + // add unique test suites override def addTestSuites { - import freechips.rocketchip.system.DefaultTestSuites._ - val xlen = params(XLen) - - // TODO: support heterogenous systems? - // TODO: generate tests for hart0 of the system since asm tests run on hart0 by default - - // rocket specific tests - params(RocketTilesKey).find(_.hartId == 0).map { tileParams => - val coreParams = tileParams.core - val vm = coreParams.useVM - val env = if (vm) List("p","v") else List("p") - coreParams.fpu foreach { case cfg => - if (xlen == 32) { - TestGeneration.addSuites(env.map(rv32uf)) - if (cfg.fLen >= 64) - TestGeneration.addSuites(env.map(rv32ud)) - } else { - TestGeneration.addSuite(rv32udBenchmarks) - TestGeneration.addSuites(env.map(rv64uf)) - if (cfg.fLen >= 64) - TestGeneration.addSuites(env.map(rv64ud)) - } - } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) - TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - else - TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) - } - if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) - - TestGeneration.addSuites(rvi.map(_("p"))) - TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - TestGeneration.addSuite(benchmarks) - TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) - } - - // boom specific tests - params(BoomTilesKey).find(_.hartId == 0).map { tileParams => - val coreParams = tileParams.core - val vm = coreParams.useVM - val env = if (vm) List("p","v") else List("p") - coreParams.fpu foreach { case cfg => - if (xlen == 32) { - TestGeneration.addSuites(env.map(rv32uf)) - if (cfg.fLen >= 64) { - TestGeneration.addSuites(env.map(rv32ud)) - } - } else if (cfg.fLen >= 64) { - TestGeneration.addSuites(env.map(rv64ud)) - TestGeneration.addSuites(env.map(rv64uf)) - TestGeneration.addSuite(rv32udBenchmarks) - } - } - if (coreParams.useAtomics) { - if (tileParams.dcache.flatMap(_.scratch).isEmpty) { - TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) - } else { - TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) - } - } - if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) - - // Include our BOOM-specific overrides. - val (rvi, rvu) = - if (xlen == 64) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) - - TestGeneration.addSuites(rvi.map(_("p"))) - TestGeneration.addSuites(rvu.map(_("p"))) - TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - TestGeneration.addSuite(benchmarks) - rv64RegrTestNames -= "rv64mi-p-breakpoint" // TODO: breakpoints not implemented yet - TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) - } + implicit val p: Parameters = params + TestSuiteHelper.addRocketTestSuites + TestSuiteHelper.addBoomTestSuites } + // specify the name that the generator outputs files as val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs + + // generate files generateFirrtl generateAnno generateTestSuiteMakefrags From 4cca0ed57e5a9751f7d31940743e6fcfb07f88bb Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Jun 2019 09:35:46 -0700 Subject: [PATCH 018/160] bump verilator version --- sims/verisim/verilator.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/verisim/verilator.mk b/sims/verisim/verilator.mk index a5c953c1..4edfa6e3 100644 --- a/sims/verisim/verilator.mk +++ b/sims/verisim/verilator.mk @@ -5,7 +5,7 @@ ######################################################################################### # verilator version, binary, and path ######################################################################################### -VERILATOR_VERSION=4.008 +VERILATOR_VERSION=4.016 VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) @@ -15,7 +15,7 @@ INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) $(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata touch $@ - + .PHONY: verilator_install: $(INSTALLED_VERILATOR) From b556bee0b9a1500cad165033f56990db9ab3a824 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Jun 2019 11:28:35 -0700 Subject: [PATCH 019/160] rename to "Chipyard" --- .circleci/README.md | 12 ++++++------ .circleci/build-toolchains.sh | 2 +- .circleci/config.yml | 2 +- README.md | 16 ++++++++-------- build.sbt | 16 ++++++++-------- common.mk | 6 +++--- docs/Generators/index.rst | 2 +- .../Adding-An-Accelerator-Tutorial.rst | 6 +++--- .../{REBAR-Basics.rst => Chipyard-Basics.rst} | 6 +++--- ...-mixins.rst => Chipyard-Generator-Mixins.rst} | 0 .../Configs-Parameters-Mixins.rst | 4 ++-- docs/Getting-Started/Development-Ecosystem.rst | 6 +++--- docs/Getting-Started/Running-A-Simulation.rst | 6 +++--- docs/Getting-Started/index.rst | 6 +++--- docs/Makefile | 2 +- docs/Simulation/Commercial-Simulators.rst | 2 +- docs/Simulation/FPGA-Based-Simulators.rst | 4 ++-- docs/Simulation/Open-Source-Simulators.rst | 2 +- docs/Simulation/index.rst | 4 ++-- docs/Tools/index.rst | 2 +- docs/VLSI/index.rst | 2 +- docs/conf.py | 14 +++++++------- docs/index.rst | 8 ++++---- scripts/build-toolchains.sh | 6 +++--- scripts/gen-tags.sh | 4 ++-- variables.mk | 8 ++++---- 26 files changed, 74 insertions(+), 74 deletions(-) rename docs/Getting-Started/{REBAR-Basics.rst => Chipyard-Basics.rst} (97%) rename docs/Getting-Started/{rebar-generator-mixins.rst => Chipyard-Generator-Mixins.rst} (100%) diff --git a/.circleci/README.md b/.circleci/README.md index 50ede340..018b4b57 100644 --- a/.circleci/README.md +++ b/.circleci/README.md @@ -1,5 +1,5 @@ -REBAR CI -======== +Chipyard CI +=========== Website: https://circleci.com/gh/ucb-bar/project-template @@ -32,17 +32,17 @@ Here the key is built from a string where the `checksum` portion converts the fi .circleci directory ------------------- -This directory contains all the collateral for the REBAR CI to work. +This directory contains all the collateral for the Chipyard CI to work. The following is included: - + build-toolchains.sh # build either riscv-tools or esp-tools build-verilator.sh # build verilator create-hash.sh # create hashes of riscv-tools/esp-tools so circleci caching can work do-rtl-build.sh # use verilator to build a sim executable config.yml # main circleci config script to enumerate jobs/workflows -How things are setup for REBAR ------------------------------- +How things are setup for Chipyard +--------------------------------- The steps for CI to run are as follows. 1st, build the toolchains in parallel (note: `esp-tools` is currently not used in the run). diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index 28b87caa..9b5477f6 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -11,5 +11,5 @@ if [ ! -d "$HOME/$1-install" ]; then cd $HOME/ # init all submodules including the tools - REBAR_DIR=$HOME/project ./project/scripts/build-toolchains.sh $1 + CHIPYARD_DIR=$HOME/project ./project/scripts/build-toolchains.sh $1 fi diff --git a/.circleci/config.yml b/.circleci/config.yml index 0f982233..61e73e54 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -484,7 +484,7 @@ jobs: # Order and dependencies of jobs to run workflows: version: 2 - build-and-test-rebar-integration: + build-and-test-chipyard-integration: jobs: # check to make sure commits are on master - commit-on-master-check diff --git a/README.md b/README.md index 2bf6a212..708de178 100644 --- a/README.md +++ b/README.md @@ -1,20 +1,20 @@ -# REBAR Framework [![CircleCI](https://circleci.com/gh/ucb-bar/project-template/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/project-template/tree/master) +# Chipyard Framework [![CircleCI](https://circleci.com/gh/ucb-bar/project-template/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/project-template/tree/master) -## Using REBAR +## Using Chipyard -To get started using REBAR, see the documentation on the REBAR documentation site: https://bar-project-template.readthedocs.io/en/latest/ +To get started using Chipyard, see the documentation on the Chipyard documentation site: https://bar-project-template.readthedocs.io/en/latest/ -## What is REBAR +## What is Chipyard -REBAR is an open source starter template for your custom Chisel project. +Chipyard is an open source starter template for your custom Chisel project. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. It contains processor cores ([Rocket][rocket-chip], [BOOM][boom]), accelerators ([Hwacha][hwacha]), FPGA simulation tools ([FireSim][firesim]), ASIC tools ([HAMMER][hammer]) and other tooling to help create a full featured SoC. -REBAR is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. +Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. ## Resources -* REBAR Website: ...TBD at a later date... -* REBAR Documentation: https://bar-project-template.readthedocs.io/ +* Chipyard Website: ...TBD at a later date... +* Chipyard Documentation: https://bar-project-template.readthedocs.io/ [hwacha]:http://hwacha.org [hammer]:https://github.com/ucb-bar/hammer diff --git a/build.sbt b/build.sbt index 6a06fcba..09c78b34 100644 --- a/build.sbt +++ b/build.sbt @@ -19,17 +19,17 @@ lazy val commonSettings = Seq( Resolver.sonatypeRepo("releases"), Resolver.mavenLocal)) -lazy val rebarFirrtl = (project in file("tools/firrtl")) +lazy val chipyardFirrtl = (project in file("tools/firrtl")) .settings(commonSettings) lazy val rocketchip = RootProject(file("generators/rocket-chip")) -lazy val rebarrocketchip = project +lazy val chipyardrocketchip = project .dependsOn(rocketchip) .settings(commonSettings) lazy val testchipip = (project in file("generators/testchipip")) - .dependsOn(rebarrocketchip) + .dependsOn(chipyardrocketchip) .settings(commonSettings) // Checks for -DROCKET_USE_MAVEN. @@ -53,25 +53,25 @@ lazy val utilities = conditionalDependsOn(project in file("generators/utilities" .settings(commonSettings) lazy val hwacha = (project in file ("generators/hwacha")) - .dependsOn(rebarrocketchip) + .dependsOn(chipyardrocketchip) .settings(commonSettings) lazy val boom = (project in file("generators/boom")) - .dependsOn(rebarrocketchip) + .dependsOn(chipyardrocketchip) .settings(commonSettings) lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) - .dependsOn(rebarFirrtl) + .dependsOn(chipyardFirrtl) .settings(commonSettings) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) .settings(commonSettings) lazy val `barstools-macros` = (project in file("./tools/barstools/macros/")) - .dependsOn(mdf, rebarrocketchip, rebarFirrtl) + .dependsOn(mdf, chipyardrocketchip, chipyardFirrtl) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) lazy val sifive_blocks = (project in file("generators/sifive-blocks")) - .dependsOn(rebarrocketchip) + .dependsOn(chipyardrocketchip) .settings(commonSettings) diff --git a/common.mk b/common.mk index ff67066a..bd61184b 100644 --- a/common.mk +++ b/common.mk @@ -22,10 +22,10 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class ######################################################################################### FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar -$(FIRRTL_JAR): $(call lookup_scala_srcs, $(REBAR_FIRRTL_DIR)/src/main/scala) - $(MAKE) -C $(REBAR_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(REBAR_FIRRTL_DIR) build-scala +$(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala) + $(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala mkdir -p $(dir $@) - cp -p $(REBAR_FIRRTL_DIR)/utils/bin/firrtl.jar $@ + cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@ touch $@ ######################################################################################### diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 765b2549..a01b5adc 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -5,7 +5,7 @@ Generator can be thought of as a generalized RTL design, written using a mix of This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Chisel`). A standard RTL design is essentially just a single instance of a design coming from a generator. However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. -The following pages introduce the generators integrated with the REBAR framework. +The following pages introduce the generators integrated with the Chipyard framework. .. toctree:: :maxdepth: 2 diff --git a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst index bad5ceef..4eefe9b8 100644 --- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst +++ b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst @@ -28,7 +28,7 @@ Integrating into the Generator Build System ------------------------------------------- While developing, you want to include Chisel code in a submodule so that it can be shared by different projects. -To add a submodule to the REBAR framework, make sure that your project is organized as follows. +To add a submodule to the Chipyard framework, make sure that your project is organized as follows. .. code-block:: none @@ -45,7 +45,7 @@ Then add it as a submodule to under the following directory hierarchy: ``generat cd generators/ git submodule add https://git-repository.com/yourproject.git -Then add ``yourproject`` to the REBAR top-level build.sbt file. +Then add ``yourproject`` to the Chipyard top-level build.sbt file. .. code-block:: scala @@ -59,7 +59,7 @@ the ``example`` project, change the final line in build.sbt to the following. lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) -Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the REBAR top level. +Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the Chipyard top level. This will allow make to detect that your source files have changed when building the Verilog/FIRRTL files. MMIO Peripheral diff --git a/docs/Getting-Started/REBAR-Basics.rst b/docs/Getting-Started/Chipyard-Basics.rst similarity index 97% rename from docs/Getting-Started/REBAR-Basics.rst rename to docs/Getting-Started/Chipyard-Basics.rst index 5dcac5d7..7b9f1bbe 100644 --- a/docs/Getting-Started/REBAR-Basics.rst +++ b/docs/Getting-Started/Chipyard-Basics.rst @@ -1,10 +1,10 @@ -REBAR Basics +Chipyard Basics =============================== Generators ------------------------------------------- -The REBAR Framework currently consists of the following RTL generators: +The Chipyard Framework currently consists of the following RTL generators: Processor Cores ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -72,7 +72,7 @@ Toolchains A collection of software toolchains used to develop and execute software on the RISC-V ISA. The include compiler and assembler toolchains, functional ISA simulator (spike), the Berkeley Boot Loader (BBL) and proxy kernel. The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.). - Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the REBAR framework. + Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the Chipyard framework. **esp-tools** A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension. diff --git a/docs/Getting-Started/rebar-generator-mixins.rst b/docs/Getting-Started/Chipyard-Generator-Mixins.rst similarity index 100% rename from docs/Getting-Started/rebar-generator-mixins.rst rename to docs/Getting-Started/Chipyard-Generator-Mixins.rst diff --git a/docs/Getting-Started/Configs-Parameters-Mixins.rst b/docs/Getting-Started/Configs-Parameters-Mixins.rst index 852f85af..d9becfdf 100644 --- a/docs/Getting-Started/Configs-Parameters-Mixins.rst +++ b/docs/Getting-Started/Configs-Parameters-Mixins.rst @@ -1,7 +1,7 @@ Configs, Parameters, Mix-ins, and Everything In Between ======================================================== -A significant portion of generators in the REBAR framework use the Rocket Chip parameter system. +A significant portion of generators in the Chipyard framework use the Rocket Chip parameter system. This parameter system enables for the flexible configuration of the SoC without invasive RTL changes. In order to use the parameter system correctly, we will use several terms and conventions: @@ -69,7 +69,7 @@ Cake Pattern ------------------------- A cake pattern is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection). -It is used in the Rocket Chip SoC library and REBAR framework in merging multiple system components and IO interfaces into a large system component. +It is used in the Rocket Chip SoC library and Chipyard framework in merging multiple system components and IO interfaces into a large system component. :numref:`cake-example` shows a Rocket Chip based SoC that merges multiple system components (BootROM, UART, etc) into a single top-level design. diff --git a/docs/Getting-Started/Development-Ecosystem.rst b/docs/Getting-Started/Development-Ecosystem.rst index fa407194..7755a7f3 100644 --- a/docs/Getting-Started/Development-Ecosystem.rst +++ b/docs/Getting-Started/Development-Ecosystem.rst @@ -1,12 +1,12 @@ Development Ecosystem =============================== -REBAR Approach +Chipyard Approach ------------------------------------------- The trend towards agile hardware design and evaluation provides an ecosystem of debugging and implementation tools, that make it easier for computer architecture researchers to develop novel concepts. -REBAR hopes to build on this prior work in order to create a singular location to which multiple projects within the `Berkeley Architecture Research `__ can coexist and be used together. -REBAR aims to be the "one-stop shop" for creating and testing your own unique System on a Chip (SoC). +Chipyard hopes to build on this prior work in order to create a singular location to which multiple projects within the `Berkeley Architecture Research `__ can coexist and be used together. +Chipyard aims to be the "one-stop shop" for creating and testing your own unique System on a Chip (SoC). Chisel/FIRRTL ------------------------------------------- diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index 673bf0ae..0cc4a024 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -1,13 +1,13 @@ Running A Simulation ======================================================== -REBAR provides support and integration for multiple simulation flows, for various user levels and requirements. +Chipyard provides support and integration for multiple simulation flows, for various user levels and requirements. In the majority of cases during a digital design development process, simple software RTL simulation is needed. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. Software RTL Simulation ------------------------ -The REBAR framework provides wrappers for two common software RTL simulators: +The Chipyard framework provides wrappers for two common software RTL simulators: the open-source Verilator simulator and the proprietary VCS simulator. For more information on either of these simulators, please refer to :ref:`Verilator` or :ref:`VCS`. The following instructions assume at least one of these simulators is installed. @@ -97,7 +97,7 @@ FireSim enables simulations at 1000x-100000x the speed of standard software simu This is enabled using FPGA-acceleration on F1 instances of the AWS (Amazon Web Services) public cloud. Therefore FireSim simulation requires to be set-up on the AWS public cloud rather than on our local development machine. -To run an FPGA-accelerated simulation using FireSim, a we need to clone the REBAR repository (or our fork of the REBAR repository) to an AWS EC2, and follow the setup instructions specified in the FireSim Initial Setup documentation page. +To run an FPGA-accelerated simulation using FireSim, a we need to clone the Chipyard repository (or our fork of the Chipyard repository) to an AWS EC2, and follow the setup instructions specified in the FireSim Initial Setup documentation page. After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design. We will work from within the ``sims/firesim`` directory. diff --git a/docs/Getting-Started/index.rst b/docs/Getting-Started/index.rst index be6aa1e3..dcfe0802 100644 --- a/docs/Getting-Started/index.rst +++ b/docs/Getting-Started/index.rst @@ -1,7 +1,7 @@ Getting Started ================================ -These guides will walk you through the basics of the REBAR framework: +These guides will walk you through the basics of the Chipyard framework: - First, we will go over the different configurations available. @@ -13,9 +13,9 @@ Hit next to get started! :maxdepth: 2 :caption: Getting Started: - REBAR-Basics + Chipyard-Basics Configs-Parameters-Mixins Adding-An-Accelerator-Tutorial Initial-Repo-Setup Running-A-Simulation - rebar-generator-mixins + Chipyard-Generator-Mixins diff --git a/docs/Makefile b/docs/Makefile index b3492e6c..adea9f26 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -4,7 +4,7 @@ # You can set these variables from the command line. SPHINXOPTS = SPHINXBUILD = python -msphinx -SPHINXPROJ = REBAR +SPHINXPROJ = Chipyard SOURCEDIR = . BUILDDIR = _build diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Commercial-Simulators.rst index 8c1c34d7..0e971d51 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/Commercial-Simulators.rst @@ -6,7 +6,7 @@ VCS `VCS `__ is a commercial RTL simulator developed by Synopsys. It requires commercial licenses. -The REBAR framework can compile and execute simulations using VCS. +The Chipyard framework can compile and execute simulations using VCS. VCS simulation will generally compile faster than Verilator simulations. To run a simulation using VCS, perform the following steps: diff --git a/docs/Simulation/FPGA-Based-Simulators.rst b/docs/Simulation/FPGA-Based-Simulators.rst index 9ef19d49..1180b470 100644 --- a/docs/Simulation/FPGA-Based-Simulators.rst +++ b/docs/Simulation/FPGA-Based-Simulators.rst @@ -9,9 +9,9 @@ FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than so FireSim also provides additional device models to allow full-system simulation, including memory models and network models. FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. -In order to simulate your REBAR design using FireSim, you should follow the following steps: +In order to simulate your Chipyard design using FireSim, you should follow the following steps: Follow the initial EC2 setup instructions as detailed in the `FireSim documentation `__. -Then clone your full REBAR repository onto your Amazon EC2 FireSim manager instance. +Then clone your full Chipyard repository onto your Amazon EC2 FireSim manager instance. Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for `running a simulation `__. diff --git a/docs/Simulation/Open-Source-Simulators.rst b/docs/Simulation/Open-Source-Simulators.rst index 11d8d696..bc8a0dcc 100644 --- a/docs/Simulation/Open-Source-Simulators.rst +++ b/docs/Simulation/Open-Source-Simulators.rst @@ -5,7 +5,7 @@ Verilator ----------------------- `Verilator `__ is an open-source LGPL-Licensed simulator maintained by `Veripool `__. -The REBAR framework can download, build, and execute simulations using Verilator. +The Chipyard framework can download, build, and execute simulations using Verilator. To run a simulation using Verilator, perform the following steps: diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index d61b5ed7..339960bd 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,10 +1,10 @@ Simulators ======================= -REBAR provides support and integration for multiple simulation flows, for various user levels and requirements. +Chipyard provides support and integration for multiple simulation flows, for various user levels and requirements. In the majority of cases during a digital design development process, a simple software RTL simulation will do. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. -The following pages provide detailed information about the simulation possibilities within the REBAR framework. +The following pages provide detailed information about the simulation possibilities within the Chipyard framework. .. toctree:: :maxdepth: 2 diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index 37e0d76e..d73d4072 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -1,7 +1,7 @@ Tools ============================== -The REBAR framework relays heavily on a set of Scala-based tools. +The Chipyard framework relays heavily on a set of Scala-based tools. The following pages will introduce them, and how we can use them in order to generate flexible designs. .. toctree:: diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 448fadd7..464d9828 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -1,7 +1,7 @@ VLSI Production ================================ -The REBAR framework aim to provide wrappers to a general VLSI flow. +The Chipyard framework aim to provide wrappers to a general VLSI flow. In particular, we aim to support the HAMMER flow. .. toctree:: diff --git a/docs/conf.py b/docs/conf.py index 9b7bbe43..200e0c1e 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# REBAR documentation build configuration file, created by +# Chipyard documentation build configuration file, created by # sphinx-quickstart on Fri Mar 8 11:46:38 2019. # # This file is execfile()d with the current directory set to its @@ -52,7 +52,7 @@ source_suffix = '.rst' master_doc = 'index' # General information about the project. -project = u'REBAR' +project = u'Chipyard' copyright = u'2019, Berkeley Architecture Research' author = u'Berkeley Architecture Research' @@ -125,7 +125,7 @@ html_sidebars = { # -- Options for HTMLHelp output ------------------------------------------ # Output file base name for HTML help builder. -htmlhelp_basename = 'REBARdoc' +htmlhelp_basename = 'Chipyarddoc' # -- Options for LaTeX output --------------------------------------------- @@ -152,7 +152,7 @@ latex_elements = { # (source start file, target name, title, # author, documentclass [howto, manual, or own class]). latex_documents = [ - (master_doc, 'REBAR.tex', u'REBAR Documentation', + (master_doc, 'Chipyard.tex', u'Chipyard Documentation', u'Berkeley Architecture Research', 'manual'), ] @@ -162,7 +162,7 @@ latex_documents = [ # One entry per manual page. List of tuples # (source start file, name, description, authors, manual section). man_pages = [ - (master_doc, 'rebar', u'REBAR Documentation', + (master_doc, 'chipyard', u'Chipyard Documentation', [author], 1) ] @@ -173,8 +173,8 @@ man_pages = [ # (source start file, target name, title, author, # dir menu entry, description, category) texinfo_documents = [ - (master_doc, 'REBAR', u'REBAR Documentation', - author, 'REBAR', 'One line description of project.', + (master_doc, 'Chipyard', u'Chipyard Documentation', + author, 'Chipyard', 'One line description of project.', 'Miscellaneous'), ] diff --git a/docs/index.rst b/docs/index.rst index 68598e7a..ce083f2c 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,14 +1,14 @@ -.. REBAR documentation master file, created by +.. Chipyard documentation master file, created by sphinx-quickstart on Fri Mar 8 11:46:38 2019. You can adapt this file completely to your liking, but it should at least contain the root `toctree` directive. -Welcome to REBAR's documentation! +Welcome to Chipyard's documentation! ================================= -REBAR is a a framework for designing and evaluating full-system hardware using agile teams. +Chipyard is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. -New to REBAR? Jump to the :ref:`Getting Started` page for more info. +New to Chipyard? Jump to the :ref:`Getting Started` page for more info. .. toctree:: :maxdepth: 3 diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 9b659109..20ce4800 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -6,7 +6,7 @@ set -o pipefail unamestr=$(uname) RDIR=$(pwd) -: ${REBAR_DIR:=$(pwd)} #default value is the PWD unless overridden +: ${CHIPYARD_DIR:=$(pwd)} #default value is the PWD unless overridden if [ $# -ne 0 ]; then TOOLCHAIN=$1 @@ -26,8 +26,8 @@ RISCV="$(pwd)/$INSTALL_DIR" # install risc-v tools export RISCV="$RISCV" -git -C $REBAR_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 -cd "$REBAR_DIR/toolchains/$TOOLCHAIN" +git -C $CHIPYARD_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 +cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" export MAKEFLAGS="-j16" ./build.sh cd $RDIR diff --git a/scripts/gen-tags.sh b/scripts/gen-tags.sh index 52df9aa7..afc7e228 100755 --- a/scripts/gen-tags.sh +++ b/scripts/gen-tags.sh @@ -1,10 +1,10 @@ #!/usr/bin/env bash -# run this script in the main rebar directory to generate ctags for all relevant repos +# run this script in the main Chipyard directory to generate ctags for all relevant repos # note: this requires exuberant-ctags # tested with: Exuberant Ctags 5.8 # instructions: -# cd /path/to/rebar/ +# cd /path/to/chipyard/ # ./scripts/gen-tags.sh # # input: diff --git a/variables.mk b/variables.mk index 76632f48..601afb03 100644 --- a/variables.mk +++ b/variables.mk @@ -52,7 +52,7 @@ ifeq ($(SUB_PROJECT),boom) endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) - SBT_PROJECT ?= rebarrocketchip + SBT_PROJECT ?= chipyardrocketchip MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= freechips.rocketchip.system @@ -78,9 +78,9 @@ endif ######################################################################################### # path to rocket-chip and testchipip ######################################################################################### -ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip -TESTCHIP_DIR = $(base_dir)/generators/testchipip -REBAR_FIRRTL_DIR = $(base_dir)/tools/firrtl +ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip +TESTCHIP_DIR = $(base_dir)/generators/testchipip +CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl ######################################################################################### # names of various files needed to compile and run things From 5f19697618b7f42e4c0df54bfc9a4030c83b4f01 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 31 May 2019 17:51:05 -0700 Subject: [PATCH 020/160] first attempt at explaining heter systems --- docs/Advanced-Usage/Heterogeneous-SoCs.rst | 127 +++++++++++++++++++++ docs/Advanced-Usage/index.rst | 11 ++ docs/index.rst | 4 + 3 files changed, 142 insertions(+) create mode 100644 docs/Advanced-Usage/Heterogeneous-SoCs.rst create mode 100644 docs/Advanced-Usage/index.rst diff --git a/docs/Advanced-Usage/Heterogeneous-SoCs.rst b/docs/Advanced-Usage/Heterogeneous-SoCs.rst new file mode 100644 index 00000000..2ee9cba4 --- /dev/null +++ b/docs/Advanced-Usage/Heterogeneous-SoCs.rst @@ -0,0 +1,127 @@ +Heterogeneous SoCs +=============================== + +The REBAR framework involves multiple cores and accelerators that can be composed in arbitrary ways. +This discussion will focus on how you combine Rocket, BOOM and Hwacha in particular ways to create a unique SoC. + +Creating a Rocket and BOOM System +------------------------------------------- + +Instantiating an SoC with Rocket and BOOM cores is all done with the configuration system and two specific mixins. +Both BOOM and Rocket have mixins labelled ``WithNBoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core. +When used together you can create a heterogeneous system. +The following example shows a dual core BOOM with a single Rocket. + +.. code-block:: scala + + class DualCoreBoomAndRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.system.WithRenumberHarts ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +In this example, the ``WithN...Cores(X)`` mixins set up particular parameters for the duplicated core. +For example, the Rocket tiles will be "BigCores" while BOOM has some generic parameters set in its mixin. +In BOOMs case, we override these base core parameters to create multiple "DefaultBoom"s with calling ``DefaultBoomConfig`` after the multi-core instantiation. +This mixin applies to all the BOOM cores in the system and sets up the parameters for each. + +Great! Now you have a heterogeneous setup with BOOMs and Rockets. +The final thing you need to make this system work is to renumber the ``hartId``'s of the cores so that each core has a unique ``hartId``. +This is done with ``WithRenumberHarts`` (which can label the Rocket cores first or the BOOM cores first). +The reason this is needed is because by default the ``WithN...Cores(X)`` mixin assumes that there are only that type of core in the system. +Thus, without the renumber mixin, each set of cores is labeled starting from zero. + +Another option to create a multi heterogeneous core system is to override the parameters yourself so you can specify the core parameters per core. +The mixin to add to your system would look something like the following. + +.. code-block:: scala + + // create 6 cores (4 boom and 2 rocket) + class WithHeterCoresSetup extends Config((site, here, up) => { + case BoomTilesKey => { + val boomTile0 = BoomTileParams(...) // params for boom core 0 + val boomTile1 = BoomTileParams(...) // params for boom core 1 + val boomTile2 = BoomTileParams(...) // params for boom core 2 + val boomTile3 = BoomTileParams(...) // params for boom core 3 + boomTile0 ++ boomTile1 ++ boomTile2 ++ boomTile3 + } + + case RocketTilesKey => { + val rocketTile0 = RocketTileParams(...) // params for rocket core 0 + val rocketTile1 = RocketTileParams(...) // params for rocket core 1 + rocketTile0 ++ rocketTile1 + } + }) + +Then you could use this new mixin like the following. + +.. code-block:: scala + + class SixCoreConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new WithHeterCoresSetup ++ + new freechips.rocketchip.system.BaseConfig) + +Note, in this setup you most likely dont need the ``WithRenumberHarts`` mixin since you have to assign the ``hartId`` of each tile in the params yourself. + +Adding Hwachas +------------------------------------------- + +Adding a Hwacha accelerator is as easy as adding the ``DefaultHwachaConfig`` so that it can setup the Hwacha parameters and add itself to the ``BuildRoCC`` parameter. +An example of adding a Hwacha to all tiles in the system is below. + +.. code-block:: scala + + class DualCoreBoomAndRocketWithHwachasConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new hwacha.DefaultHwachaConfig ++ + new boom.system.WithRenumberHarts ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +In this example, Hwachas are added to both BOOM's and to the Rocket tile. +All with the same Hwacha parameters. + +Assigning Accelerators to Specific Tiles with MultiRoCC +------------------------------------------------------- + +Located in ``generators/example/src/main/scala/ConfigMixins.scala`` is a Mixin that provides support for adding RoCC accelerators to specific tiles in your SoC. +Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile. +For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles. +An example is shown below with two BOOM cores, and one Rocket attached to a Hwacha. + +.. code-block:: scala + + class DualCoreBoomAndOneHwachaRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new WithMultiRoCC ++ + new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket + new boom.system.WithRenumberHarts ++ + new hwacha.DefaultHwachaConfig ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +In this example, the ``WithRenumberHarts`` relabels the ``hartId``'s of all the BOOM/Rocket cores. +Then after that is applied to the parameters, the ``WithMultiRoCCHwacha(0)`` is used to assign to ``hartId`` zero a Hwacha (in this case ``hartId`` zero is Rocket). +Finally, the ``WithMultiRoCC`` mixin is called. +This mixin sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default. +This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter. +If this is used earlier in the configuration sequence, then MultiRoCC does not work. + +This mixin can be changed to put more accelerators on more cores by changing the arguments to cover more ``hartId``'s (i.e. ``WithMultiRoCCHwacha(0,1,3,6,...)``). diff --git a/docs/Advanced-Usage/index.rst b/docs/Advanced-Usage/index.rst new file mode 100644 index 00000000..6aa2a195 --- /dev/null +++ b/docs/Advanced-Usage/index.rst @@ -0,0 +1,11 @@ +Advanced Usage +================================ + +The following sections are advanced topics about how to use REBAR and special features of the framework. +They expect you to know about Chisel, Parameters, Configs, etc. + +.. toctree:: + :maxdepth: 2 + :caption: Getting Started: + + Heterogeneous-SoCs diff --git a/docs/index.rst b/docs/index.rst index ce083f2c..019a6991 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -37,6 +37,10 @@ New to Chipyard? Jump to the :ref:`Getting Started` page for more info. :numbered: VLSI/index + :maxdepth: 3 + :caption: Advanced Usage: + :numbered: + Advanced-Usage/index Indices and tables ================== From c61713d807c07d6435210e6a636f2a1cd9851c39 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Jun 2019 11:52:00 -0700 Subject: [PATCH 021/160] removed extra core in names | misc cleanup --- docs/Advanced-Usage/Heterogeneous-SoCs.rst | 24 +++++++++---------- docs/Advanced-Usage/index.rst | 2 +- .../example/src/main/scala/Configs.scala | 6 ++--- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/docs/Advanced-Usage/Heterogeneous-SoCs.rst b/docs/Advanced-Usage/Heterogeneous-SoCs.rst index 2ee9cba4..596ba59b 100644 --- a/docs/Advanced-Usage/Heterogeneous-SoCs.rst +++ b/docs/Advanced-Usage/Heterogeneous-SoCs.rst @@ -1,7 +1,7 @@ Heterogeneous SoCs =============================== -The REBAR framework involves multiple cores and accelerators that can be composed in arbitrary ways. +The Chipyard framework involves multiple cores and accelerators that can be composed in arbitrary ways. This discussion will focus on how you combine Rocket, BOOM and Hwacha in particular ways to create a unique SoC. Creating a Rocket and BOOM System @@ -10,11 +10,11 @@ Creating a Rocket and BOOM System Instantiating an SoC with Rocket and BOOM cores is all done with the configuration system and two specific mixins. Both BOOM and Rocket have mixins labelled ``WithNBoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core. When used together you can create a heterogeneous system. -The following example shows a dual core BOOM with a single Rocket. +The following example shows a dual core BOOM with a single core Rocket. .. code-block:: scala - class DualCoreBoomAndRocketConfig extends Config( + class DualBoomAndOneRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.WithRenumberHarts ++ @@ -33,8 +33,8 @@ This mixin applies to all the BOOM cores in the system and sets up the parameter Great! Now you have a heterogeneous setup with BOOMs and Rockets. The final thing you need to make this system work is to renumber the ``hartId``'s of the cores so that each core has a unique ``hartId``. This is done with ``WithRenumberHarts`` (which can label the Rocket cores first or the BOOM cores first). -The reason this is needed is because by default the ``WithN...Cores(X)`` mixin assumes that there are only that type of core in the system. -Thus, without the renumber mixin, each set of cores is labeled starting from zero. +The reason this is needed is because by default the ``WithN...Cores(X)`` mixin assumes that there are only BOOM or only Rocket cores in the system. +Thus, without the ``WithRenumberHarts`` mixin, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``. Another option to create a multi heterogeneous core system is to override the parameters yourself so you can specify the core parameters per core. The mixin to add to your system would look something like the following. @@ -68,7 +68,7 @@ Then you could use this new mixin like the following. new WithHeterCoresSetup ++ new freechips.rocketchip.system.BaseConfig) -Note, in this setup you most likely dont need the ``WithRenumberHarts`` mixin since you have to assign the ``hartId`` of each tile in the params yourself. +Note, in this setup you most likely don't need the ``WithRenumberHarts`` mixin since you have to assign the ``hartId`` of each tile in the tile parameters yourself. Adding Hwachas ------------------------------------------- @@ -78,7 +78,7 @@ An example of adding a Hwacha to all tiles in the system is below. .. code-block:: scala - class DualCoreBoomAndRocketWithHwachasConfig extends Config( + class DualBoomAndRocketWithHwachasConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ new hwacha.DefaultHwachaConfig ++ @@ -90,25 +90,25 @@ An example of adding a Hwacha to all tiles in the system is below. new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) -In this example, Hwachas are added to both BOOM's and to the Rocket tile. +In this example, Hwachas are added to both BOOM tiles and to the Rocket tile. All with the same Hwacha parameters. Assigning Accelerators to Specific Tiles with MultiRoCC ------------------------------------------------------- -Located in ``generators/example/src/main/scala/ConfigMixins.scala`` is a Mixin that provides support for adding RoCC accelerators to specific tiles in your SoC. +Located in ``generators/example/src/main/scala/ConfigMixins.scala`` is a mixin that provides support for adding RoCC accelerators to specific tiles in your SoC. Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile. For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles. -An example is shown below with two BOOM cores, and one Rocket attached to a Hwacha. +An example is shown below with two BOOM cores, and one Rocket tile with a Hwacha attached. .. code-block:: scala - class DualCoreBoomAndOneHwachaRocketConfig extends Config( + class DualBoomAndOneHwachaRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ new WithMultiRoCC ++ new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket - new boom.system.WithRenumberHarts ++ + new boom.system.WithRenumberHarts(rocketFirst = true) ++ new hwacha.DefaultHwachaConfig ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ diff --git a/docs/Advanced-Usage/index.rst b/docs/Advanced-Usage/index.rst index 6aa2a195..62dd11aa 100644 --- a/docs/Advanced-Usage/index.rst +++ b/docs/Advanced-Usage/index.rst @@ -1,7 +1,7 @@ Advanced Usage ================================ -The following sections are advanced topics about how to use REBAR and special features of the framework. +The following sections are advanced topics about how to use Chipyard and special features of the framework. They expect you to know about Chisel, Parameters, Configs, etc. .. toctree:: diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index d6ff3432..4b5352d3 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -205,7 +205,7 @@ class GPIOBoomAndRocketConfig extends Config( new WithGPIOBoomRocketTop ++ new BaseBoomAndRocketConfig) -class DualCoreBoomAndOneRocketConfig extends Config( +class DualBoomAndOneRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.WithRenumberHarts ++ @@ -216,12 +216,12 @@ class DualCoreBoomAndOneRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) -class DualCoreBoomAndOneHwachaRocketConfig extends Config( +class DualBoomAndOneHwachaRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ new WithMultiRoCC ++ new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket - new boom.system.WithRenumberHarts ++ + new boom.system.WithRenumberHarts(rocketFirst = true) ++ new hwacha.DefaultHwachaConfig ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ From b3eeb70045ce08f4d5582cc1feeb5cfcb0cff0bf Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 23 Jun 2019 22:58:34 -0700 Subject: [PATCH 022/160] clarifications --- docs/Advanced-Usage/Heterogeneous-SoCs.rst | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/docs/Advanced-Usage/Heterogeneous-SoCs.rst b/docs/Advanced-Usage/Heterogeneous-SoCs.rst index 596ba59b..1ac91633 100644 --- a/docs/Advanced-Usage/Heterogeneous-SoCs.rst +++ b/docs/Advanced-Usage/Heterogeneous-SoCs.rst @@ -25,13 +25,12 @@ The following example shows a dual core BOOM with a single core Rocket. new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) -In this example, the ``WithN...Cores(X)`` mixins set up particular parameters for the duplicated core. -For example, the Rocket tiles will be "BigCores" while BOOM has some generic parameters set in its mixin. -In BOOMs case, we override these base core parameters to create multiple "DefaultBoom"s with calling ``DefaultBoomConfig`` after the multi-core instantiation. -This mixin applies to all the BOOM cores in the system and sets up the parameters for each. +In this example, the ``WithNBoomCores`` and ``WithNBigCores`` mixins set up the default parameters for the multiple BOOM and Rocket cores, respectively. +However, for BOOM, an extra mixin called ``DefaultBoomConfig`` is added to override the default parameters with a "normal" sized out-of-order core. +This mixin applies to all BOOM cores in the system and changes the parameters for each. Great! Now you have a heterogeneous setup with BOOMs and Rockets. -The final thing you need to make this system work is to renumber the ``hartId``'s of the cores so that each core has a unique ``hartId``. +The final thing you need to make this system work is to renumber the ``hartId``'s of the cores so that each core has a unique ``hartId`` (a ``hartId`` is the hardware thread id of the core). This is done with ``WithRenumberHarts`` (which can label the Rocket cores first or the BOOM cores first). The reason this is needed is because by default the ``WithN...Cores(X)`` mixin assumes that there are only BOOM or only Rocket cores in the system. Thus, without the ``WithRenumberHarts`` mixin, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``. @@ -68,7 +67,7 @@ Then you could use this new mixin like the following. new WithHeterCoresSetup ++ new freechips.rocketchip.system.BaseConfig) -Note, in this setup you most likely don't need the ``WithRenumberHarts`` mixin since you have to assign the ``hartId`` of each tile in the tile parameters yourself. +Note, in this setup you need to specify the ``hartId`` of each core in the "TileParams", where each ``hartId`` is unique. Adding Hwachas ------------------------------------------- From 9fc0b9393cd040a0a2a7c8fb65fa32850c56a3ef Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 24 Jun 2019 14:32:49 -0700 Subject: [PATCH 023/160] more clarity on defaults --- docs/Advanced-Usage/Heterogeneous-SoCs.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Advanced-Usage/Heterogeneous-SoCs.rst b/docs/Advanced-Usage/Heterogeneous-SoCs.rst index 1ac91633..4afb6f20 100644 --- a/docs/Advanced-Usage/Heterogeneous-SoCs.rst +++ b/docs/Advanced-Usage/Heterogeneous-SoCs.rst @@ -26,7 +26,7 @@ The following example shows a dual core BOOM with a single core Rocket. new freechips.rocketchip.system.BaseConfig) In this example, the ``WithNBoomCores`` and ``WithNBigCores`` mixins set up the default parameters for the multiple BOOM and Rocket cores, respectively. -However, for BOOM, an extra mixin called ``DefaultBoomConfig`` is added to override the default parameters with a "normal" sized out-of-order core. +However, for BOOM, an extra mixin called ``DefaultBoomConfig`` is added to override the default parameters with a different set of more common default parameters. This mixin applies to all BOOM cores in the system and changes the parameters for each. Great! Now you have a heterogeneous setup with BOOMs and Rockets. From 73dc1dfe6fdcb0412ae5000ae02c5db12c1ab1c8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 25 Jun 2019 07:59:35 -0700 Subject: [PATCH 024/160] bump rocket and testchipip --- generators/rocket-chip | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index b8baef6f..50de8a34 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit b8baef6f26fa36c9b4e0b2a5eec12cd76ae5daf8 +Subproject commit 50de8a34c19c12de5066cd7ada50ebb5f5b2ea26 diff --git a/generators/testchipip b/generators/testchipip index cd176871..855a4dd4 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit cd1768712ead82d1a76278b65b7f6ea41ae82dc9 +Subproject commit 855a4dd4822cee1693fe1e0bf7d0727f074ceae5 From 44b1412c5e840330c92d1a98e5f98c87c3070465 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 25 Jun 2019 09:22:06 -0700 Subject: [PATCH 025/160] clarify hwacha=rocc | alternative clarification --- docs/Advanced-Usage/Heterogeneous-SoCs.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Advanced-Usage/Heterogeneous-SoCs.rst b/docs/Advanced-Usage/Heterogeneous-SoCs.rst index 4afb6f20..96a7e40e 100644 --- a/docs/Advanced-Usage/Heterogeneous-SoCs.rst +++ b/docs/Advanced-Usage/Heterogeneous-SoCs.rst @@ -35,7 +35,7 @@ This is done with ``WithRenumberHarts`` (which can label the Rocket cores first The reason this is needed is because by default the ``WithN...Cores(X)`` mixin assumes that there are only BOOM or only Rocket cores in the system. Thus, without the ``WithRenumberHarts`` mixin, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``. -Another option to create a multi heterogeneous core system is to override the parameters yourself so you can specify the core parameters per core. +Another alternative option to create a multi heterogeneous core system is to override the parameters yourself so you can specify the core parameters per core. The mixin to add to your system would look something like the following. .. code-block:: scala @@ -98,7 +98,7 @@ Assigning Accelerators to Specific Tiles with MultiRoCC Located in ``generators/example/src/main/scala/ConfigMixins.scala`` is a mixin that provides support for adding RoCC accelerators to specific tiles in your SoC. Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile. For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles. -An example is shown below with two BOOM cores, and one Rocket tile with a Hwacha attached. +An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached. .. code-block:: scala From bc6686a063ce3162e3c076bf1dd9660b783bfea7 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 28 Jun 2019 17:57:12 +0000 Subject: [PATCH 026/160] [FireChip] Fix BootROM path handling --- generators/firechip/src/main/scala/TargetConfigs.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 6e20364d..9be95d89 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -16,11 +16,11 @@ import icenet._ class WithBootROM extends Config((site, here, up) => { case BootROMParams => { - val rebarBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") - val firesimBootROM = new File(s"./target-rtl/firechip/generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") + val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") + val firesimBootROM = new File(s"./target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") - val bootROMPath = if (rebarBootROM.exists()) { - rebarBootROM.getAbsolutePath() + val bootROMPath = if (chipyardBootROM.exists()) { + chipyardBootROM.getAbsolutePath() } else { firesimBootROM.getAbsolutePath() } From dc9cef30ae1a043490ab9e6ffada693f924ce308 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 28 Jun 2019 11:07:41 -0700 Subject: [PATCH 027/160] bump rc/firrtl | bump to temp boom/testchipip --- generators/boom | 2 +- generators/rocket-chip | 2 +- generators/testchipip | 2 +- tools/firrtl | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/boom b/generators/boom index 22c5f9ec..4688b7e8 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 22c5f9ec3f0325b9bdbf1a98b5752b6ac843eb19 +Subproject commit 4688b7e8441244ac3425ee69d59d66c1931002ca diff --git a/generators/rocket-chip b/generators/rocket-chip index b8baef6f..50de8a34 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit b8baef6f26fa36c9b4e0b2a5eec12cd76ae5daf8 +Subproject commit 50de8a34c19c12de5066cd7ada50ebb5f5b2ea26 diff --git a/generators/testchipip b/generators/testchipip index cd176871..532d4a42 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit cd1768712ead82d1a76278b65b7f6ea41ae82dc9 +Subproject commit 532d4a42914286548179f3893ab6349a0aedb5e3 diff --git a/tools/firrtl b/tools/firrtl index 99ae1d66..228c9a4b 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit 99ae1d6649f1731c5dec2098b10733735232b72c +Subproject commit 228c9a4b7432ac52178d63b8f27fe064aec71e9c From 0faadb75d6cb7834b55f4eb091c80eedd89c6c8e Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 28 Jun 2019 18:49:03 +0000 Subject: [PATCH 028/160] [FireChip] Update BOOM based targets to use new SubSystem --- generators/firechip/src/main/scala/Generator.scala | 0 generators/firechip/src/main/scala/TargetMixins.scala | 1 - generators/firechip/src/main/scala/Targets.scala | 10 +++++----- 3 files changed, 5 insertions(+), 6 deletions(-) mode change 100755 => 100644 generators/firechip/src/main/scala/Generator.scala mode change 100755 => 100644 generators/firechip/src/main/scala/Targets.scala diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala old mode 100755 new mode 100644 diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 1c38ce2e..5544376f 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -10,7 +10,6 @@ import freechips.rocketchip.util._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.TracedInstruction import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} -import boom.system.BoomSubsystem import midas.models.AXI4BundleWithEdge import midas.targetutils.ExcludeInstanceAsserts diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala old mode 100755 new mode 100644 index 3a565c65..c9077044 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.amba.axi4.AXI4Bundle import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.LazyModule -import boom.system.{BoomSubsystem, BoomSubsystemModuleImp} +import boom.system.{BoomRocketSubsystem, BoomRocketSubsystemModuleImp} import icenet._ import testchipip._ import testchipip.SerialAdapter.SERIAL_IF_WIDTH @@ -80,7 +80,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod with HasTraceIOImp -class FireBoom(implicit p: Parameters) extends BoomSubsystem +class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -94,7 +94,7 @@ class FireBoom(implicit p: Parameters) extends BoomSubsystem override lazy val module = new FireBoomModuleImp(this) } -class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomSubsystemModuleImp(l) +class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -106,7 +106,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomSubsystemModuleImp(l) with HasTraceIOImp with ExcludeInvalidBoomAssertions -class FireBoomNoNIC(implicit p: Parameters) extends BoomSubsystem +class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -119,7 +119,7 @@ class FireBoomNoNIC(implicit p: Parameters) extends BoomSubsystem override lazy val module = new FireBoomNoNICModuleImp(this) } -class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomSubsystemModuleImp(l) +class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp From f65d5d57d63e0b7c26ed6c6802b4df695b4e1a0f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 28 Jun 2019 19:01:44 +0000 Subject: [PATCH 029/160] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index ddad6761..f26ea913 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ddad676138290c6d5e72881ec91815d5447b030b +Subproject commit f26ea913a08e2ae43f4ed11a3796030706179f4a From 1f48e33be546b44c33b9d706562077dcd0a35f22 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 28 Jun 2019 19:16:34 +0000 Subject: [PATCH 030/160] Bump FireSim, and add back the firrtl intrp lib dep --- build.sbt | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 1e283547..f2fa105c 100644 --- a/build.sbt +++ b/build.sbt @@ -13,7 +13,7 @@ lazy val commonSettings = Seq( libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.5" % "test", libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1", libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value, - //libraryDependencies += "edu.berkeley.cs" %% "firrtl-interpreter" % "1.2-SNAPSHOT", + libraryDependencies += "edu.berkeley.cs" %% "firrtl-interpreter" % "1.2-SNAPSHOT", libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), resolvers ++= Seq( diff --git a/sims/firesim b/sims/firesim index f26ea913..65be3cae 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f26ea913a08e2ae43f4ed11a3796030706179f4a +Subproject commit 65be3cae99022375fb2babbc242cc433d5671b86 From 473bc0aa4e8710bc5d9ecd758acb2b5c94bb4500 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 28 Jun 2019 23:53:58 +0000 Subject: [PATCH 031/160] Comment out FireChip make variables for now --- sims/firesim | 2 +- variables.mk | 25 +++++++++++++------------ 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/sims/firesim b/sims/firesim index 65be3cae..7f8152e5 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 65be3cae99022375fb2babbc242cc433d5671b86 +Subproject commit 7f8152e5114c7f7793df54a41a53a9e6a04fa8cd diff --git a/variables.mk b/variables.mk index 91060aed..da3a9a6e 100644 --- a/variables.mk +++ b/variables.mk @@ -74,18 +74,19 @@ ifeq ($(SUB_PROJECT),hwacha) TB ?= TestDriver TOP ?= ExampleRocketSystem endif -# Stand-in firechip variables -ifeq ($(SUB_PROJECT),firechip) - SBT_PROJECT ?= $(SUB_PROJECT) - MODEL ?= TestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= freechips.rocketchip.system - CONFIG ?= FireSimRocketChipConfig - CONFIG_PACKAGE ?= firesim.firesim - GENERATOR_PACKAGE ?= firesim.firesim - TB ?= TestDriver - TOP ?= FireSimNoNIC -endif +# Stand-in firechip variables: +# TODO: need a seperate generator and test harnesses for each target +#ifeq ($(SUB_PROJECT),firechip) +# SBT_PROJECT ?= $(SUB_PROJECT) +# MODEL ?= TestHarness +# VLOG_MODEL ?= TestHarness +# MODEL_PACKAGE ?= freechips.rocketchip.system +# CONFIG ?= FireSimRocketChipConfig +# CONFIG_PACKAGE ?= firesim.firesim +# GENERATOR_PACKAGE ?= firesim.firesim +# TB ?= TestDriver +# TOP ?= FireSimNoNIC +#endif ######################################################################################### # path to rocket-chip and testchipip From 424f5aead121173474cdccfd1b988afda2542e42 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 1 Jul 2019 11:28:21 -0700 Subject: [PATCH 032/160] bump boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 4688b7e8..577eee7f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 4688b7e8441244ac3425ee69d59d66c1931002ca +Subproject commit 577eee7f0ef01bb79180e6dccde2862855e9d39c From 9db6535370f699f42507ced77068b669b59614f3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 1 Jul 2019 11:42:30 -0700 Subject: [PATCH 033/160] updated boom configs in example --- .../example/src/main/scala/Configs.scala | 25 +++++++++++-------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 4b5352d3..cd81f894 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -68,7 +68,7 @@ class GB1MemoryConfig extends Config( class BaseBoomConfig extends Config( new WithBootROM ++ - new boom.system.BoomConfig) + new boom.system.LargeBoomConfig) class SmallBaseBoomConfig extends Config( new WithBootROM ++ @@ -121,7 +121,8 @@ class DualCoreBoomConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ - new boom.common.DefaultBoomConfig ++ + new boom.common.WithLargeBooms ++ + new boom.common.BaseBoomConfig ++ new boom.system.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) @@ -131,7 +132,7 @@ class DualCoreSmallBoomConfig extends Config( new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ - new boom.common.DefaultBoomConfig ++ + new boom.common.BaseBoomConfig ++ new boom.system.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) @@ -149,7 +150,8 @@ class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ - new boom.common.DefaultBoomConfig ++ + new boom.common.WithLargeBooms ++ + new boom.common.BaseBoomConfig ++ new boom.system.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ @@ -160,7 +162,7 @@ class SmallBaseBoomAndRocketConfig extends Config( new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ - new boom.common.DefaultBoomConfig ++ + new boom.common.BaseBoomConfig ++ new boom.system.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ @@ -205,12 +207,13 @@ class GPIOBoomAndRocketConfig extends Config( new WithGPIOBoomRocketTop ++ new BaseBoomAndRocketConfig) -class DualBoomAndOneRocketConfig extends Config( +class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ - new boom.common.DefaultBoomConfig ++ + new boom.common.WithLargeBooms ++ + new boom.common.BaseBoomConfig ++ new boom.system.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ @@ -224,7 +227,8 @@ class DualBoomAndOneHwachaRocketConfig extends Config( new boom.system.WithRenumberHarts(rocketFirst = true) ++ new hwacha.DefaultHwachaConfig ++ new boom.common.WithRVC ++ - new boom.common.DefaultBoomConfig ++ + new boom.common.WithLargeBooms ++ + new boom.common.BaseBoomConfig ++ new boom.system.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ @@ -236,9 +240,10 @@ class RV32BoomAndRocketConfig extends Config( new boom.system.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ new boom.common.WithRVC ++ - new boom.common.DefaultBoomConfig ++ + new boom.common.WithLargeBooms ++ + new boom.common.BaseBoomConfig ++ new boom.system.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new WithRV32 ++ + new freechips.rocketchip.subsystem.WithRV32 ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) From c44b6b721fe161c41cf039e1a59467f4e8bb5c0a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 1 Jul 2019 11:57:29 -0700 Subject: [PATCH 034/160] fix variables for new boom naming --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index da3a9a6e..d9ce7781 100644 --- a/variables.mk +++ b/variables.mk @@ -44,7 +44,7 @@ ifeq ($(SUB_PROJECT),boom) MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= boom.system - CONFIG ?= BoomConfig + CONFIG ?= LargeBoomConfig CONFIG_PACKAGE ?= boom.system GENERATOR_PACKAGE ?= boom.system TB ?= TestDriver From 65df55cf9d4b920d3897f2c4fe9e11ab5daa4e2e Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 2 Jul 2019 15:29:01 -0700 Subject: [PATCH 035/160] add InclusiveCache --- .gitmodules | 3 +++ build.sbt | 9 +++++++-- common.mk | 2 +- generators/example/src/main/scala/Configs.scala | 11 ++++++++++- generators/sifive-cache | 1 + 5 files changed, 22 insertions(+), 4 deletions(-) create mode 160000 generators/sifive-cache diff --git a/.gitmodules b/.gitmodules index 03010358..ca80d661 100644 --- a/.gitmodules +++ b/.gitmodules @@ -37,3 +37,6 @@ [submodule "generators/icenet"] path = generators/icenet url = https://github.com/firesim/icenet.git +[submodule "generators/block-inclusivecache-sifive"] + path = generators/sifive-cache + url = https://github.com/sifive/block-inclusivecache-sifive.git diff --git a/build.sbt b/build.sbt index f2fa105c..cb3a0b69 100644 --- a/build.sbt +++ b/build.sbt @@ -81,7 +81,7 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val example = conditionalDependsOn(project in file("generators/example")) - .dependsOn(boom, hwacha, sifive_blocks) + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache) .settings(commonSettings) lazy val utilities = conditionalDependsOn(project in file("generators/utilities")) @@ -114,12 +114,17 @@ lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) .settings(commonSettings) +lazy val sifive_cache = (project in file("generators/sifive-cache")).settings( + commonSettings, + scalaSource in Compile := baseDirectory.value / "craft" + ).dependsOn(rocketchip) + // Library components of FireSim lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, icenet, testchipip, sifive_blocks, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/common.mk b/common.mk index a8160248..310da07c 100644 --- a/common.mk +++ b/common.mk @@ -8,7 +8,7 @@ SHELL=/bin/bash ######################################################################################### lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null) -PACKAGES=$(addprefix generators/, rocket-chip testchipip boom hwacha sifive-blocks example) \ +PACKAGES=$(addprefix generators/, rocket-chip testchipip boom hwacha sifive-blocks sifive-cache example) \ $(addprefix sims/firesim/sim/, . firesim-lib midas midas/targetutils) SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index cd81f894..6ac2f064 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -3,7 +3,7 @@ package example import chisel3._ import freechips.rocketchip.config.{Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks, WithInclusiveCache} import testchipip._ @@ -247,3 +247,12 @@ class RV32BoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithRV32 ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) + +class RocketL2Config extends Config( + new WithInclusiveCache ++ new DefaultRocketConfig) + +class BoomL2Config extends Config( + new WithInclusiveCache ++ new SmallDefaultBoomConfig) + +class DualCoreRocketL2Config extends Config( + new WithInclusiveCache ++ new DualCoreRocketConfig) diff --git a/generators/sifive-cache b/generators/sifive-cache new file mode 160000 index 00000000..13d0c2f1 --- /dev/null +++ b/generators/sifive-cache @@ -0,0 +1 @@ +Subproject commit 13d0c2f17853a658ae86eae793718c71ac82dddf From 9031a98514f473e9a2de41b07736c04a9d300399 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 2 Jul 2019 14:54:07 -0700 Subject: [PATCH 036/160] don't need to make copy of HTIF args in emulator --- .../utilities/src/main/resources/csrc/emulator.cc | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 1a4f4dd2..b4f2e093 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -121,7 +121,6 @@ int main(int argc, char** argv) FILE * vcdfile = NULL; uint64_t start = 0; #endif - char ** htif_argv = NULL; int verilog_plusargs_legal = 1; while (1) { @@ -243,10 +242,6 @@ done_processing: usage(argv[0]); return 1; } - int htif_argc = 1 + argc - optind; - htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); - htif_argv[0] = argv[0]; - for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -269,8 +264,8 @@ done_processing: #endif jtag = new remote_bitbang_t(rbb_port); - dtm = new dtm_t(htif_argc, htif_argv); - tsi = new tsi_t(htif_argc, htif_argv); + dtm = new dtm_t(argc, argv); + tsi = new tsi_t(argc, argv); signal(SIGTERM, handle_sigterm); @@ -351,6 +346,5 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; - if (htif_argv) free(htif_argv); return ret; } From 0088a6a8e8452a6689fba37bd268bce29d0a3dd7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 2 Jul 2019 17:30:46 -0700 Subject: [PATCH 037/160] revert firrtl --- tools/firrtl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/firrtl b/tools/firrtl index 228c9a4b..99ae1d66 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit 228c9a4b7432ac52178d63b8f27fe064aec71e9c +Subproject commit 99ae1d6649f1731c5dec2098b10733735232b72c From 1232b374161f701f07e8f008fcff82b50d07d90b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 2 Jul 2019 18:03:23 -0700 Subject: [PATCH 038/160] have configs reside by the proper areas --- generators/example/src/main/scala/Configs.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 6ac2f064..c2334ca8 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -62,6 +62,9 @@ class GB1MemoryConfig extends Config( new WithExtMemSize((1<<30) * 1L) ++ new DefaultRocketConfig) +class RocketL2Config extends Config( + new WithInclusiveCache ++ new DefaultRocketConfig) + // ------------ // BOOM Configs // ------------ @@ -142,6 +145,9 @@ class RV32UnifiedBoomConfig extends Config( new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) +class BoomL2Config extends Config( + new WithInclusiveCache ++ new SmallDefaultBoomConfig) + // --------------------- // BOOM and Rocket Configs // --------------------- @@ -248,11 +254,5 @@ class RV32BoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) -class RocketL2Config extends Config( - new WithInclusiveCache ++ new DefaultRocketConfig) - -class BoomL2Config extends Config( - new WithInclusiveCache ++ new SmallDefaultBoomConfig) - class DualCoreRocketL2Config extends Config( new WithInclusiveCache ++ new DualCoreRocketConfig) From e2621a875799190d071b9c283c738e05dc3da175 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 4 Jul 2019 12:47:10 -0700 Subject: [PATCH 039/160] Bump boom for fetch buffer fixes --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 577eee7f..80a68074 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 577eee7f0ef01bb79180e6dccde2862855e9d39c +Subproject commit 80a680745c27dfe54bdd217e8de9c24c1c96b553 From ef1620b753ca1d24d71c0187116e995f39ad406c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 6 Jul 2019 15:13:37 -0700 Subject: [PATCH 040/160] update verilator.mk to support different install location --- sims/verisim/verilator.mk | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/sims/verisim/verilator.mk b/sims/verisim/verilator.mk index 4edfa6e3..80abd869 100644 --- a/sims/verisim/verilator.mk +++ b/sims/verisim/verilator.mk @@ -5,9 +5,10 @@ ######################################################################################### # verilator version, binary, and path ######################################################################################### -VERILATOR_VERSION=4.016 -VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) -INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) +VERILATOR_VERSION = 4.016 +VERILATOR_INSTALL_DIR ?= verilator +VERILATOR_SRCDIR = $(VERILATOR_INSTALL_DIR)/src/verilator-$(VERILATOR_VERSION) +INSTALLED_VERILATOR = $(abspath $(VERILATOR_INSTALL_DIR)/install/bin/verilator) ######################################################################################### # build and install our own verilator to work around versioning issues @@ -25,15 +26,15 @@ $(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile $(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure mkdir -p $(dir $@) - cd $(dir $@) && ./configure --prefix=$(abspath verilator/install) + cd $(dir $@) && ./configure --prefix=$(abspath $(VERILATOR_INSTALL_DIR)/install) -$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz +$(VERILATOR_SRCDIR)/configure: $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz rm -rf $(dir $@) mkdir -p $(dir $@) cat $^ | tar -xz --strip-components=1 -C $(dir $@) touch $@ -verilator/verilator-$(VERILATOR_VERSION).tar.gz: +$(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz: mkdir -p $(dir $@) wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ From 87e4090e3861251d02322fca63648153f5ed2619 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 8 Jul 2019 14:31:41 -0700 Subject: [PATCH 041/160] bump boom | correct error on first cmd in pipe --- common.mk | 4 ++-- generators/boom | 2 +- sims/verisim/Makefile | 2 +- sims/vsim/Makefile | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/common.mk b/common.mk index 310da07c..1b0d139d 100644 --- a/common.mk +++ b/common.mk @@ -76,7 +76,7 @@ verilog: $(sim_vsrcs) # helper rules to run simulator ######################################################################################### run-binary: $(sim) - $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) ######################################################################################### # run assembly/benchmarks rules @@ -89,7 +89,7 @@ $(output_dir)/%.run: $(output_dir)/% $(sim) $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@) ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/generators/boom b/generators/boom index 80a68074..84879571 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 80a680745c27dfe54bdd217e8de9c24c1c96b553 +Subproject commit 848795715f721b6a88887283179176474a1496b8 diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 655d67cc..629373c8 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -84,7 +84,7 @@ $(sim_debug): $(model_mk_debug) # helper rules to run simulator with debug ######################################################################################### run-binary-debug: $(sim_debug) - $(sim_debug) $(SIM_FLAGS) -v$(sim_out_name).vcd $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out + (set -o pipefail && $(sim_debug) $(SIM_FLAGS) -v$(sim_out_name).vcd $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) ######################################################################################### # create a verisim vpd rule diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index d34fb5eb..f5882757 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -90,7 +90,7 @@ $(sim_debug) : $(sim_vsrcs) $(sim_dotf) # helper rules to run simulator with debug ######################################################################################### run-binary-debug: $(sim_debug) - $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) ######################################################################################### # create a vcs vpd rule From a408422ac18d7062cc0a2f3bb265eff6e63eab6d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 8 Jul 2019 14:34:17 -0700 Subject: [PATCH 042/160] reverse @zhemao commit on htif: need to parse args for verilator --- .../utilities/src/main/resources/csrc/emulator.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index b4f2e093..1a4f4dd2 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -121,6 +121,7 @@ int main(int argc, char** argv) FILE * vcdfile = NULL; uint64_t start = 0; #endif + char ** htif_argv = NULL; int verilog_plusargs_legal = 1; while (1) { @@ -242,6 +243,10 @@ done_processing: usage(argv[0]); return 1; } + int htif_argc = 1 + argc - optind; + htif_argv = (char **) malloc((htif_argc) * sizeof (char *)); + htif_argv[0] = argv[0]; + for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++]; if (verbose) fprintf(stderr, "using random seed %u\n", random_seed); @@ -264,8 +269,8 @@ done_processing: #endif jtag = new remote_bitbang_t(rbb_port); - dtm = new dtm_t(argc, argv); - tsi = new tsi_t(argc, argv); + dtm = new dtm_t(htif_argc, htif_argv); + tsi = new tsi_t(htif_argc, htif_argv); signal(SIGTERM, handle_sigterm); @@ -346,5 +351,6 @@ done_processing: if (tsi) delete tsi; if (jtag) delete jtag; if (tile) delete tile; + if (htif_argv) free(htif_argv); return ret; } From ba102fab4ab5d7074976491bb97b47d268e73863 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 8 Jul 2019 15:04:21 -0700 Subject: [PATCH 043/160] Allow esp-tools to get updated after init script --- scripts/init-submodules-no-riscv-tools.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 27005cbb..ed6182d4 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -16,4 +16,5 @@ git config --global submodule.experimental-blocks.update none git submodule update --init --recursive #--jobs 8 # unignore riscv-tools,catapult-shell2 globally git config --global --unset submodule.riscv-tools.update +git config --global --unset submodule.esp-tools.update git config --global --unset submodule.experimental-blocks.update From 00d59bd25d0202548720f742209dd2ba28c827be Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 Jul 2019 16:03:25 -0700 Subject: [PATCH 044/160] use remote build server --- .circleci/build-toolchains.sh | 3 +- .circleci/build-verilator.sh | 26 +++- .circleci/config.yml | 224 ++++++++++------------------------ .circleci/defaults.sh | 28 +++++ .circleci/do-rtl-build.sh | 35 ++++-- 5 files changed, 141 insertions(+), 175 deletions(-) create mode 100755 .circleci/defaults.sh diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index 9b5477f6..6965da30 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -7,8 +7,7 @@ set -ex if [ ! -d "$HOME/$1-install" ]; then - - cd $HOME/ + cd $HOME # init all submodules including the tools CHIPYARD_DIR=$HOME/project ./project/scripts/build-toolchains.sh $1 diff --git a/.circleci/build-verilator.sh b/.circleci/build-verilator.sh index 00cd7217..5a837e1f 100755 --- a/.circleci/build-verilator.sh +++ b/.circleci/build-verilator.sh @@ -5,11 +5,27 @@ # turn echo on and error on earliest command set -ex -cd $HOME/project +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh -cd sims/verisim +# call clean on exit +trap clean EXIT -if [ ! -d "$HOME/project/sims/verisim/verilator" ]; then - # make verilator - make verilator_install +if [ ! -d "$LOCAL_VERILATOR_DIR" ]; then + # set stricthostkeychecking to no (must happen before rsync) + run "echo \"Ping $SERVER\"" + + clean + + run "mkdir -p $REMOTE_CHIPYARD_DIR" + copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR + + run "make -C $REMOTE_CHIPYARD_DIR/sims/verisim VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR verilator_install" + + # copy so that circleci can cache + mkdir -p $LOCAL_CHIPYARD_DIR + mkdir -p $LOCAL_VERILATOR_DIR + copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR + copy $SERVER:$REMOTE_VERILATOR_DIR/ $LOCAL_VERILATOR_DIR fi diff --git a/.circleci/config.yml b/.circleci/config.yml index 61e73e54..0e971f74 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -7,479 +7,387 @@ version: 2 jobs: commit-on-master-check: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Check commits of each submodule command: | .circleci/check-commit.sh - install-riscv-toolchain: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - run: name: Building riscv-tools toolchain command: | .circleci/build-toolchains.sh riscv-tools no_output_timeout: 120m - - save_cache: key: riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} paths: - "/home/riscvuser/riscv-tools-install" - install-esp-toolchain: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} - - run: name: Building esp-tools toolchain command: | .circleci/build-toolchains.sh esp-tools no_output_timeout: 120m - - save_cache: key: esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} paths: - "/home/riscvuser/esp-tools-install" - install-verilator: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - restore_cache: keys: - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - - run: name: Build Verilator command: | .circleci/build-verilator.sh no_output_timeout: 120m - - save_cache: key: verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} paths: - - "/home/riscvuser/project/sims/verisim/verilator" - + - "/home/riscvuser/verilator" prepare-example: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - - run: name: Building the example subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=example no_output_timeout: 120m - - save_cache: key: example-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - prepare-boomexample: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - - run: name: Building the boomexample subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig no_output_timeout: 120m - - save_cache: key: boomexample-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - prepare-boomrocketexample: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - - run: name: Building the boomrocketexample subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig no_output_timeout: 120m - - save_cache: key: boomrocketexample-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - prepare-boom: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - - run: name: Building the boom subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=boom no_output_timeout: 120m - - save_cache: key: boom-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - prepare-rocketchip: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - - run: name: Building the rocketchip subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=rocketchip no_output_timeout: 120m - - save_cache: key: rocketchip-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - - prepare-hwacha-verilog-only: + prepare-hwacha: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} - - run: name: Building the hwacha subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=hwacha verilog + command: .circleci/do-rtl-build.sh SUB_PROJECT=hwacha no_output_timeout: 120m - - save_cache: key: hwacha-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - example-run-benchmark-tests: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - example-{{ .Branch }}-{{ .Revision }} - - run: name: Run example benchmark tests command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example - boomexample-run-benchmark-tests: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - boomexample-{{ .Branch }}-{{ .Revision }} - - run: name: Run boomexample benchmark tests command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig - boomrocketexample-run-benchmark-tests: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - boomrocketexample-{{ .Branch }}-{{ .Revision }} - - run: name: Run boomrocketexample benchmark tests command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig - boom-run-benchmark-tests: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - boom-{{ .Branch }}-{{ .Revision }} - - run: name: Run boom benchmark tests command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boom - rocketchip-run-benchmark-tests: docker: - - image: riscvboom/riscvboom-images:0.0.5 + - image: riscvboom/riscvboom-images:0.0.10 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb - steps: - # Checkout the code - checkout - - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - - restore_cache: keys: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - - restore_cache: keys: - rocketchip-{{ .Branch }}-{{ .Revision }} - - run: name: Run rocketchip benchmark tests command: make run-bmark-tests -C sims/verisim SUB_PROJECT=rocketchip - -# hwacha-run-benchmark-tests: -# docker: -# - image: riscvboom/riscvboom-images:0.0.5 -# environment: -# JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit -# TERM: dumb -# -# steps: -# # Checkout the code -# - checkout -# -# - run: -# name: Create hash of toolchains -# command: | -# .circleci/create-hash.sh -# -# - restore_cache: -# keys: -# - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} -# -# - restore_cache: -# keys: -# - hwacha-{{ .Branch }}-{{ .Revision }} -# -# - run: -# name: Run hwacha benchmark tests -# command: make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha + hwacha-run-benchmark-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.10 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + steps: + - checkout + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + - restore_cache: + keys: + - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} + - restore_cache: + keys: + - hwacha-{{ .Branch }}-{{ .Revision }} + - run: + name: Run hwacha benchmark tests + command: export RISCV=/home/riscvuser/esp-tools-install; export LD_LIBRARY_PATH=$RISCV/lib; make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha # Order and dependencies of jobs to run workflows: @@ -523,9 +431,8 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-hwacha-verilog-only: + - prepare-hwacha: requires: - - install-riscv-toolchain # TODO: Remove when esp-tools is used - install-esp-toolchain - install-verilator @@ -557,8 +464,7 @@ workflows: - install-riscv-toolchain - prepare-rocketchip -# - hwacha-run-benchmark-tests: -# requires: -# - install-riscv-toolchain # TODO: Remove when esp-tools is used -# - install-esp-toolchain -# - prepare-hwacha + - hwacha-run-benchmark-tests: + requires: + - install-esp-toolchain + - prepare-hwacha diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh new file mode 100755 index 00000000..78c4a350 --- /dev/null +++ b/.circleci/defaults.sh @@ -0,0 +1,28 @@ +#!/bin/bash + +copy () { + rsync -avzp -e 'ssh' $1 $2 +} + +run () { + ssh -o "StrictHostKeyChecking no" -t $SERVER $1 +} + +clean () { + # remove remote work dir + run "rm -rf $REMOTE_WORK_DIR" +} + +# remote variables +REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB +REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install +REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard +REMOTE_VERILATOR_DIR=$REMOTE_WORK_DIR/verilator +REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verisim + +# local variables (aka within the docker container) +LOCAL_CHECKOUT_DIR=$HOME/project +LOCAL_RISCV_DIR=$HOME/riscv-tools-install +LOCAL_CHIPYARD_DIR=$HOME/chipyard +LOCAL_VERILATOR_DIR=$HOME/verilator +LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verisim diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 51ad760b..af46dbcb 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -6,15 +6,32 @@ # turn echo on and error on earliest command set -ex -# init all submodules -cd $HOME/project -./scripts/init-submodules-no-riscv-tools.sh +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh -# enter the verisim directory and build the specific config -cd sims/verisim -make clean +# call clean on exit +trap clean EXIT -# run the particular build command -make JAVA_ARGS="-Xmx2G -Xss8M" $@ +# set stricthostkeychecking to no (must happen before rsync) +run "echo \"Ping $SERVER\"" -rm -rf ../../project +clean + +# copy over riscv-tools, verilator, and chipyard to remote +run "mkdir -p $REMOTE_RISCV_DIR" +run "mkdir -p $REMOTE_CHIPYARD_DIR" +run "mkdir -p $REMOTE_VERILATOR_DIR" +copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR +copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR +copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR + +# enter the verisim directory and build the specific config on remote server +run "cd $REMOTE_CHIPYARD_DIR && ./scripts/init-submodules-no-riscv-tools.sh" +run "make -C $REMOTE_SIM_DIR clean" +run "export RISCV=\"$REMOTE_RISCV_DIR\"; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" SUB_PROJECT=boom CONFIG=$1 TOP=BoomRocketSystem" +run "rm -rf $REMOTE_CHIPYARD_DIR/project" + +# copy back the final build +mkdir -p $LOCAL_CHIPYARD_DIR +copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR From 3e59bc07251ee93db2845fcc5665eda2693c55a2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 Jul 2019 16:15:04 -0700 Subject: [PATCH 045/160] update the readme --- .circleci/README.md | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/.circleci/README.md b/.circleci/README.md index 018b4b57..83fd3264 100644 --- a/.circleci/README.md +++ b/.circleci/README.md @@ -1,7 +1,7 @@ Chipyard CI =========== -Website: https://circleci.com/gh/ucb-bar/project-template +Website: https://circleci.com/gh/ucb-bar/chipyard CircleCI Brief Explanation --------------------------- @@ -35,11 +35,12 @@ Here the key is built from a string where the `checksum` portion converts the fi This directory contains all the collateral for the Chipyard CI to work. The following is included: - build-toolchains.sh # build either riscv-tools or esp-tools - build-verilator.sh # build verilator - create-hash.sh # create hashes of riscv-tools/esp-tools so circleci caching can work - do-rtl-build.sh # use verilator to build a sim executable - config.yml # main circleci config script to enumerate jobs/workflows + `build-toolchains.sh` # build either riscv-tools or esp-tools + `build-verilator.sh` # build verilator (remotely) + `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work + `do-rtl-build.sh` # use verilator to build a sim executable (remotely) + `config.yml` # main circleci config script to enumerate jobs/workflows + `defaults.sh` # default variables used How things are setup for Chipyard --------------------------------- @@ -52,3 +53,18 @@ The docker image sets up the `PATH` and `RISCV` variable so that `riscv-tools` i This requires the `riscv-tools` for `fesvr` and `verilator` to be able to build the binary. This stores all collateral for the tests (srcs, generated-srcs, sim binary, etc) to run "out of the gate" in the next job (make needs everything or else it will run again). 4th, finally run the tests that were wanted. + +Other CI Setup +-------------- + +To get the CI to work correctly you need to setup CircleCI environment variables to point to the remote directory to build files and the server user/ip. +In the project settings, you can find this under "Build Settings" "Environment Variables". +You need to add two variables like the following: + +CI\_DIR = /path/to/where/you/want/to/store/remote/files +SERVER = username@myserver.coolmachine.berkeley.edu + +Additionally, you need to add under the "PERMISSIONS" "SSH Permissions" section a private key that is on the build server that you are using. +After adding a private key, it will show a fingerprint that should be added under the jobs that need to be run. + +Note: On the remote server you need to have the `*.pub` key file added to the `authorized_keys` file. From 4963b607e1533a4a65476cc9e17e95f766385104 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 Jul 2019 16:22:29 -0700 Subject: [PATCH 046/160] remove extra dependencies --- .circleci/config.yml | 6 ------ 1 file changed, 6 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 0e971f74..ad81f5fc 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -441,30 +441,24 @@ workflows: # Run the example tests - example-run-benchmark-tests: requires: - - install-riscv-toolchain - prepare-example - boomexample-run-benchmark-tests: requires: - - install-riscv-toolchain - prepare-boomexample - boomrocketexample-run-benchmark-tests: requires: - - install-riscv-toolchain - prepare-boomrocketexample - boom-run-benchmark-tests: requires: - - install-riscv-toolchain - prepare-boom - rocketchip-run-benchmark-tests: requires: - - install-riscv-toolchain - prepare-rocketchip - hwacha-run-benchmark-tests: requires: - - install-esp-toolchain - prepare-hwacha From f5a3ff3ac542591afa01a7d3458a11f3df72d8b8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 Jul 2019 16:31:36 -0700 Subject: [PATCH 047/160] update variables | add more repos to commit check --- .circleci/build-toolchains.sh | 6 +++++- .circleci/check-commit.sh | 8 ++++++-- .circleci/create-hash.sh | 6 +++++- .circleci/defaults.sh | 4 +++- 4 files changed, 19 insertions(+), 5 deletions(-) diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index 6965da30..d0be57c2 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -6,9 +6,13 @@ # turn echo on and error on earliest command set -ex +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + if [ ! -d "$HOME/$1-install" ]; then cd $HOME # init all submodules including the tools - CHIPYARD_DIR=$HOME/project ./project/scripts/build-toolchains.sh $1 + CHIPYARD_DIR=$LOCAL_CHIPYARD_DIR .$LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 fi diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index ea7e30f5..4ad48ed5 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -5,8 +5,12 @@ # turn echo on and error on earliest command set -ex +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + # enter bhd repo -cd $HOME/project +cd $LOCAL_CHIPYARD_DIR # initialize submodules and get the hashes git submodule update --init @@ -22,7 +26,7 @@ search () { done } -submodules=("boom" "hwacha" "rocket-chip" "sifive-blocks" "testchipip") +submodules=("boom" "firechip" "hwacha" "icenet" "rocket-chip" "sifive-blocks" "sifive-cache" "testchipip") dir="generators" search diff --git a/.circleci/create-hash.sh b/.circleci/create-hash.sh index 2aff9727..84a75244 100755 --- a/.circleci/create-hash.sh +++ b/.circleci/create-hash.sh @@ -5,8 +5,12 @@ # turn echo on and error on earliest command set -ex +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + # enter bhd repo -cd $HOME/project +cd $LOCAL_CHIPYARD_DIR # get the version of riscv-tools from the git submodule hash git submodule status | grep "riscv-tools" | awk '{print$1}' | grep -o "[[:alnum:]]*" >> $HOME/riscv-tools.hash diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 78c4a350..b639009e 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -16,6 +16,7 @@ clean () { # remote variables REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install +REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_VERILATOR_DIR=$REMOTE_WORK_DIR/verilator REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verisim @@ -23,6 +24,7 @@ REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verisim # local variables (aka within the docker container) LOCAL_CHECKOUT_DIR=$HOME/project LOCAL_RISCV_DIR=$HOME/riscv-tools-install -LOCAL_CHIPYARD_DIR=$HOME/chipyard +LOCAL_ESP_DIR=$HOME/esp-tools-install +LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR LOCAL_VERILATOR_DIR=$HOME/verilator LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verisim From 1094b5723e3c4f171e66d471cacb7077e6c2fb69 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 Jul 2019 16:50:02 -0700 Subject: [PATCH 048/160] bump verilator cache --- .circleci/config.yml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index ad81f5fc..94584c8a 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -78,14 +78,14 @@ jobs: - checkout - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Build Verilator command: | .circleci/build-verilator.sh no_output_timeout: 120m - save_cache: - key: verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + key: verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} paths: - "/home/riscvuser/verilator" prepare-example: @@ -108,7 +108,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the example subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=example @@ -137,7 +137,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boomexample subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig @@ -166,7 +166,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boomrocketexample subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig @@ -195,7 +195,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boom subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=boom @@ -224,7 +224,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the rocketchip subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=rocketchip @@ -253,7 +253,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the hwacha subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=hwacha From 64daa500a057962e073ff6b0c6abbbb78be41baf Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 Jul 2019 17:31:04 -0700 Subject: [PATCH 049/160] pass in all args for rtl build --- .circleci/do-rtl-build.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index af46dbcb..30790e38 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -29,7 +29,7 @@ copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR # enter the verisim directory and build the specific config on remote server run "cd $REMOTE_CHIPYARD_DIR && ./scripts/init-submodules-no-riscv-tools.sh" run "make -C $REMOTE_SIM_DIR clean" -run "export RISCV=\"$REMOTE_RISCV_DIR\"; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" SUB_PROJECT=boom CONFIG=$1 TOP=BoomRocketSystem" +run "export RISCV=\"$REMOTE_RISCV_DIR\"; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" $@" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build From 847a874762ecfbbc30cc62f7652df90c823a06df Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 Jul 2019 18:26:37 -0700 Subject: [PATCH 050/160] pass correct verilator root --- .circleci/do-rtl-build.sh | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 30790e38..85bbc3ec 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -13,6 +13,9 @@ source $SCRIPT_DIR/defaults.sh # call clean on exit trap clean EXIT +cd $LOCAL_CHIPYARD_DIR +./scripts/init-submodules-no-riscv-tools.sh + # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" @@ -27,9 +30,8 @@ copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR # enter the verisim directory and build the specific config on remote server -run "cd $REMOTE_CHIPYARD_DIR && ./scripts/init-submodules-no-riscv-tools.sh" run "make -C $REMOTE_SIM_DIR clean" -run "export RISCV=\"$REMOTE_RISCV_DIR\"; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" $@" +run "export RISCV=\"$REMOTE_RISCV_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" $@" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build From 72f4941d4bce1b8352c3d6cc3d11488dfdef62ce Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 Jul 2019 18:43:22 -0700 Subject: [PATCH 051/160] update verilator_root --- .circleci/do-rtl-build.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 85bbc3ec..8ead657b 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -31,7 +31,7 @@ copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR # enter the verisim directory and build the specific config on remote server run "make -C $REMOTE_SIM_DIR clean" -run "export RISCV=\"$REMOTE_RISCV_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" $@" +run "export RISCV=\"$REMOTE_RISCV_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" $@" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build From 82e781420550592703e880766f5fcbfef1e38eec Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 Jul 2019 23:38:25 -0700 Subject: [PATCH 052/160] add cleanup script | fix verilator unknown bin --- .circleci/build-verilator.sh | 4 ++++ .circleci/clean-old-files.sh | 30 ++++++++++++++++++++++++++++++ .circleci/config.yml | 16 ++++++++-------- .circleci/defaults.sh | 4 ++++ 4 files changed, 46 insertions(+), 8 deletions(-) create mode 100755 .circleci/clean-old-files.sh diff --git a/.circleci/build-verilator.sh b/.circleci/build-verilator.sh index 5a837e1f..673ae527 100755 --- a/.circleci/build-verilator.sh +++ b/.circleci/build-verilator.sh @@ -12,6 +12,8 @@ source $SCRIPT_DIR/defaults.sh # call clean on exit trap clean EXIT +run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh + if [ ! -d "$LOCAL_VERILATOR_DIR" ]; then # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" @@ -28,4 +30,6 @@ if [ ! -d "$LOCAL_VERILATOR_DIR" ]; then mkdir -p $LOCAL_VERILATOR_DIR copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR copy $SERVER:$REMOTE_VERILATOR_DIR/ $LOCAL_VERILATOR_DIR + + cp -r $LOCAL_VERILATOR_DIR/install/bin/* $LOCAL_VERILATOR_DIR/install/share/verilator/bin/. fi diff --git a/.circleci/clean-old-files.sh b/.circleci/clean-old-files.sh new file mode 100755 index 00000000..0fe4f429 --- /dev/null +++ b/.circleci/clean-old-files.sh @@ -0,0 +1,30 @@ +#!/bin/bash + +# clean directories that are older than 30 days + +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + +age () { + local AGE_SEC + local CUR_SEC + local DIFF_SEC + local SEC_PER_DAY + + SEC_PER_DAY=86400 + + CUR_SEC=$(date +%s) + AGE_SEC=$(stat -c %Y -- "$1") + DIFF_SEC=$(expr $CUR_SEC - $AGE_SEC) + + echo $(expr $DIFF_SEC / $SEC_PER_DAY) +} + +for d in $CI_DIR/*/ ; do + DIR_AGE="$(age $d)" + if [ $DIR_AGE -ge 30 ]; then + echo "Deleting $d since is it $DIR_AGE old" + rm -rf $d + fi +done diff --git a/.circleci/config.yml b/.circleci/config.yml index 94584c8a..600cc998 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -78,14 +78,14 @@ jobs: - checkout - restore_cache: keys: - - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Build Verilator command: | .circleci/build-verilator.sh no_output_timeout: 120m - save_cache: - key: verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} + key: verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} paths: - "/home/riscvuser/verilator" prepare-example: @@ -108,7 +108,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the example subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=example @@ -137,7 +137,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boomexample subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig @@ -166,7 +166,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boomrocketexample subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig @@ -195,7 +195,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boom subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=boom @@ -224,7 +224,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the rocketchip subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=rocketchip @@ -253,7 +253,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v2-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the hwacha subproject using Verilator command: .circleci/do-rtl-build.sh SUB_PROJECT=hwacha diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index b639009e..c4d7eb6f 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -8,6 +8,10 @@ run () { ssh -o "StrictHostKeyChecking no" -t $SERVER $1 } +run_script () { + ssh -o "StrictHostKeyChecking no" -t $SERVER 'bash -s' < $1 +} + clean () { # remove remote work dir run "rm -rf $REMOTE_WORK_DIR" From fdf0edf8e01afec05d6e7300286bb3bcf6bdd8f6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 9 Jul 2019 23:42:04 -0700 Subject: [PATCH 053/160] fix cleanup script --- .circleci/build-verilator.sh | 2 +- .circleci/clean-old-files.sh | 9 ++++----- .circleci/defaults.sh | 2 +- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/.circleci/build-verilator.sh b/.circleci/build-verilator.sh index 673ae527..2c0b6a13 100755 --- a/.circleci/build-verilator.sh +++ b/.circleci/build-verilator.sh @@ -12,7 +12,7 @@ source $SCRIPT_DIR/defaults.sh # call clean on exit trap clean EXIT -run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh +run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR if [ ! -d "$LOCAL_VERILATOR_DIR" ]; then # set stricthostkeychecking to no (must happen before rsync) diff --git a/.circleci/clean-old-files.sh b/.circleci/clean-old-files.sh index 0fe4f429..96fcf8d7 100755 --- a/.circleci/clean-old-files.sh +++ b/.circleci/clean-old-files.sh @@ -1,10 +1,7 @@ #!/bin/bash # clean directories that are older than 30 days - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh +# argument is used as the directory to look in age () { local AGE_SEC @@ -21,10 +18,12 @@ age () { echo $(expr $DIFF_SEC / $SEC_PER_DAY) } -for d in $CI_DIR/*/ ; do +for d in $1/*/ ; do DIR_AGE="$(age $d)" if [ $DIR_AGE -ge 30 ]; then echo "Deleting $d since is it $DIR_AGE old" rm -rf $d + else + echo "Keep $d since it is $DIR_AGE old" fi done diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index c4d7eb6f..accf4ff9 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -9,7 +9,7 @@ run () { } run_script () { - ssh -o "StrictHostKeyChecking no" -t $SERVER 'bash -s' < $1 + ssh -o "StrictHostKeyChecking no" -t $SERVER 'bash -s' < $1 "$2" } clean () { From 64690459895b2774c29f9415287d1624b60e6772 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 10 Jul 2019 09:29:06 -0700 Subject: [PATCH 054/160] wrap variables in runtest --- .circleci/config.yml | 54 ++++++++++++++++++++++++++++-------------- .circleci/run-tests.sh | 50 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+), 18 deletions(-) create mode 100755 .circleci/run-tests.sh diff --git a/.circleci/config.yml b/.circleci/config.yml index 600cc998..91fd44ca 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -262,7 +262,7 @@ jobs: key: hwacha-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" - example-run-benchmark-tests: + example-run-tests: docker: - image: riscvboom/riscvboom-images:0.0.10 environment: @@ -280,10 +280,13 @@ jobs: - restore_cache: keys: - example-{{ .Branch }}-{{ .Revision }} + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Run example benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example - boomexample-run-benchmark-tests: + command: .circleci/run-tests.sh example + boomexample-run-tests: docker: - image: riscvboom/riscvboom-images:0.0.10 environment: @@ -301,10 +304,13 @@ jobs: - restore_cache: keys: - boomexample-{{ .Branch }}-{{ .Revision }} + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Run boomexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig - boomrocketexample-run-benchmark-tests: + command: .circleci/run-tests.sh boomexample + boomrocketexample-run-tests: docker: - image: riscvboom/riscvboom-images:0.0.10 environment: @@ -322,10 +328,13 @@ jobs: - restore_cache: keys: - boomrocketexample-{{ .Branch }}-{{ .Revision }} + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Run boomrocketexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig - boom-run-benchmark-tests: + command: .circleci/run-tests.sh boomrocketexample + boom-run-tests: docker: - image: riscvboom/riscvboom-images:0.0.10 environment: @@ -343,10 +352,13 @@ jobs: - restore_cache: keys: - boom-{{ .Branch }}-{{ .Revision }} + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Run boom benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boom - rocketchip-run-benchmark-tests: + command: .circleci/run-tests.sh boom + rocketchip-run-tests: docker: - image: riscvboom/riscvboom-images:0.0.10 environment: @@ -364,10 +376,13 @@ jobs: - restore_cache: keys: - rocketchip-{{ .Branch }}-{{ .Revision }} + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Run rocketchip benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=rocketchip - hwacha-run-benchmark-tests: + command: .circleci/run-tests.sh rocketchip + hwacha-run-tests: docker: - image: riscvboom/riscvboom-images:0.0.10 environment: @@ -385,9 +400,12 @@ jobs: - restore_cache: keys: - hwacha-{{ .Branch }}-{{ .Revision }} + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Run hwacha benchmark tests - command: export RISCV=/home/riscvuser/esp-tools-install; export LD_LIBRARY_PATH=$RISCV/lib; make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha + command: export RISCV=/home/riscvuser/esp-tools-install; export LD_LIBRARY_PATH=$RISCV/lib; .circleci/run-tests.sh hwacha # Order and dependencies of jobs to run workflows: @@ -439,26 +457,26 @@ workflows: # Run the respective tests # Run the example tests - - example-run-benchmark-tests: + - example-run-tests: requires: - prepare-example - - boomexample-run-benchmark-tests: + - boomexample-run-tests: requires: - prepare-boomexample - - boomrocketexample-run-benchmark-tests: + - boomrocketexample-run-tests: requires: - prepare-boomrocketexample - - boom-run-benchmark-tests: + - boom-run-tests: requires: - prepare-boom - - rocketchip-run-benchmark-tests: + - rocketchip-run-tests: requires: - prepare-rocketchip - - hwacha-run-benchmark-tests: + - hwacha-run-tests: requires: - prepare-hwacha diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh new file mode 100755 index 00000000..a2b63f01 --- /dev/null +++ b/.circleci/run-tests.sh @@ -0,0 +1,50 @@ +#!/bin/bash + +# run the different tests + +# turn echo on and error on earliest command +set -ex + +# get remote exec variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + +run_bmark () { + export VERILATOR_ROOT=$LOCAL_VERILATOR_DIR/install/share/verilator + make run-bmark-tests-fast -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ +} + +run_asm () { + export VERILATOR_ROOT=$LOCAL_VERILATOR_DIR/install/share/verilator + make run-asm-tests-fast -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ +} + +run_both () { + run_bmark $@ + run_asm $@ +} + +case $1 in + example) + run_bmark SUB_PROJECT=example + ;; + boomexample) + run_bmark SUB_PROJECT=example CONFIG=DefaultBoomConfig + ;; + boomrocketexample) + run_bmark SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig + ;; + boom) + run_bmark SUB_PROJECT=boom + ;; + rocketchip) + run_bmark SUB_PROJECT=rocketchip + ;; + hwacha) + run_bmark SUB_PROJECT=hwacha + ;; + *) + echo "No set of tests for $1. Did you spell it right?" + exit 1 + ;; +esac From 06b45c01ed43445c7fcc1bd789421f3fde403390 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 10 Jul 2019 09:52:44 -0700 Subject: [PATCH 055/160] use large boom configs everywhere --- .circleci/config.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 91fd44ca..0c2121a5 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -140,7 +140,7 @@ jobs: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boomexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=DefaultBoomConfig no_output_timeout: 120m - save_cache: key: boomexample-{{ .Branch }}-{{ .Revision }} @@ -169,7 +169,7 @@ jobs: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boomrocketexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig no_output_timeout: 120m - save_cache: key: boomrocketexample-{{ .Branch }}-{{ .Revision }} From 8e529e86bc20855e261cf2defc5a1faeaf60c923 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 10 Jul 2019 11:06:49 -0700 Subject: [PATCH 056/160] ensure all args are passed to run --- .circleci/defaults.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index accf4ff9..39a0c9a3 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -5,7 +5,7 @@ copy () { } run () { - ssh -o "StrictHostKeyChecking no" -t $SERVER $1 + ssh -o "StrictHostKeyChecking no" -t $SERVER $@ } run_script () { From 228cd3630165db67fba84ebdfce4b9298753c973 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 10 Jul 2019 13:35:19 -0700 Subject: [PATCH 057/160] remove duplicate blackbox files | general grep --- common.mk | 2 +- sims/vsim/Makefile | 15 +++++++++++---- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/common.mk b/common.mk index 1b0d139d..5f9d04cb 100644 --- a/common.mk +++ b/common.mk @@ -55,7 +55,7 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)" - grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) + grep -v ".*\.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs MACROCOMPILER_MODE ?= --mode synflops diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index f5882757..d434139a 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -58,8 +58,7 @@ VCS_NONCC_OPTS = \ +v2k \ +vcs+lic+wait \ +vc+list \ - -f $(sim_top_blackboxes) \ - -f $(sim_harness_blackboxes) \ + -f $(sim_vcs_blackboxes) \ -f $(sim_dotf) \ -sverilog \ +incdir+$(build_dir) \ @@ -75,14 +74,22 @@ VCS_NONCC_OPTS = \ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) +######################################################################################## +# remove duplicate blackboxes +######################################################################################## +sim_vcs_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.vcs.f + +$(sim_vcs_blackboxes): $(sim_top_blackboxes) $(sim_harness_blackboxes) + join -a 1 -a 2 <(sort $(sim_top_blackboxes)) <(sort $(sim_harness_blackboxes)) > $@ + ######################################################################################### # vcs simulator rules ######################################################################################### -$(sim): $(sim_vsrcs) $(sim_dotf) +$(sim): $(sim_vsrcs) $(sim_dotf) $(sim_vcs_blackboxes) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug) : $(sim_vsrcs) $(sim_dotf) +$(sim_debug) : $(sim_vsrcs) $(sim_dotf) $(sim_vcs_blackboxes) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp From 1abde25fd679bb94f5fc7ad08c98801c97840ff8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 10 Jul 2019 15:39:50 -0700 Subject: [PATCH 058/160] use key/value store for build strings | run simple hwacha tests --- .circleci/config.yml | 24 ++++++++++++------------ .circleci/defaults.sh | 9 +++++++++ .circleci/do-rtl-build.sh | 2 +- .circleci/run-tests.sh | 16 ++++++++-------- 4 files changed, 30 insertions(+), 21 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 0c2121a5..73fe147d 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -111,7 +111,7 @@ jobs: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the example subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=example + command: .circleci/do-rtl-build.sh example no_output_timeout: 120m - save_cache: key: example-{{ .Branch }}-{{ .Revision }} @@ -140,7 +140,7 @@ jobs: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boomexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=DefaultBoomConfig + command: .circleci/do-rtl-build.sh boomexample no_output_timeout: 120m - save_cache: key: boomexample-{{ .Branch }}-{{ .Revision }} @@ -169,7 +169,7 @@ jobs: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boomrocketexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig + command: .circleci/do-rtl-build.sh boomrocketexample no_output_timeout: 120m - save_cache: key: boomrocketexample-{{ .Branch }}-{{ .Revision }} @@ -198,7 +198,7 @@ jobs: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the boom subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=boom + command: .circleci/do-rtl-build.sh boom no_output_timeout: 120m - save_cache: key: boom-{{ .Branch }}-{{ .Revision }} @@ -227,7 +227,7 @@ jobs: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the rocketchip subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=rocketchip + command: .circleci/do-rtl-build.sh rocketchip no_output_timeout: 120m - save_cache: key: rocketchip-{{ .Branch }}-{{ .Revision }} @@ -256,7 +256,7 @@ jobs: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Building the hwacha subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=hwacha + command: .circleci/do-rtl-build.sh hwacha no_output_timeout: 120m - save_cache: key: hwacha-{{ .Branch }}-{{ .Revision }} @@ -284,7 +284,7 @@ jobs: keys: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: - name: Run example benchmark tests + name: Run example tests command: .circleci/run-tests.sh example boomexample-run-tests: docker: @@ -308,7 +308,7 @@ jobs: keys: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: - name: Run boomexample benchmark tests + name: Run boomexample tests command: .circleci/run-tests.sh boomexample boomrocketexample-run-tests: docker: @@ -332,7 +332,7 @@ jobs: keys: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: - name: Run boomrocketexample benchmark tests + name: Run boomrocketexample tests command: .circleci/run-tests.sh boomrocketexample boom-run-tests: docker: @@ -356,7 +356,7 @@ jobs: keys: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: - name: Run boom benchmark tests + name: Run boom tests command: .circleci/run-tests.sh boom rocketchip-run-tests: docker: @@ -380,7 +380,7 @@ jobs: keys: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: - name: Run rocketchip benchmark tests + name: Run rocketchip tests command: .circleci/run-tests.sh rocketchip hwacha-run-tests: docker: @@ -404,7 +404,7 @@ jobs: keys: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: - name: Run hwacha benchmark tests + name: Run hwacha tests command: export RISCV=/home/riscvuser/esp-tools-install; export LD_LIBRARY_PATH=$RISCV/lib; .circleci/run-tests.sh hwacha # Order and dependencies of jobs to run diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 39a0c9a3..a17dca78 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -32,3 +32,12 @@ LOCAL_ESP_DIR=$HOME/esp-tools-install LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR LOCAL_VERILATOR_DIR=$HOME/verilator LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verisim + +# key value store to get the build strings +declare -A mapping +mapping["example"]="SUB_PROJECT=example" +mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig" +mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig" +mapping["boom"]="SUB_PROJECT=boom" +mapping["rocketchip"]="SUB_PROJECT=rocketchip" +mapping["hwacha"]="SUB_PROJECT=hwacha" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 8ead657b..c99c490e 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -31,7 +31,7 @@ copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR # enter the verisim directory and build the specific config on remote server run "make -C $REMOTE_SIM_DIR clean" -run "export RISCV=\"$REMOTE_RISCV_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" $@" +run "export RISCV=\"$REMOTE_RISCV_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" $mapping[$1]" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index a2b63f01..bd49f17a 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -9,13 +9,13 @@ set -ex SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh +export VERILATOR_ROOT=$LOCAL_VERILATOR_DIR/install/share/verilator + run_bmark () { - export VERILATOR_ROOT=$LOCAL_VERILATOR_DIR/install/share/verilator make run-bmark-tests-fast -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ } run_asm () { - export VERILATOR_ROOT=$LOCAL_VERILATOR_DIR/install/share/verilator make run-asm-tests-fast -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ } @@ -26,22 +26,22 @@ run_both () { case $1 in example) - run_bmark SUB_PROJECT=example + run_bmark $mapping[$1] ;; boomexample) - run_bmark SUB_PROJECT=example CONFIG=DefaultBoomConfig + run_bmark $mapping[$1] ;; boomrocketexample) - run_bmark SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig + run_bmark $mapping[$1] ;; boom) - run_bmark SUB_PROJECT=boom + run_bmark $mapping[$1] ;; rocketchip) - run_bmark SUB_PROJECT=rocketchip + run_bmark $mapping[$1] ;; hwacha) - run_bmark SUB_PROJECT=hwacha + make run-rv64uv-p-asm-tests-fst -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $mapping[$1] ;; *) echo "No set of tests for $1. Did you spell it right?" From 9f9b7087ed88ee7fe1bb81243b210f3f99444a8f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 10 Jul 2019 15:50:22 -0700 Subject: [PATCH 059/160] fix key/value store access --- .circleci/do-rtl-build.sh | 2 +- .circleci/run-tests.sh | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index c99c490e..40975108 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -31,7 +31,7 @@ copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR # enter the verisim directory and build the specific config on remote server run "make -C $REMOTE_SIM_DIR clean" -run "export RISCV=\"$REMOTE_RISCV_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" $mapping[$1]" +run "export RISCV=\"$REMOTE_RISCV_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" ${mapping[$1]}" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index bd49f17a..e0587e03 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -26,22 +26,22 @@ run_both () { case $1 in example) - run_bmark $mapping[$1] + run_bmark ${mapping[$1]} ;; boomexample) - run_bmark $mapping[$1] + run_bmark ${mapping[$1]} ;; boomrocketexample) - run_bmark $mapping[$1] + run_bmark ${mapping[$1]} ;; boom) - run_bmark $mapping[$1] + run_bmark ${mapping[$1]} ;; rocketchip) - run_bmark $mapping[$1] + run_bmark ${mapping[$1]} ;; hwacha) - make run-rv64uv-p-asm-tests-fst -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $mapping[$1] + make run-rv64uv-p-asm-tests-fst -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} ;; *) echo "No set of tests for $1. Did you spell it right?" From 37241af1fca7be9dec04be37f8d477e7bcd91003 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 4 Jun 2019 10:36:25 -0700 Subject: [PATCH 060/160] Add initial VLSI flow scripts --- .gitmodules | 4 ++ vlsi/.gitignore | 6 +++ vlsi/Makefile | 122 ++++++++++++++++++++++++++++++++++++++++++++++ vlsi/README.md | 5 ++ vlsi/example-vlsi | 36 ++++++++++++++ vlsi/hammer | 1 + 6 files changed, 174 insertions(+) create mode 100644 vlsi/.gitignore create mode 100644 vlsi/Makefile create mode 100644 vlsi/README.md create mode 100755 vlsi/example-vlsi create mode 160000 vlsi/hammer diff --git a/.gitmodules b/.gitmodules index ca80d661..9e30fb35 100644 --- a/.gitmodules +++ b/.gitmodules @@ -40,3 +40,7 @@ [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache url = https://github.com/sifive/block-inclusivecache-sifive.git +[submodule "vlsi/hammer"] + path = vlsi/hammer + url = git@github.com:ucb-bar/hammer.git + diff --git a/vlsi/.gitignore b/vlsi/.gitignore new file mode 100644 index 00000000..4cbcfe8f --- /dev/null +++ b/vlsi/.gitignore @@ -0,0 +1,6 @@ +inputs.yml +__pycache__ +hammer*.log +build +src/test/output-*.json +generated-src \ No newline at end of file diff --git a/vlsi/Makefile b/vlsi/Makefile new file mode 100644 index 00000000..5b6390b7 --- /dev/null +++ b/vlsi/Makefile @@ -0,0 +1,122 @@ +######################################################################################### +# vlsi makefile +######################################################################################### + +######################################################################################### +# general path variables +######################################################################################### +base_dir=$(abspath ..) +vlsi_dir=$(abspath .) +sim_dir=$(abspath .) + +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/variables.mk + +######################################################################################### +# import other necessary rules and variables +######################################################################################### +include $(base_dir)/common.mk + +######################################################################################### +# vlsi types and rules +######################################################################################### + +#sim_name is unused, but GenerateSimFiles expects it +sim_name ?= vcs +tech_name ?= +tech_dir ?= $(vlsi_dir)/hammer-$(tech_nam)-plugin/$(tech_name) +SMEMS_COMP ?= $(tech_dir)/sram-compiler.json +SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json +MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) +OBJ_DIR ?= $(vlsi_dir)/build +ENV_YML ?= $(vlsi_dir)/hammer-cad-plugins/bwrc-env.yml +INPUT_CONFS ?= example.yml $(dir $(tech_dir))/bwrc.yml +HAMMER_EXEC ?= ./example-vlsi + +ROCKET_SRC_DIR=$(ROCKETCHIP_DIR)/src/main/resources/vsrc + +ROCKET_SRCS = \ + $(ROCKET_SRC_DIR)/ClockDivider2.v \ + $(ROCKET_SRC_DIR)/ClockDivider3.v \ + $(ROCKET_SRC_DIR)/AsyncResetReg.v \ + $(ROCKET_SRC_DIR)/plusarg_reader.v \ + $(ROCKET_SRC_DIR)/EICG_wrapper.v \ + +ALL_RTL = $(ROCKET_SRCS) $(VERILOG_FILE) $(SMEMS_FILE) + +CLOCK_DOMAINS = $(build_dir)/$(long_name).domains + +.PHONY: default +default: all + +all: drc lvs + + +###################################################### SYN ############################################################ + +SYNTH_CONF = $(OBJ_DIR)/inputs.yml + +$(SYNTH_CONF): + mkdir -p $(dir $@) + echo "synthesis.inputs:" > $@ + echo " top_module: $(TOP)" >> $@ + echo " input_files:" >> $@ + for x in $(ALL_RTL); do \ + echo ' - "'$$x'"' >> $@; \ + done + +GENERATED_CONFS=$(SYNTH_CONF) $(SRAM_CONF) + +.PHONY: syn synthesis +syn: $(OBJ_DIR)/syn-rundir/$(TOP).mapped.v +synthesis: syn + +$(OBJ_DIR)/syn-rundir/$(TOP).mapped.v $(OBJ_DIR)/syn-rundir/syn-output.json: $(ENV_YML) $(INPUT_CONFS) $(GENERATED_CONFS) $(ALL_RTL) + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) syn + +$(OBJ_DIR)/par-input.json: $(OBJ_DIR)/syn-rundir/syn-output.json + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $<, -p $(x)) -o $@ syn_to_par + +###################################################### PAR ############################################################ + +.PHONY: par place-and-route +par: $(OBJ_DIR)/par-rundir/$(TOP).gds +place-and-route: par + +$(OBJ_DIR)/par-rundir/$(TOP).gds $(OBJ_DIR)/par-rundir/par-output.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/syn-rundir/$(TOP).mapped.v + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) par + +$(OBJ_DIR)/drc-input.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/par-rundir/par-output.json + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$^, -p $(x)) -o $@ --obj_dir $(OBJ_DIR) par_to_drc + +###################################################### DRC ############################################################ +# TODO unimplemented +.PHONY: drc +drc: $(OBJ_DIR)/drc-rundir/drc_results.db + +$(OBJ_DIR)/drc-rundir/drc_results.db: $(OBJ_DIR)/drc-input.json $(OBJ_DIR)/par-rundir/$(TOP).gds + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) drc + +###################################################### LVS ############################################################ +# TODO unimplemented +$(OBJ_DIR)/lvs-input.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/par-rundir/par-output.json + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$^, -p $(x)) -o $@ --obj_dir $(OBJ_DIR) par_to_lvs + +.PHONY: lvs +lvs: $(OBJ_DIR)/lvs-rundir/lvs_results.rpt + +$(OBJ_DIR)/lvs-rundir/lvs_results.rpt: $(OBJ_DIR)/lvs-input.json $(OBJ_DIR)/par-rundir/$(TOP).gds + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) lvs + +.PHONY: clean +clean: + rm -rf $(OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) generated-src diff --git a/vlsi/README.md b/vlsi/README.md new file mode 100644 index 00000000..d09fb5d8 --- /dev/null +++ b/vlsi/README.md @@ -0,0 +1,5 @@ +This is the starting point for a vlsi flow from this repository. + +This flow will not work without the necessary CAD and technology plugins for HAMMER. + +If you are a UCB-affiliate, you may be able to acquire access to the tech-plugins. \ No newline at end of file diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi new file mode 100755 index 00000000..90ddec3c --- /dev/null +++ b/vlsi/example-vlsi @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 + +import hammer_vlsi +from hammer_vlsi import CLIDriver + +from typing import Dict, Callable, Optional + +def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: + x.append(''' +# TODO +''') + return True + +class ExampleDriver(CLIDriver): + + def action_map(self) -> Dict[str, Callable[[hammer_vlsi.HammerDriver, Callable[[str], None]], Optional[dict]]]: + par_action = self.create_par_action(custom_hooks=[ + hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells) + ]) + + new_dict = dict(super().action_map()) + new_dict.update({ + "par": par_action + }) + return new_dict + + def par_action(self, driver: hammer_vlsi.HammerDriver, append_error_func: Callable[[str], None]) -> Optional[dict]: + if not driver.load_par_tool(): + return None + success, par_output = driver.run_par(hook_actions=[ + hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells) + ]) + return par_output + +if __name__ == '__main__': + ExampleDriver().main() diff --git a/vlsi/hammer b/vlsi/hammer new file mode 160000 index 00000000..873b2c1a --- /dev/null +++ b/vlsi/hammer @@ -0,0 +1 @@ +Subproject commit 873b2c1af0a54cb339a19a7c8cf3a1e7905feb58 From f7735dedc0c3eb9744695af61de230864b05d12d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 4 Jun 2019 12:18:34 -0700 Subject: [PATCH 061/160] Use new API for par hooks | fix typo --- vlsi/Makefile | 2 +- vlsi/example-vlsi | 25 ++++--------------------- 2 files changed, 5 insertions(+), 22 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 5b6390b7..193ed0b4 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -26,7 +26,7 @@ include $(base_dir)/common.mk #sim_name is unused, but GenerateSimFiles expects it sim_name ?= vcs tech_name ?= -tech_dir ?= $(vlsi_dir)/hammer-$(tech_nam)-plugin/$(tech_name) +tech_dir ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 90ddec3c..3f65d9a5 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -1,9 +1,9 @@ #!/usr/bin/env python3 import hammer_vlsi -from hammer_vlsi import CLIDriver +from hammer_vlsi import CLIDriver, HammerToolHookAction -from typing import Dict, Callable, Optional +from typing import Dict, Callable, Optional, List def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: x.append(''' @@ -12,25 +12,8 @@ def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: return True class ExampleDriver(CLIDriver): - - def action_map(self) -> Dict[str, Callable[[hammer_vlsi.HammerDriver, Callable[[str], None]], Optional[dict]]]: - par_action = self.create_par_action(custom_hooks=[ - hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells) - ]) - - new_dict = dict(super().action_map()) - new_dict.update({ - "par": par_action - }) - return new_dict - - def par_action(self, driver: hammer_vlsi.HammerDriver, append_error_func: Callable[[str], None]) -> Optional[dict]: - if not driver.load_par_tool(): - return None - success, par_output = driver.run_par(hook_actions=[ - hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells) - ]) - return par_output + def get_extra_par_hooks(self) -> List[HammerToolHookAction]: + return [hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells)] if __name__ == '__main__': ExampleDriver().main() From 5414df40f029cdb420d21d7e1c2971d08ad25557 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 10 Jul 2019 17:51:46 -0700 Subject: [PATCH 062/160] setup esp-tools path --- .circleci/config.yml | 4 ++-- .circleci/do-rtl-build.sh | 18 ++++++++++++++---- .circleci/run-tests.sh | 2 ++ 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 73fe147d..de58be12 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -250,7 +250,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - esp-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} @@ -405,7 +405,7 @@ jobs: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} - run: name: Run hwacha tests - command: export RISCV=/home/riscvuser/esp-tools-install; export LD_LIBRARY_PATH=$RISCV/lib; .circleci/run-tests.sh hwacha + command: .circleci/run-tests.sh hwacha # Order and dependencies of jobs to run workflows: diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 40975108..2c7242cc 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -21,17 +21,27 @@ run "echo \"Ping $SERVER\"" clean -# copy over riscv-tools, verilator, and chipyard to remote -run "mkdir -p $REMOTE_RISCV_DIR" +# copy over riscv/esp-tools, verilator, and chipyard to remote run "mkdir -p $REMOTE_CHIPYARD_DIR" run "mkdir -p $REMOTE_VERILATOR_DIR" -copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR +TOOLS_DIR=$REMOTE_RISCV_DIR +LD_LIB_DIR=$REMOTE_RISCV_DIR/lib +if [ $1 = "hwacha" ]; then + TOOLS_DIR=$REMOTE_ESP_DIR + LD_LIB_DIR=$REMOTE_ESP_DIR/lib + run "mkdir -p $REMOTE_ESP_DIR" + copy $LOCAL_ESP_DIR/ $SERVER:$REMOTE_ESP_DIR +else + run "mkdir -p $REMOTE_RISCV_DIR" + copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR +fi + # enter the verisim directory and build the specific config on remote server run "make -C $REMOTE_SIM_DIR clean" -run "export RISCV=\"$REMOTE_RISCV_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" ${mapping[$1]}" +run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" ${mapping[$1]}" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index e0587e03..445278ee 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -41,6 +41,8 @@ case $1 in run_bmark ${mapping[$1]} ;; hwacha) + export RISCV=$REMOTE_ESP_DIR + export LD_LIBRARY_PATH=$REMOTE_ESP_DIR/lib make run-rv64uv-p-asm-tests-fst -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} ;; *) From 66443175dc61bb3d01b1f8076ffddff8bf197555 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 10 Jul 2019 20:09:24 -0700 Subject: [PATCH 063/160] pass the right hash --- .circleci/config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index de58be12..42397ea8 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -250,7 +250,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - esp-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} From cf4e383805bc7b63cd85474e2befb7e0ca2d244c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 10 Jul 2019 21:52:00 -0700 Subject: [PATCH 064/160] update esp tools to local dir --- .circleci/run-tests.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 445278ee..0f6ef18f 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -41,8 +41,8 @@ case $1 in run_bmark ${mapping[$1]} ;; hwacha) - export RISCV=$REMOTE_ESP_DIR - export LD_LIBRARY_PATH=$REMOTE_ESP_DIR/lib + export RISCV=$LOCAL_ESP_DIR + export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib make run-rv64uv-p-asm-tests-fst -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} ;; *) From ff945e38e5a81e9e77ae77688b78aaf84c808f49 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 10 Jul 2019 23:27:19 -0700 Subject: [PATCH 065/160] run normal tests (not fast) for hwacha --- .circleci/run-tests.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 0f6ef18f..99fd42dd 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -43,7 +43,8 @@ case $1 in hwacha) export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib - make run-rv64uv-p-asm-tests-fst -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} + export PATH=$RISCV/bin:$PATH + make run-rv64uv-p-asm-tests -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} ;; *) echo "No set of tests for $1. Did you spell it right?" From 5337a4472d897aee8e70e4dae19b8b2ed0967481 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 11 Jul 2019 09:52:06 -0700 Subject: [PATCH 066/160] cleaner implementation of dedup --- sims/vsim/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index d434139a..88aaed1e 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -80,7 +80,7 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) sim_vcs_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.vcs.f $(sim_vcs_blackboxes): $(sim_top_blackboxes) $(sim_harness_blackboxes) - join -a 1 -a 2 <(sort $(sim_top_blackboxes)) <(sort $(sim_harness_blackboxes)) > $@ + awk '{print $1;}' $^ | sort -u > $@ ######################################################################################### # vcs simulator rules From 0c5e3736e1fde3bb1cf5a08e239c01c293dc654d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 11 Jul 2019 11:26:51 -0700 Subject: [PATCH 067/160] Fix stupid rst title underlining warnings --- docs/Simulation/Commercial-Simulators.rst | 2 +- docs/Simulation/Open-Source-Simulators.rst | 2 +- docs/index.rst | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Commercial-Simulators.rst index 0e971d51..30d6f7ab 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/Commercial-Simulators.rst @@ -1,5 +1,5 @@ Commercial Software RTL Simulators -============================== +================================== VCS ----------------------- diff --git a/docs/Simulation/Open-Source-Simulators.rst b/docs/Simulation/Open-Source-Simulators.rst index bc8a0dcc..bd8d9534 100644 --- a/docs/Simulation/Open-Source-Simulators.rst +++ b/docs/Simulation/Open-Source-Simulators.rst @@ -1,5 +1,5 @@ Open Source Software RTL Simulators -============================== +=================================== Verilator ----------------------- diff --git a/docs/index.rst b/docs/index.rst index 019a6991..b2fa001a 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -4,7 +4,7 @@ contain the root `toctree` directive. Welcome to Chipyard's documentation! -================================= +==================================== Chipyard is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. From 72c4a6dc4c3ac1ba7e0bc372da8def1623bfd57f Mon Sep 17 00:00:00 2001 From: Adam Izraelevitz Date: Thu, 11 Jul 2019 13:20:16 -0700 Subject: [PATCH 068/160] Fix CircleCI link to chipyard --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 708de178..e59f5af5 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# Chipyard Framework [![CircleCI](https://circleci.com/gh/ucb-bar/project-template/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/project-template/tree/master) +# Chipyard Framework [![CircleCI](https://circleci.com/gh/ucb-bar/project-template/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/chipyard/tree/master) ## Using Chipyard From 7b43b3e951d54db0d1e9a5a46cc50cbaa9b8389c Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 11 Jul 2019 12:25:34 -0700 Subject: [PATCH 069/160] Rework simulation splash page --- ...rs.rst => FPGA-Accelerated-Simulators.rst} | 2 +- docs/Simulation/Open-Source-Simulators.rst | 35 ---------------- ...l-Simulators.rst => SW-RTL-Simulators.rst} | 40 +++++++++++++++++-- docs/Simulation/index.rst | 19 +++++---- 4 files changed, 50 insertions(+), 46 deletions(-) rename docs/Simulation/{FPGA-Based-Simulators.rst => FPGA-Accelerated-Simulators.rst} (97%) delete mode 100644 docs/Simulation/Open-Source-Simulators.rst rename docs/Simulation/{Commercial-Simulators.rst => SW-RTL-Simulators.rst} (50%) diff --git a/docs/Simulation/FPGA-Based-Simulators.rst b/docs/Simulation/FPGA-Accelerated-Simulators.rst similarity index 97% rename from docs/Simulation/FPGA-Based-Simulators.rst rename to docs/Simulation/FPGA-Accelerated-Simulators.rst index 1180b470..4fcc6668 100644 --- a/docs/Simulation/FPGA-Based-Simulators.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulators.rst @@ -1,4 +1,4 @@ -FPGA-Based Simulators +FPGA-Accelerated Simulators ============================== FireSim diff --git a/docs/Simulation/Open-Source-Simulators.rst b/docs/Simulation/Open-Source-Simulators.rst deleted file mode 100644 index bd8d9534..00000000 --- a/docs/Simulation/Open-Source-Simulators.rst +++ /dev/null @@ -1,35 +0,0 @@ -Open Source Software RTL Simulators -=================================== - -Verilator ------------------------ - -`Verilator `__ is an open-source LGPL-Licensed simulator maintained by `Veripool `__. -The Chipyard framework can download, build, and execute simulations using Verilator. - -To run a simulation using Verilator, perform the following steps: - -To compile the example design, run ``make`` in the ``sims/verisim`` directory. -This will elaborate the ``DefaultRocketConfig`` in the example project. - -An executable called ``simulator-example-DefaultRocketConfig`` will be produced. -This executable is a simulator that has been compiled based on the design that was built. -You can then use this executable to run any compatible RV64 code. -For instance, to run one of the riscv-tools assembly tests. - -.. code-block:: shell - - ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple - -If you later create your own project, you can use environment variables to build an alternate configuration. - -.. code-block:: shell - - make SUB_PROJECT=yourproject - ./simulator-- ... - -If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. -This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. -An open-source vcd-capable waveform viewer is `GTKWave `__. - -Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running. diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/SW-RTL-Simulators.rst similarity index 50% rename from docs/Simulation/Commercial-Simulators.rst rename to docs/Simulation/SW-RTL-Simulators.rst index 30d6f7ab..9df94d52 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/SW-RTL-Simulators.rst @@ -1,9 +1,43 @@ -Commercial Software RTL Simulators -================================== +Software RTL Simulators +=================================== -VCS +Verilator (Open-Source) ----------------------- +`Verilator `__ is an open-source LGPL-Licensed simulator maintained by `Veripool `__. +The Chipyard framework can download, build, and execute simulations using Verilator. + +To run a simulation using Verilator, perform the following steps: + +To compile the example design, run ``make`` in the ``sims/verisim`` directory. +This will elaborate the ``DefaultRocketConfig`` in the example project. + +An executable called ``simulator-example-DefaultRocketConfig`` will be produced. +This executable is a simulator that has been compiled based on the design that was built. +You can then use this executable to run any compatible RV64 code. +For instance, to run one of the riscv-tools assembly tests. + +.. code-block:: shell + + ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + +If you later create your own project, you can use environment variables to build an alternate configuration. + +.. code-block:: shell + + make SUB_PROJECT=yourproject + ./simulator-- ... + +If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. +This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. +An open-source vcd-capable waveform viewer is `GTKWave `__. + +Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running. +Commercial Software RTL Simulators + +Synopsys VCS (License Required) +-------------------------------- + `VCS `__ is a commercial RTL simulator developed by Synopsys. It requires commercial licenses. The Chipyard framework can compile and execute simulations using VCS. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index 339960bd..f8ff7e46 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,15 +1,20 @@ Simulators ======================= -Chipyard provides support and integration for multiple simulation flows, for various user levels and requirements. -In the majority of cases during a digital design development process, a simple software RTL simulation will do. -When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. -The following pages provide detailed information about the simulation possibilities within the Chipyard framework. +Chipyard supports two classes of simulation: + +#. Software RTL simulation using commercial or open-source (Verilator) RTL simulators +#. FPGA-accelerated full-system simulation using FireSim + +Software RTL simulators of Chipyard designs run at O(1 KHz), but compile +quickly and provide full waveforms. Conversly, FPGA-accelerated simulators run +at O(100 MHz), making them appropriate for booting an operating system and +running a complete workload, but have long compile time and poorer debug +visability. .. toctree:: :maxdepth: 2 :caption: Simulators: - Open-Source-Simulators - Commercial-Simulators - FPGA-Based-Simulators + SW-RTL-Simulators + FPGA-Accelerated-Simulators From 9f83b3a3d2ef84665e48dae516fb7410c2661768 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 11 Jul 2019 18:23:53 -0700 Subject: [PATCH 070/160] Update FireSim instructions --- .../FPGA-Accelerated-Simulators.rst | 55 +++++++++++++++++-- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/docs/Simulation/FPGA-Accelerated-Simulators.rst b/docs/Simulation/FPGA-Accelerated-Simulators.rst index 4fcc6668..a3bbbe19 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulators.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulators.rst @@ -9,9 +9,56 @@ FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than so FireSim also provides additional device models to allow full-system simulation, including memory models and network models. FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. -In order to simulate your Chipyard design using FireSim, you should follow the following steps: +In order to simulate your Chipyard design using FireSim, if you have not +already, follow the initial EC2 setup instructions as detailed in the `FireSim +documentation `__. +Then clone your full Chipyard repository onto your Amazon EC2 FireSim manager +instance, and setup your Chipyard repository as you would normally. -Follow the initial EC2 setup instructions as detailed in the `FireSim documentation `__. -Then clone your full Chipyard repository onto your Amazon EC2 FireSim manager instance. +When you are ready to use FireSim, initalize it as library in Chipyard by running: -Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for `running a simulation `__. +.. code-block:: shell + + # At the root of your chipyard repo + ./scripts/firesim-setup.sh --fast + + +``firesim-setup.sh`` initializes additional submodules and then invokes +firesim's ``build-setup.sh`` script. ``firesim-setup.sh`` accepts all of the same arguments and +passes them through to ``build-setup.sh``, adding ``--library`` to properly +initialize FireSim as a library submodule in chipyard. You may run +``./sims/firesim/build-setup.sh --help`` to see more options. + +In order to build bitstreams, run simulations, or to generate MIDAS-transformed RTL for your +simulator, you'll need to source one of the following three environments: + +.. code-block:: shell + + cd sims/firesim + # (Recommended) The default manager environment (includes env.sh) + source sourceme-f1-manager.sh + + # OR A minimal environment to run recipes out of sim/ (to invoke MIDAS; run MIDAS-level RTL simulation)generate RTL; transform At the root of your chipyard repo + source env.sh + + # OR A complete environment to run local FPGA builds with Vivado + source sourceme-f1-full.sh + +At this point you're ready to use FireSim with Chipyard. If you're not already +familiar with FireSim, please refer to the `FireSim Docs `__, and proceed +through the rest of the tutorial. + + +Current Limitations: +++++++++++++++++++++ + +FireSim integration in chipyard is still a work in progress. Presently, you +cannot build a FireSim simulator from any generator project in Chipyard except ``firechip``, +which properly invokes MIDAS on the target RTL. + +In the interim, workaround this limitation by importing Config and Module +classes from other generator projects into FireChip. You should then be able to +refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG`` +variables. Note that if your target machine has I/O not provided in the default +FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need +to write a custom endpoint. From 0e80a6b6bcb65ce9912ecdbd74ef32b3b077a4a0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 12 Jul 2019 11:52:44 -0700 Subject: [PATCH 071/160] bump testchipip to master --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 532d4a42..cd9d53c3 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 532d4a42914286548179f3893ab6349a0aedb5e3 +Subproject commit cd9d53c3611b075d0cb580e051cb3ae38864148b From 6e790abdeeb52a284f95c69f4a70343ad424eebb Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 Jul 2019 16:08:10 -0700 Subject: [PATCH 072/160] Add hammer-cad-plugins submodule --- .gitmodules | 3 +++ vlsi/Makefile | 2 +- vlsi/hammer-cad-plugins | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) create mode 160000 vlsi/hammer-cad-plugins diff --git a/.gitmodules b/.gitmodules index 9e30fb35..9729ae2e 100644 --- a/.gitmodules +++ b/.gitmodules @@ -43,4 +43,7 @@ [submodule "vlsi/hammer"] path = vlsi/hammer url = git@github.com:ucb-bar/hammer.git +[submodule "vlsi/hammer-cad-plugins"] + path = vlsi/hammer-cad-plugins + url = git@github.com:ucb-bar/hammer-cad-plugins diff --git a/vlsi/Makefile b/vlsi/Makefile index 193ed0b4..7dc797c6 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -31,7 +31,7 @@ SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) OBJ_DIR ?= $(vlsi_dir)/build -ENV_YML ?= $(vlsi_dir)/hammer-cad-plugins/bwrc-env.yml +ENV_YML ?= $(vlsi_dir)/bwrc-env.yml INPUT_CONFS ?= example.yml $(dir $(tech_dir))/bwrc.yml HAMMER_EXEC ?= ./example-vlsi diff --git a/vlsi/hammer-cad-plugins b/vlsi/hammer-cad-plugins new file mode 160000 index 00000000..72809f53 --- /dev/null +++ b/vlsi/hammer-cad-plugins @@ -0,0 +1 @@ +Subproject commit 72809f538c4bbe91c103de52e92baad9df6d8f9a From 906f5af809df17f97079f46870785175db25494d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 Jul 2019 16:15:09 -0700 Subject: [PATCH 073/160] Don't pull hammer-cad-plugins in init script --- .circleci/check-commit.sh | 1 + scripts/init-submodules-no-riscv-tools.sh | 2 ++ 2 files changed, 3 insertions(+) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index ea7e30f5..bcf4e2ea 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -9,6 +9,7 @@ set -ex cd $HOME/project # initialize submodules and get the hashes +git config submodule.vlsi/hammer-cad-plugins.update none git submodule update --init status=$(git submodule status) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 8bf6b300..99b1b497 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -16,6 +16,8 @@ git config --global submodule.esp-tools.update none git config --global submodule.experimental-blocks.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none +# Disable updates to the hammer-cad-plugins repo +git config submodule.vlsi/hammer-cad-plugins.update none git submodule update --init --recursive #--jobs 8 # unignore riscv-tools,catapult-shell2 globally git config --global --unset submodule.riscv-tools.update From fd5a00a0ab9d2fa8635e6a9566afd6662417c2a3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 15 Jul 2019 10:58:41 -0700 Subject: [PATCH 074/160] rename sim dirs | add "fast" helper target | re-add -q flag --- common.mk | 5 ++++- sims/{vsim => vcs}/.gitignore | 0 sims/{vsim => vcs}/Makefile | 1 + sims/{verisim => verilator}/.gitignore | 0 sims/{verisim => verilator}/Makefile | 0 sims/{verisim => verilator}/verilator.mk | 0 6 files changed, 5 insertions(+), 1 deletion(-) rename sims/{vsim => vcs}/.gitignore (100%) rename sims/{vsim => vcs}/Makefile (99%) rename sims/{verisim => verilator}/.gitignore (100%) rename sims/{verisim => verilator}/Makefile (100%) rename sims/{verisim => verilator}/verilator.mk (100%) diff --git a/common.mk b/common.mk index 5f9d04cb..0c94a669 100644 --- a/common.mk +++ b/common.mk @@ -73,11 +73,14 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) verilog: $(sim_vsrcs) ######################################################################################### -# helper rules to run simulator +# helper rules to run simulations ######################################################################################### +.PHONY: run-binary run-fast run-binary: $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) +run-fast: run-asm-tests-fast run-bmark-tests-fast + ######################################################################################### # run assembly/benchmarks rules ######################################################################################### diff --git a/sims/vsim/.gitignore b/sims/vcs/.gitignore similarity index 100% rename from sims/vsim/.gitignore rename to sims/vcs/.gitignore diff --git a/sims/vsim/Makefile b/sims/vcs/Makefile similarity index 99% rename from sims/vsim/Makefile rename to sims/vcs/Makefile index 88aaed1e..fcf6ed7c 100644 --- a/sims/vsim/Makefile +++ b/sims/vcs/Makefile @@ -54,6 +54,7 @@ VCS_NONCC_OPTS = \ -error=PCWM-L \ -timescale=1ns/10ps \ -quiet \ + -q \ +rad \ +v2k \ +vcs+lic+wait \ diff --git a/sims/verisim/.gitignore b/sims/verilator/.gitignore similarity index 100% rename from sims/verisim/.gitignore rename to sims/verilator/.gitignore diff --git a/sims/verisim/Makefile b/sims/verilator/Makefile similarity index 100% rename from sims/verisim/Makefile rename to sims/verilator/Makefile diff --git a/sims/verisim/verilator.mk b/sims/verilator/verilator.mk similarity index 100% rename from sims/verisim/verilator.mk rename to sims/verilator/verilator.mk From c784fdc658642162a2a7d655bf86a4a03f14b0e2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 15 Jul 2019 16:53:37 -0700 Subject: [PATCH 075/160] rename ci --- .circleci/build-verilator.sh | 2 +- .circleci/config.yml | 28 ++++++++++++++-------------- .circleci/defaults.sh | 4 ++-- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/.circleci/build-verilator.sh b/.circleci/build-verilator.sh index 2c0b6a13..acd038fb 100755 --- a/.circleci/build-verilator.sh +++ b/.circleci/build-verilator.sh @@ -23,7 +23,7 @@ if [ ! -d "$LOCAL_VERILATOR_DIR" ]; then run "mkdir -p $REMOTE_CHIPYARD_DIR" copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR - run "make -C $REMOTE_CHIPYARD_DIR/sims/verisim VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR verilator_install" + run "make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR verilator_install" # copy so that circleci can cache mkdir -p $LOCAL_CHIPYARD_DIR diff --git a/.circleci/config.yml b/.circleci/config.yml index 42397ea8..e03f2a9c 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -78,14 +78,14 @@ jobs: - checkout - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Build Verilator command: | .circleci/build-verilator.sh no_output_timeout: 120m - save_cache: - key: verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + key: verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} paths: - "/home/riscvuser/verilator" prepare-example: @@ -108,7 +108,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the example subproject using Verilator command: .circleci/do-rtl-build.sh example @@ -137,7 +137,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the boomexample subproject using Verilator command: .circleci/do-rtl-build.sh boomexample @@ -166,7 +166,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the boomrocketexample subproject using Verilator command: .circleci/do-rtl-build.sh boomrocketexample @@ -195,7 +195,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the boom subproject using Verilator command: .circleci/do-rtl-build.sh boom @@ -224,7 +224,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the rocketchip subproject using Verilator command: .circleci/do-rtl-build.sh rocketchip @@ -253,7 +253,7 @@ jobs: - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the hwacha subproject using Verilator command: .circleci/do-rtl-build.sh hwacha @@ -282,7 +282,7 @@ jobs: - example-{{ .Branch }}-{{ .Revision }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Run example tests command: .circleci/run-tests.sh example @@ -306,7 +306,7 @@ jobs: - boomexample-{{ .Branch }}-{{ .Revision }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Run boomexample tests command: .circleci/run-tests.sh boomexample @@ -330,7 +330,7 @@ jobs: - boomrocketexample-{{ .Branch }}-{{ .Revision }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Run boomrocketexample tests command: .circleci/run-tests.sh boomrocketexample @@ -354,7 +354,7 @@ jobs: - boom-{{ .Branch }}-{{ .Revision }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Run boom tests command: .circleci/run-tests.sh boom @@ -378,7 +378,7 @@ jobs: - rocketchip-{{ .Branch }}-{{ .Revision }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Run rocketchip tests command: .circleci/run-tests.sh rocketchip @@ -402,7 +402,7 @@ jobs: - hwacha-{{ .Branch }}-{{ .Revision }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Run hwacha tests command: .circleci/run-tests.sh hwacha diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index a17dca78..91b8f589 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -23,7 +23,7 @@ REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_VERILATOR_DIR=$REMOTE_WORK_DIR/verilator -REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verisim +REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator # local variables (aka within the docker container) LOCAL_CHECKOUT_DIR=$HOME/project @@ -31,7 +31,7 @@ LOCAL_RISCV_DIR=$HOME/riscv-tools-install LOCAL_ESP_DIR=$HOME/esp-tools-install LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR LOCAL_VERILATOR_DIR=$HOME/verilator -LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verisim +LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator # key value store to get the build strings declare -A mapping From 02e76f343e57f1ba3d85fdbcbacea1519685ed4c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 15 Jul 2019 17:16:23 -0700 Subject: [PATCH 076/160] remove commit check on firechip --- .circleci/check-commit.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 4ad48ed5..630bbd08 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -26,7 +26,7 @@ search () { done } -submodules=("boom" "firechip" "hwacha" "icenet" "rocket-chip" "sifive-blocks" "sifive-cache" "testchipip") +submodules=("boom" "hwacha" "icenet" "rocket-chip" "sifive-blocks" "sifive-cache" "testchipip") dir="generators" search From 26a67fdbad606fa610bb880a292e566f19eb652f Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Mon, 15 Jul 2019 22:15:57 -0700 Subject: [PATCH 077/160] Add verbose to debug runs (#148) * Add verbose to debug runs * Reorg simulator flags for consistency, extensibility, and ease of use --- common.mk | 18 +++++++++++++++--- sims/verisim/Makefile | 10 +++------- sims/vsim/Makefile | 10 +++------- variables.mk | 3 ++- 4 files changed, 23 insertions(+), 18 deletions(-) diff --git a/common.mk b/common.mk index 5f9d04cb..68a7e632 100644 --- a/common.mk +++ b/common.mk @@ -76,7 +76,19 @@ verilog: $(sim_vsrcs) # helper rules to run simulator ######################################################################################### run-binary: $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + +######################################################################################### +# helper rules to run simulator as fast as possible +######################################################################################### +run-binary-fast: $(sim) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + +######################################################################################### +# helper rules to run simulator with as much debug info as possible +######################################################################################### +run-binary-debug: $(sim_debug) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAG) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) ######################################################################################### # run assembly/benchmarks rules @@ -86,10 +98,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< && touch $@ + $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@) ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 629373c8..801a521c 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -28,6 +28,8 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug PERMISSIVE_ON= PERMISSIVE_OFF= +WAVEFORM_FLAG=-v$(sim_out_name).vcd + .PHONY: default debug default: $(sim) debug: $(sim_debug) @@ -80,19 +82,13 @@ $(sim): $(model_mk) $(sim_debug): $(model_mk_debug) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk -######################################################################################### -# helper rules to run simulator with debug -######################################################################################### -run-binary-debug: $(sim_debug) - (set -o pipefail && $(sim_debug) $(SIM_FLAGS) -v$(sim_out_name).vcd $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) - ######################################################################################### # create a verisim vpd rule ######################################################################################### $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - $(sim_debug) -v$@.vcd +max-cycles=$(timeout_cycles) $< + $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< ######################################################################################### # general cleanup rule diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 88aaed1e..6364d2f8 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -28,6 +28,8 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug PERMISSIVE_ON=+permissive PERMISSIVE_OFF=+permissive-off +WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd + .PHONY: default debug default: $(sim) debug: $(sim_debug) @@ -93,17 +95,11 @@ $(sim_debug) : $(sim_vsrcs) $(sim_dotf) $(sim_vcs_blackboxes) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp -######################################################################################### -# helper rules to run simulator with debug -######################################################################################### -run-binary-debug: $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) - ######################################################################################### # create a vcs vpd rule ######################################################################################### $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - $(sim_debug) $(PERMISSIVE_ON) +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< + $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< ######################################################################################### # general cleanup rule diff --git a/variables.mk b/variables.mk index d9ce7781..7aefdd18 100644 --- a/variables.mk +++ b/variables.mk @@ -148,7 +148,8 @@ output_dir=$(sim_dir)/output/$(long_name) # helper variables to run binaries ######################################################################################### BINARY ?= -SIM_FLAGS ?= +max-cycles=$(timeout_cycles) +SIM_FLAGS ?= +VERBOSE_FLAGS ?= +verbose sim_out_name = $(notdir $(basename $(BINARY))).$(long_name) ######################################################################################### From 870c7d53d32503884c0a229f160bbd7297c4a277 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 16 Jul 2019 07:43:27 -0700 Subject: [PATCH 078/160] Address PR comments for FireSim docs --- .../FPGA-Accelerated-Simulators.rst | 27 +++++++------------ ...lators.rst => Software-RTL-Simulators.rst} | 0 docs/Simulation/index.rst | 4 +-- 3 files changed, 12 insertions(+), 19 deletions(-) rename docs/Simulation/{SW-RTL-Simulators.rst => Software-RTL-Simulators.rst} (100%) diff --git a/docs/Simulation/FPGA-Accelerated-Simulators.rst b/docs/Simulation/FPGA-Accelerated-Simulators.rst index a3bbbe19..6dab6378 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulators.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulators.rst @@ -8,29 +8,26 @@ FireSim FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. FireSim also provides additional device models to allow full-system simulation, including memory models and network models. -FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. +FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances. In order to simulate your Chipyard design using FireSim, if you have not already, follow the initial EC2 setup instructions as detailed in the `FireSim documentation `__. -Then clone your full Chipyard repository onto your Amazon EC2 FireSim manager +Then clone Chipyard onto your FireSim manager instance, and setup your Chipyard repository as you would normally. -When you are ready to use FireSim, initalize it as library in Chipyard by running: +Next, initalize FireSim as library in Chipyard by running: .. code-block:: shell # At the root of your chipyard repo ./scripts/firesim-setup.sh --fast - ``firesim-setup.sh`` initializes additional submodules and then invokes -firesim's ``build-setup.sh`` script. ``firesim-setup.sh`` accepts all of the same arguments and -passes them through to ``build-setup.sh``, adding ``--library`` to properly +firesim's ``build-setup.sh`` script adding ``--library`` to properly initialize FireSim as a library submodule in chipyard. You may run ``./sims/firesim/build-setup.sh --help`` to see more options. -In order to build bitstreams, run simulations, or to generate MIDAS-transformed RTL for your -simulator, you'll need to source one of the following three environments: +Finally, source the following environment at the root of the firesim directory: .. code-block:: shell @@ -38,21 +35,17 @@ simulator, you'll need to source one of the following three environments: # (Recommended) The default manager environment (includes env.sh) source sourceme-f1-manager.sh - # OR A minimal environment to run recipes out of sim/ (to invoke MIDAS; run MIDAS-level RTL simulation)generate RTL; transform At the root of your chipyard repo - source env.sh - - # OR A complete environment to run local FPGA builds with Vivado - source sourceme-f1-full.sh +`Every time you want to use FireSim with a fresh shell, you must source this sourceme.sh` At this point you're ready to use FireSim with Chipyard. If you're not already -familiar with FireSim, please refer to the `FireSim Docs `__, and proceed -through the rest of the tutorial. - +familiar with FireSim, please return to the `FireSim Docs +`__, +and proceed with the rest of the tutorial. Current Limitations: ++++++++++++++++++++ -FireSim integration in chipyard is still a work in progress. Presently, you +FireSim integration in Chipyard is still a work in progress. Presently, you cannot build a FireSim simulator from any generator project in Chipyard except ``firechip``, which properly invokes MIDAS on the target RTL. diff --git a/docs/Simulation/SW-RTL-Simulators.rst b/docs/Simulation/Software-RTL-Simulators.rst similarity index 100% rename from docs/Simulation/SW-RTL-Simulators.rst rename to docs/Simulation/Software-RTL-Simulators.rst diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index f8ff7e46..50dbb57e 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -9,12 +9,12 @@ Chipyard supports two classes of simulation: Software RTL simulators of Chipyard designs run at O(1 KHz), but compile quickly and provide full waveforms. Conversly, FPGA-accelerated simulators run at O(100 MHz), making them appropriate for booting an operating system and -running a complete workload, but have long compile time and poorer debug +running a complete workload, but have multi-hour compile times and poorer debug visability. .. toctree:: :maxdepth: 2 :caption: Simulators: - SW-RTL-Simulators + Software-RTL-Simulators FPGA-Accelerated-Simulators From 3be2241c8a78c04297af972ce5769b00b833fb74 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 16 Jul 2019 11:14:42 -0700 Subject: [PATCH 079/160] toolchain script update --- scripts/build-toolchains.sh | 109 ++++++++++++++++++++++++++++++++++-- sims/firesim | 2 +- 2 files changed, 106 insertions(+), 5 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 20ce4800..40852767 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -1,5 +1,7 @@ #!/usr/bin/env bash +#this script is based on the firesim build toolchains script + # exit script if any command fails set -e set -o pipefail @@ -8,10 +10,70 @@ unamestr=$(uname) RDIR=$(pwd) : ${CHIPYARD_DIR:=$(pwd)} #default value is the PWD unless overridden +function usage +{ + echo "usage: build-setup.sh [ firesim | --firesim] [--submodules-only]" + echo " firesim: if set, pulls in a pre-compiled RISC-V toolchain for an EC2 manager instance" + echo " submodules-only: if set, skips toolchain handling (cloning or building)" +} + +#taken from riscv-tools to check for open-ocd autoconf versions +check_version() { + $1 --version | awk "NR==1 {if (\$NF>$2) {exit 0} exit 1}" || ( + echo $3 requires at least version $2 of $1. Aborting. + exit 1 + ) +} + +if [ "$1" == "--help" -o "$1" == "-h" -o "$1" == "-H" ]; then + usage + exit 3 +fi + +while test $# -gt 0 +do + case "$1" in + firesim | --firesim) # I don't want to break this api + FIRESIMINSTALL=true + ;; + --submodules-only) + SUBMODULES_ONLY=true; + ;; + -h | -H | --help) + usage + exit + ;; + --*) echo "ERROR: bad option $1" + usage + exit 1 + ;; + *) echo "ERROR: bad argument $1" + usage + exit 2 + ;; + esac + shift +done + + if [ $# -ne 0 ]; then TOOLCHAIN=$1 if [ $1 == "riscv" ]; then TOOLCHAIN="riscv-tools" + if [ "$FIRESIMINSTALL" = "true" ]; then + cd sims/firesim/ + git clone https://github.com/firesim/firesim-riscv-tools-prebuilt.git + cd firesim-riscv-tools-prebuilt + git checkout 5fee18421a32058ab339572128201f4904354aaa + PREBUILTHASH="$(cat HASH)" + cd $RDIR/toolchain/riscv-tools/ + GITHASH="git rev-parse HEAD" + cd $RDIR + if [[ "$PREBUILTHASH" == "$GITHASH" && "$FIRESIMINSTALL" == "true" ]]; then + FASTINSTALL=true + #just call a fireism build-toolchain script? + fi + fi elif [ $1 == "hwacha" ]; then TOOLCHAIN="esp-tools" fi @@ -26,12 +88,51 @@ RISCV="$(pwd)/$INSTALL_DIR" # install risc-v tools export RISCV="$RISCV" -git -C $CHIPYARD_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 -cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" -export MAKEFLAGS="-j16" -./build.sh + +if [ "$FASTINSTALL" = true ]; then + cd sims/firesim/firesim-riscv-tools-prebuilt + ./installrelease.sh + mv distrib $(pwd)/$INSTALL_DIR + # copy HASH in case user wants it later + cp HASH $(pwd)/$INSTALL_DIR + cd $RDIR + rm -rf sims/firesim/firesim-riscv-tools-prebuilt +else + git -C $CHIPYARD_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 + cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" + export MAKEFLAGS="-j16" + #build the actual toolchain + #./build.sh + source build.common + echo "Starting RISC-V Toolchain build process" + build_project riscv-fesvr --prefix=$RISCV + build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV + build_project riscv-gnu-toolchain --prefix=$RISCV + CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv64-unknown-elf + build_project riscv-tests --prefix=$RISCV/riscv64-unknown-elf + echo -e "\\nRISC-V Toolchain installation completed!" + + # build static libfesvr library for linking into firesim driver (or others) + cd riscv-fesvr/build + $CHIPYARD_DIR/sims/firesim/scripts/build-static-libfesvr.sh + cd $RDIR + # build linux toolchain + cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN/riscv-gnu-toolchain/build" + make -j16 linux + echo -e "\\nRISC-V Linux GNU Toolchain installation completed!" + + if [ "$FIRESIMINSTALL" = "false" ]; then + check_version automake 1.14 "OpenOCD build" + check_version autoconf 2.64 "OpenOCD build" + build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --disable-werror + echo -e "\\nRISC-V OpenOCD installation completed!" + fi + +fi + cd $RDIR +echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" > env.sh echo "export RISCV=$RISCV" > env.sh echo "export PATH=$RISCV/bin:$RDIR/$DTCversion:\$PATH" >> env.sh echo "export LD_LIBRARY_PATH=$RISCV/lib" >> env.sh diff --git a/sims/firesim b/sims/firesim index 7f8152e5..b0b04d34 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7f8152e5114c7f7793df54a41a53a9e6a04fa8cd +Subproject commit b0b04d343bf252ceb9c495ed7a6f87f30cafa2a3 From 85d904f108d80202a42d80f06e0df18811bd4059 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 12 Jul 2019 13:24:08 -0700 Subject: [PATCH 080/160] add blkdev ci | cleanup simfiles to remove duplicates --- .circleci/config.yml | 34 ++++++++++++++++++++++++++++++++++ .circleci/defaults.sh | 1 + common.mk | 13 +++++++++++-- generators/testchipip | 2 +- sims/verisim/Makefile | 10 +++++----- sims/vsim/Makefile | 17 ++++------------- 6 files changed, 56 insertions(+), 21 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 42397ea8..ab514d36 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -233,6 +233,35 @@ jobs: key: rocketchip-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project" + prepare-blockdevrocketchip: + docker: + - image: riscvboom/riscvboom-images:0.0.10 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + steps: + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" + - checkout + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - restore_cache: + keys: + - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - run: + name: Building the blockdevrocketchip subproject using Verilator + command: .circleci/do-rtl-build.sh blockdevrocketchip + no_output_timeout: 120m + - save_cache: + key: blockdevrocketchip-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project" prepare-hwacha: docker: - image: riscvboom/riscvboom-images:0.0.10 @@ -449,6 +478,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-blockdevrocketchip: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-hwacha: requires: - install-esp-toolchain diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index a17dca78..5427852f 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -40,4 +40,5 @@ mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig" mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig" mapping["boom"]="SUB_PROJECT=boom" mapping["rocketchip"]="SUB_PROJECT=rocketchip" +mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=BlockDeviceModelRocketConfig TOP=BoomRocketTopWithBlockDevice" mapping["hwacha"]="SUB_PROJECT=hwacha" diff --git a/common.mk b/common.mk index 68a7e632..75419e30 100644 --- a/common.mk +++ b/common.mk @@ -53,9 +53,10 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) -$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) +# note: this depends on sim_top_blackboxes to avoid race condition where firrtl_black_box_resource_files.f is created at the same time +$(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)" - grep -v ".*\.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) + cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs MACROCOMPILER_MODE ?= --mode synflops @@ -66,6 +67,14 @@ HARNESS_MACROCOMPILER_MODE = --mode synflops $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" +######################################################################################## +# remove duplicate/*.h files in blackbox/simfiles +######################################################################################## +sim_files ?= $(build_dir)/sim_files.common.f + +$(sim_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_dotf) + awk '{print $1;}' $^ | sort -u | grep -v ".*\.h" > $@ + ######################################################################################### # helper rule to just make verilog files ######################################################################################### diff --git a/generators/testchipip b/generators/testchipip index cd9d53c3..85db33c3 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit cd9d53c3611b075d0cb580e051cb3ae38864148b +Subproject commit 85db33c398c54eba6c979f798e975ad9a29020b4 diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile index 801a521c..2dfd43ba 100644 --- a/sims/verisim/Makefile +++ b/sims/verisim/Makefile @@ -57,19 +57,19 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk ######################################################################################### LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread -$(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) +$(model_mk): $(sim_vsrcs) $(sim_files) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \ - -o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \ + -o $(sim) $(sim_vsrcs) -f $(sim_files) -LDFLAGS "$(LDFLAGS)" \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" touch $@ -$(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) +$(model_mk_debug): $(sim_vsrcs) $(sim_files) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \ - -o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \ + -o $(sim_debug) $(sim_vsrcs) -f $(sim_files) -LDFLAGS "$(LDFLAGS)" \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" touch $@ @@ -95,4 +95,4 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) ######################################################################################### .PHONY: clean clean: - rm -rf $(gen_dir)/* $(sim_prefix)-* + rm -rf $(gen_dir) $(sim_prefix)-* diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile index 6364d2f8..c96155ba 100644 --- a/sims/vsim/Makefile +++ b/sims/vsim/Makefile @@ -60,8 +60,7 @@ VCS_NONCC_OPTS = \ +v2k \ +vcs+lic+wait \ +vc+list \ - -f $(sim_vcs_blackboxes) \ - -f $(sim_dotf) \ + -f $(sim_files) \ -sverilog \ +incdir+$(build_dir) \ +define+CLOCK_PERIOD=1.0 \ @@ -76,22 +75,14 @@ VCS_NONCC_OPTS = \ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) -######################################################################################## -# remove duplicate blackboxes -######################################################################################## -sim_vcs_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.vcs.f - -$(sim_vcs_blackboxes): $(sim_top_blackboxes) $(sim_harness_blackboxes) - awk '{print $1;}' $^ | sort -u > $@ - ######################################################################################### # vcs simulator rules ######################################################################################### -$(sim): $(sim_vsrcs) $(sim_dotf) $(sim_vcs_blackboxes) +$(sim): $(sim_vsrcs) $(sim_files) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug) : $(sim_vsrcs) $(sim_dotf) $(sim_vcs_blackboxes) +$(sim_debug) : $(sim_vsrcs) $(sim_files) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp @@ -106,4 +97,4 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) ######################################################################################### .PHONY: clean clean: - rm -rf $(gen_dir)/* csrc $(sim_prefix)-* ucli.key vc_hdrs.h + rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h From 829687b2547082712065294074f1389bfb298dd2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 16 Jul 2019 11:37:36 -0700 Subject: [PATCH 081/160] move file name to variables.mk --- common.mk | 2 -- variables.mk | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/common.mk b/common.mk index 75419e30..29c2713b 100644 --- a/common.mk +++ b/common.mk @@ -70,8 +70,6 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) ######################################################################################## # remove duplicate/*.h files in blackbox/simfiles ######################################################################################## -sim_files ?= $(build_dir)/sim_files.common.f - $(sim_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_dotf) awk '{print $1;}' $^ | sort -u | grep -v ".*\.h" > $@ diff --git a/variables.mk b/variables.mk index 7aefdd18..06e08136 100644 --- a/variables.mk +++ b/variables.mk @@ -122,6 +122,7 @@ HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir +sim_files ?= $(build_dir)/sim_files.common.f sim_dotf ?= $(build_dir)/sim_files.f sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f From 56488ab1429f50b16ed2536f0e7ac2b91a3d7b6f Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 16 Jul 2019 12:10:17 -0700 Subject: [PATCH 082/160] replace riscv-tools with rocket-tools --- .gitmodules | 6 +++--- toolchains/riscv-tools | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.gitmodules b/.gitmodules index ca80d661..55e8a98b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,9 +13,6 @@ [submodule "tools/firrtl"] path = tools/firrtl url = https://github.com/freechipsproject/firrtl -[submodule "riscv-tools"] - path = toolchains/riscv-tools - url = https://github.com/riscv/riscv-tools.git [submodule "esp-tools"] path = toolchains/esp-tools url = https://github.com/ucb-bar/esp-tools.git @@ -40,3 +37,6 @@ [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache url = https://github.com/sifive/block-inclusivecache-sifive.git +[submodule "toolchains/riscv-tools"] + path = toolchains/riscv-tools + url = https://github.com/freechipsproject/rocket-tools.git diff --git a/toolchains/riscv-tools b/toolchains/riscv-tools index bce7b5e3..190bb6ba 160000 --- a/toolchains/riscv-tools +++ b/toolchains/riscv-tools @@ -1 +1 @@ -Subproject commit bce7b5e363957c134f944769e677354467b7e4ed +Subproject commit 190bb6badf53673f29611796fa29a8ba7a37f002 From f28174f64188d7e733f691bbedfdc84b7045149b Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 16 Jul 2019 21:32:13 +0000 Subject: [PATCH 083/160] move riscv-tools before fesvr merge --- toolchains/riscv-tools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/riscv-tools b/toolchains/riscv-tools index 190bb6ba..bce7b5e3 160000 --- a/toolchains/riscv-tools +++ b/toolchains/riscv-tools @@ -1 +1 @@ -Subproject commit 190bb6badf53673f29611796fa29a8ba7a37f002 +Subproject commit bce7b5e363957c134f944769e677354467b7e4ed From c6a5a333088457cf55eedc31043e8f0f5f8ce08f Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 16 Jul 2019 15:03:28 -0700 Subject: [PATCH 084/160] Update README.md with proper CI/readthedocs links --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index e59f5af5..fd6e723f 100644 --- a/README.md +++ b/README.md @@ -1,8 +1,8 @@ -# Chipyard Framework [![CircleCI](https://circleci.com/gh/ucb-bar/project-template/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/chipyard/tree/master) +# Chipyard Framework [![CircleCI](https://circleci.com/gh/ucb-bar/chipyard/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/chipyard/tree/master) ## Using Chipyard -To get started using Chipyard, see the documentation on the Chipyard documentation site: https://bar-project-template.readthedocs.io/en/latest/ +To get started using Chipyard, see the documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/en/latest/ ## What is Chipyard @@ -14,7 +14,7 @@ Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb ## Resources * Chipyard Website: ...TBD at a later date... -* Chipyard Documentation: https://bar-project-template.readthedocs.io/ +* Chipyard Documentation: https://chipyard.readthedocs.io/ [hwacha]:http://hwacha.org [hammer]:https://github.com/ucb-bar/hammer From d5f9f1e94e666895dfa58d6dfacc0201c4d6eef5 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 16 Jul 2019 15:26:44 -0700 Subject: [PATCH 085/160] Make verilator wget safe --- sims/verilator/verilator.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/verilator/verilator.mk b/sims/verilator/verilator.mk index 80abd869..9954aa4d 100644 --- a/sims/verilator/verilator.mk +++ b/sims/verilator/verilator.mk @@ -36,7 +36,7 @@ $(VERILATOR_SRCDIR)/configure: $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VE $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz: mkdir -p $(dir $@) - wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ + wget https://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ ######################################################################################### # verilator binary and flags From b74aff9ba8713bf1e4caa4742d2f36832fe536d4 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 16 Jul 2019 23:09:23 +0000 Subject: [PATCH 086/160] toolchain script fixes --- scripts/build-toolchains.sh | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 40852767..fad50914 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -12,9 +12,10 @@ RDIR=$(pwd) function usage { - echo "usage: build-setup.sh [ firesim | --firesim] [--submodules-only]" + echo "usage: ./scripts/build-toolchains.sh [riscv] [hwacha] [ firesim | --firesim] [--submodules-only]" + echo " riscv: if set, builds the riscv toolchain (this is also the default)" + echo " hwacha: if set, builds esp-tools toolchain" echo " firesim: if set, pulls in a pre-compiled RISC-V toolchain for an EC2 manager instance" - echo " submodules-only: if set, skips toolchain handling (cloning or building)" } #taken from riscv-tools to check for open-ocd autoconf versions @@ -30,15 +31,20 @@ if [ "$1" == "--help" -o "$1" == "-h" -o "$1" == "-H" ]; then exit 3 fi +TOOLCHAIN="riscv-tools" +FIRESIMINSTALL="false" while test $# -gt 0 do case "$1" in + riscv) + TOOLCHAIN="riscv-tools" + ;; + hwacha) + TOOLCHAIN="esp-tools" + ;; firesim | --firesim) # I don't want to break this api FIRESIMINSTALL=true ;; - --submodules-only) - SUBMODULES_ONLY=true; - ;; -h | -H | --help) usage exit @@ -55,11 +61,7 @@ do shift done - -if [ $# -ne 0 ]; then - TOOLCHAIN=$1 - if [ $1 == "riscv" ]; then - TOOLCHAIN="riscv-tools" +if [ "TOOLCHAINS" = "riscv-tools" ]; then if [ "$FIRESIMINSTALL" = "true" ]; then cd sims/firesim/ git clone https://github.com/firesim/firesim-riscv-tools-prebuilt.git @@ -74,11 +76,6 @@ if [ $# -ne 0 ]; then #just call a fireism build-toolchain script? fi fi - elif [ $1 == "hwacha" ]; then - TOOLCHAIN="esp-tools" - fi -else - TOOLCHAIN="riscv-tools" fi INSTALL_DIR="$TOOLCHAIN-install" From 160dbd263693814264c0b92df3d9c7643d3a7162 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 17 Jul 2019 01:54:55 +0000 Subject: [PATCH 087/160] fix env.sh --- scripts/build-toolchains.sh | 21 +++++++++++++-------- sims/firesim | 2 +- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index fad50914..69923c00 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -33,6 +33,7 @@ fi TOOLCHAIN="riscv-tools" FIRESIMINSTALL="false" +FASTINSTALL="false" while test $# -gt 0 do case "$1" in @@ -118,19 +119,23 @@ else make -j16 linux echo -e "\\nRISC-V Linux GNU Toolchain installation completed!" - if [ "$FIRESIMINSTALL" = "false" ]; then - check_version automake 1.14 "OpenOCD build" - check_version autoconf 2.64 "OpenOCD build" - build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --disable-werror - echo -e "\\nRISC-V OpenOCD installation completed!" - fi - fi cd $RDIR echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" > env.sh -echo "export RISCV=$RISCV" > env.sh +echo "export RISCV=$RISCV" >> env.sh echo "export PATH=$RISCV/bin:$RDIR/$DTCversion:\$PATH" >> env.sh echo "export LD_LIBRARY_PATH=$RISCV/lib" >> env.sh echo "Toolchain Build Complete!" + + +if [ "$FASTINSTALL" = "false" ]; then + if [ "$FIRESIMINSTALL" = "false" ]; then + echo "Building RISC-V OpenOCD Complete!" + check_version automake 1.14 "OpenOCD build" + check_version autoconf 2.64 "OpenOCD build" + build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --disable-werror + echo -e "\\nRISC-V OpenOCD installation completed!" + fi +fi diff --git a/sims/firesim b/sims/firesim index b0b04d34..08409e85 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit b0b04d343bf252ceb9c495ed7a6f87f30cafa2a3 +Subproject commit 08409e85ac2ee9f6de672e1785b1414857091117 From b0b407880185b99b30e19a74e7f96c5efe0e07b5 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 16 Jul 2019 18:55:44 -0700 Subject: [PATCH 088/160] rename files | only remove .h on blackbox files --- common.mk | 24 ++++++++++++------------ sims/vcs/Makefile | 6 +++--- sims/verilator/Makefile | 21 +++++++++++++++------ sims/verilator/verilator.mk | 5 +++-- variables.mk | 32 ++++++++++++++++++-------------- 5 files changed, 51 insertions(+), 37 deletions(-) diff --git a/common.mk b/common.mk index cc2469a7..fe0cb023 100644 --- a/common.mk +++ b/common.mk @@ -33,45 +33,45 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala) ######################################################################################### # create simulation args file rule ######################################################################################### -$(sim_dotf): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR) +$(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" ######################################################################################### # create firrtl file rule and variables ######################################################################################### -$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) +$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_files) mkdir -p $(build_dir) cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" ######################################################################################### # create verilog files rules and variables ######################################################################################### -REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) +REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF) HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF) -$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" - cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) +$(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(TOP_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" + grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_top_blackboxes) # note: this depends on sim_top_blackboxes to avoid race condition where firrtl_black_box_resource_files.f is created at the same time $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)" - cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_harness_blackboxes) + grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs MACROCOMPILER_MODE ?= --mode synflops -$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) - cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)" +$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR): $(TOP_SMEMS_CONF) + cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)" HARNESS_MACROCOMPILER_MODE = --mode synflops $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" ######################################################################################## -# remove duplicate/*.h files in blackbox/simfiles +# remove duplicate files in blackbox/simfiles ######################################################################################## -$(sim_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_dotf) - awk '{print $1;}' $^ | sort -u | grep -v ".*\.h" > $@ +$(sim_common_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_files) + awk '{print $1;}' $^ | sort -u > $@ ######################################################################################### # helper rule to just make verilog files diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 8f0ebbe0..fa05531f 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -61,7 +61,7 @@ VCS_NONCC_OPTS = \ +v2k \ +vcs+lic+wait \ +vc+list \ - -f $(sim_files) \ + -f $(sim_common_files) \ -sverilog \ +incdir+$(build_dir) \ +define+CLOCK_PERIOD=1.0 \ @@ -79,11 +79,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) ######################################################################################### # vcs simulator rules ######################################################################################### -$(sim): $(sim_vsrcs) $(sim_files) +$(sim): $(sim_vsrcs) $(sim_common_files) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug) : $(sim_vsrcs) $(sim_files) +$(sim_debug) : $(sim_vsrcs) $(sim_common_files) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 2dfd43ba..3edbc953 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -56,20 +56,29 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk # build makefile fragment that builds the verilator sim rules ######################################################################################### LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread +SHARED_FLAGS := \ + $(sim_vsrcs) \ + -f $(sim_common_files) \ + -LDFLAGS "$(LDFLAGS)" -$(model_mk): $(sim_vsrcs) $(sim_files) $(INSTALLED_VERILATOR) +$(model_mk): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) - $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \ - -o $(sim) $(sim_vsrcs) -f $(sim_files) -LDFLAGS "$(LDFLAGS)" \ + $(VERILATOR) $(VERILATOR_FLAGS) \ + -Mdir $(build_dir)/$(long_name) \ + -o $(sim) \ + $(SHARED_FLAGS) \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" touch $@ -$(model_mk_debug): $(sim_vsrcs) $(sim_files) $(INSTALLED_VERILATOR) +$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug - $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \ - -o $(sim_debug) $(sim_vsrcs) -f $(sim_files) -LDFLAGS "$(LDFLAGS)" \ + $(VERILATOR) $(VERILATOR_FLAGS) \ + -Mdir $(build_dir)/$(long_name).debug \ + --trace \ + -o $(sim_debug) \ + $(SHARED_FLAGS) \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" touch $@ diff --git a/sims/verilator/verilator.mk b/sims/verilator/verilator.mk index 80abd869..382715ca 100644 --- a/sims/verilator/verilator.mk +++ b/sims/verilator/verilator.mk @@ -6,7 +6,7 @@ # verilator version, binary, and path ######################################################################################### VERILATOR_VERSION = 4.016 -VERILATOR_INSTALL_DIR ?= verilator +VERILATOR_INSTALL_DIR ?= verilator_install VERILATOR_SRCDIR = $(VERILATOR_INSTALL_DIR)/src/verilator-$(VERILATOR_VERSION) INSTALLED_VERILATOR = $(abspath $(VERILATOR_INSTALL_DIR)/install/bin/verilator) @@ -45,7 +45,8 @@ VERILATOR := $(INSTALLED_VERILATOR) --cc --exe CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS VERILATOR_FLAGS := --top-module $(VLOG_MODEL) \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ + +define+STOP_COND=\$$c\(\"done_reset\"\) \ + --assert \ --output-split 20000 \ -Wno-STMTDLY --x-assign unique \ -O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" diff --git a/variables.mk b/variables.mk index 06e08136..f0bdf634 100644 --- a/variables.mk +++ b/variables.mk @@ -108,24 +108,28 @@ ifeq ($(GENERATOR_PACKAGE),hwacha) long_name=$(MODEL_PACKAGE).$(CONFIG) endif -FIRRTL_FILE ?= $(build_dir)/$(long_name).fir -ANNO_FILE ?= $(build_dir)/$(long_name).anno.json -VERILOG_FILE ?= $(build_dir)/$(long_name).top.v -TOP_FIR ?= $(build_dir)/$(long_name).top.fir -TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json +FIRRTL_FILE ?= $(build_dir)/$(long_name).fir +ANNO_FILE ?= $(build_dir)/$(long_name).anno.json + +TOP_FILE ?= $(build_dir)/$(long_name).top.v +TOP_FIR ?= $(build_dir)/$(long_name).top.fir +TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json +TOP_SMEMS_FILE ?= $(build_dir)/$(long_name).top.mems.v +TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf +TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir + HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir -SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v -SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf -SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir -sim_files ?= $(build_dir)/sim_files.common.f -sim_dotf ?= $(build_dir)/sim_files.f -sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f -sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f + +sim_files ?= $(build_dir)/sim_files.f +sim_files ?= $(build_dir)/sim_files.f +sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f +sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f +sim_common_files ?= $(build_dir)/sim_files.common.f ######################################################################################### # java arguments used in sbt @@ -168,9 +172,9 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc # sources needed to run simulators ######################################################################################### sim_vsrcs = \ - $(VERILOG_FILE) \ + $(TOP_FILE) \ $(HARNESS_FILE) \ - $(SMEMS_FILE) \ + $(TOP_SMEMS_FILE) \ $(HARNESS_SMEMS_FILE) ######################################################################################### From 52f959f457b3458be356070538df61351f0b9f87 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 16 Jul 2019 18:57:57 -0700 Subject: [PATCH 089/160] remove duplicate line --- variables.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/variables.mk b/variables.mk index f0bdf634..a0c6a9af 100644 --- a/variables.mk +++ b/variables.mk @@ -125,7 +125,6 @@ HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir -sim_files ?= $(build_dir)/sim_files.f sim_files ?= $(build_dir)/sim_files.f sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f From d3a3c9bc16e696237a5f05608829725d45be6bad Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 17 Jul 2019 03:33:52 +0000 Subject: [PATCH 090/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 08409e85..4cad8b72 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 08409e85ac2ee9f6de672e1785b1414857091117 +Subproject commit 4cad8b72b4edbd83d782c8b09a5f18a18b09e74c From 44f2c594da80519405bdb1c38bbea0f1b491c1d6 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 17 Jul 2019 03:59:57 +0000 Subject: [PATCH 091/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 4cad8b72..21c8a5e5 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4cad8b72b4edbd83d782c8b09a5f18a18b09e74c +Subproject commit 21c8a5e5f1e5f329232473380b067d9d5a8e0f8c From b7bc96b6d659fb2863a20137fa05528c0ea82f20 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 16 Jul 2019 21:36:36 -0700 Subject: [PATCH 092/160] rename missing vcs/verilator names | fix ci path --- .circleci/config.yml | 2 +- .circleci/do-rtl-build.sh | 2 +- .../Adding-An-Accelerator-Tutorial.rst | 2 +- docs/Getting-Started/Chipyard-Basics.rst | 8 ++--- docs/Getting-Started/Running-A-Simulation.rst | 8 ++--- docs/Simulation/Software-RTL-Simulators.rst | 4 +-- scripts/regression.sh | 31 ------------------- sims/verilator/Makefile | 2 +- 8 files changed, 14 insertions(+), 45 deletions(-) delete mode 100755 scripts/regression.sh diff --git a/.circleci/config.yml b/.circleci/config.yml index 4630446d..db4eb614 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -253,7 +253,7 @@ jobs: - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verisim/verilator.mk" }} + - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Building the blockdevrocketchip subproject using Verilator command: .circleci/do-rtl-build.sh blockdevrocketchip diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 2c7242cc..00dc7290 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -39,7 +39,7 @@ else copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR fi -# enter the verisim directory and build the specific config on remote server +# enter the verilator directory and build the specific config on remote server run "make -C $REMOTE_SIM_DIR clean" run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" ${mapping[$1]}" run "rm -rf $REMOTE_CHIPYARD_DIR/project" diff --git a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst index 4eefe9b8..4edbde1b 100644 --- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst +++ b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst @@ -227,7 +227,7 @@ Now with all of that done, we can go ahead and run our simulation. .. code-block:: shell - cd verisim + cd verilator make CONFIG=PWMConfig ./simulator-example-PWMConfig ../tests/pwm.riscv diff --git a/docs/Getting-Started/Chipyard-Basics.rst b/docs/Getting-Started/Chipyard-Basics.rst index 7b9f1bbe..c5aa5a62 100644 --- a/docs/Getting-Started/Chipyard-Basics.rst +++ b/docs/Getting-Started/Chipyard-Basics.rst @@ -81,14 +81,14 @@ Toolchains Sims ------------------------------------------- -**verisim (Verilator wrapper)** +**verilator (Verilator wrapper)** Verilator is an open source Verilog simulator. - The ``verisim`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). + The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). See :ref:`Verilator` for more information. -**vsim (VCS wrapper)** +**vcs (VCS wrapper)** VCS is a proprietary Verilog simulator. - Assuming the user has valid VCS licenses and installations, the ``vsim`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). + Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). See :ref:`VCS` for more information. **FireSim** diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index 0cc4a024..39128f30 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -15,9 +15,9 @@ The following instructions assume at least one of these simulators is installed. Verilator/VCS Flows ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Verilator is an open-source RTL simulator. -We run Verilator simulations from within the ``sims/verisim`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations. +We run Verilator simulations from within the ``sims/verilator`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations. On the other hand, VCS is a proprietary RTL simulator. -We run VCS simulations from within the ``sims/vsim`` directory. +We run VCS simulations from within the ``sims/vcs`` directory. Assuming VCS is already installed on the machine running simulations (and is found on our ``PATH``), then this guide is the same for both Verilator and VCS. First, we will start by entering the Verilator or VCS directory: @@ -25,12 +25,12 @@ First, we will start by entering the Verilator or VCS directory: .. code-block:: shell # Enter Verilator directory - cd sims/verisim + cd sims/verilator # OR # Enter VCS directory - cd sims/vsim + cd sims/vcs In order to construct the simulator with our custom design, we run the following command within the simulator directory: diff --git a/docs/Simulation/Software-RTL-Simulators.rst b/docs/Simulation/Software-RTL-Simulators.rst index 9df94d52..cef1b1f3 100644 --- a/docs/Simulation/Software-RTL-Simulators.rst +++ b/docs/Simulation/Software-RTL-Simulators.rst @@ -9,7 +9,7 @@ The Chipyard framework can download, build, and execute simulations using Verila To run a simulation using Verilator, perform the following steps: -To compile the example design, run ``make`` in the ``sims/verisim`` directory. +To compile the example design, run ``make`` in the ``sims/verilator`` directory. This will elaborate the ``DefaultRocketConfig`` in the example project. An executable called ``simulator-example-DefaultRocketConfig`` will be produced. @@ -47,7 +47,7 @@ To run a simulation using VCS, perform the following steps: Make sure that the VCS simulator is on your ``PATH``. -To compile the example design, run make in the ``sims/vsim`` directory. +To compile the example design, run make in the ``sims/vcs`` directory. This will elaborate the ``DefaultRocketConfig`` in the example project. An executable called ``simulator-example-DefaultRocketConfig`` will be produced. diff --git a/scripts/regression.sh b/scripts/regression.sh deleted file mode 100755 index 3175891c..00000000 --- a/scripts/regression.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/bash - -# NOTE: TEMPORARY UNTIL CI IS ONLINE - -# Run by just giving the test to run (run-bmark-tests | run-asm-tests) -# Runs in vsim and verisim - -set -ex -set -euo pipefail - -cd sims/vsim/ - -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 -make SUB_PROJECT=boom CONFIG=BoomConfig -make SUB_PROJECT=boom CONFIG=BoomConfig $1 -make SUB_PROJECT=example CONFIG=DefaultRocketConfig -make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 -make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig -make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 - -cd ../verisim/ - -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig -make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1 -make SUB_PROJECT=boom CONFIG=BoomConfig -make SUB_PROJECT=boom CONFIG=BoomConfig $1 -make SUB_PROJECT=example CONFIG=DefaultRocketConfig -make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1 -make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig -make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1 diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 3edbc953..c97f9844 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -92,7 +92,7 @@ $(sim_debug): $(model_mk_debug) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk ######################################################################################### -# create a verisim vpd rule +# create a verilator vpd rule ######################################################################################### $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd From baf3753b91f6d205eb1d13d0b16b1522d64cdca9 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 17 Jul 2019 07:08:27 +0000 Subject: [PATCH 093/160] update pre-compiled hash --- scripts/build-toolchains.sh | 4 ++-- sims/firesim | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 69923c00..ec2e31b9 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -62,12 +62,12 @@ do shift done -if [ "TOOLCHAINS" = "riscv-tools" ]; then +if [ "$TOOLCHAINS" = "riscv-tools" ]; then if [ "$FIRESIMINSTALL" = "true" ]; then cd sims/firesim/ git clone https://github.com/firesim/firesim-riscv-tools-prebuilt.git cd firesim-riscv-tools-prebuilt - git checkout 5fee18421a32058ab339572128201f4904354aaa + git checkout 56a40961c98db5e8f904f15dc6efd0870bfefd9e PREBUILTHASH="$(cat HASH)" cd $RDIR/toolchain/riscv-tools/ GITHASH="git rev-parse HEAD" diff --git a/sims/firesim b/sims/firesim index 21c8a5e5..fe20b389 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 21c8a5e5f1e5f329232473380b067d9d5a8e0f8c +Subproject commit fe20b389a9c19ae672500868e850e84fd8671fca From 1bb86cfffe36a31422efcfe2e7946cf151d5c30f Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Jul 2019 09:49:12 -0700 Subject: [PATCH 094/160] updated boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 84879571..51bfc070 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 848795715f721b6a88887283179176474a1496b8 +Subproject commit 51bfc070e8b4750f5401b5db235233421ab8deba From 5cedeea35204188deedc446124d0ed04ecd982e3 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 17 Jul 2019 11:45:32 -0700 Subject: [PATCH 095/160] model verilator args after vcs make --- sims/verilator/Makefile | 47 +++++++++++++++++++++++-------------- sims/verilator/verilator.mk | 13 ---------- 2 files changed, 29 insertions(+), 31 deletions(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index c97f9844..d717aa63 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -40,6 +40,31 @@ debug: $(sim_debug) include $(base_dir)/common.mk include $(sim_dir)/verilator.mk +######################################################################################### +# verilator binary and flags +######################################################################################### +VERILATOR := $(INSTALLED_VERILATOR) --cc --exe + +CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS +LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread + +VERILATOR_CC_OPTS = \ + -O3 \ + -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \ + -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs" \ + -LDFLAGS "$(LDFLAGS)" + +VERILATOR_NONCC_OPTS = \ + --top-module $(VLOG_MODEL) \ + +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ + +define+STOP_COND=\$$c\(\"done_reset\"\) \ + --assert \ + --output-split 20000 \ + $(sim_vsrcs) \ + -f $(sim_common_files) + +VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) + ######################################################################################### # verilator build paths and file names ######################################################################################### @@ -55,41 +80,27 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules ######################################################################################### -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread -SHARED_FLAGS := \ - $(sim_vsrcs) \ - -f $(sim_common_files) \ - -LDFLAGS "$(LDFLAGS)" $(model_mk): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) - $(VERILATOR) $(VERILATOR_FLAGS) \ - -Mdir $(build_dir)/$(long_name) \ - -o $(sim) \ - $(SHARED_FLAGS) \ - -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" + $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug - $(VERILATOR) $(VERILATOR_FLAGS) \ - -Mdir $(build_dir)/$(long_name).debug \ - --trace \ - -o $(sim_debug) \ - $(SHARED_FLAGS) \ - -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" + $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ ######################################################################################### # invoke make to make verilator sim rules ######################################################################################### $(sim): $(model_mk) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(VLOG_MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk $(sim_debug): $(model_mk_debug) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk ######################################################################################### # create a verilator vpd rule diff --git a/sims/verilator/verilator.mk b/sims/verilator/verilator.mk index 382715ca..7f8a8c46 100644 --- a/sims/verilator/verilator.mk +++ b/sims/verilator/verilator.mk @@ -37,16 +37,3 @@ $(VERILATOR_SRCDIR)/configure: $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VE $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz: mkdir -p $(dir $@) wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ - -######################################################################################### -# verilator binary and flags -######################################################################################### -VERILATOR := $(INSTALLED_VERILATOR) --cc --exe -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS -VERILATOR_FLAGS := --top-module $(VLOG_MODEL) \ - +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) \ - --assert \ - --output-split 20000 \ - -Wno-STMTDLY --x-assign unique \ - -O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" From 89f1271734c259318e712355cbd86d17c9b7a48f Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 17 Jul 2019 21:47:02 +0000 Subject: [PATCH 096/160] typo fix --- scripts/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index ec2e31b9..74c12938 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -62,7 +62,7 @@ do shift done -if [ "$TOOLCHAINS" = "riscv-tools" ]; then +if [ "$TOOLCHAIN" = "riscv-tools" ]; then if [ "$FIRESIMINSTALL" = "true" ]; then cd sims/firesim/ git clone https://github.com/firesim/firesim-riscv-tools-prebuilt.git From 9976bc192acd20e86efcb93b471d88de2f6a335d Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 17 Jul 2019 22:17:24 +0000 Subject: [PATCH 097/160] more typos --- scripts/build-toolchains.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 74c12938..4a8a5d89 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -69,10 +69,10 @@ if [ "$TOOLCHAIN" = "riscv-tools" ]; then cd firesim-riscv-tools-prebuilt git checkout 56a40961c98db5e8f904f15dc6efd0870bfefd9e PREBUILTHASH="$(cat HASH)" - cd $RDIR/toolchain/riscv-tools/ - GITHASH="git rev-parse HEAD" + cd $RDIR/toolchains/riscv-tools/ + GITHASH="$(git rev-parse HEAD)" cd $RDIR - if [[ "$PREBUILTHASH" == "$GITHASH" && "$FIRESIMINSTALL" == "true" ]]; then + if [[ $PREBUILTHASH == $GITHASH && "$FIRESIMINSTALL" == "true" ]]; then FASTINSTALL=true #just call a fireism build-toolchain script? fi From f97beed12d836e6e9e509321c8b8e63540c870e8 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 17 Jul 2019 15:31:03 -0700 Subject: [PATCH 098/160] Add phony targets --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index fe0cb023..f9d5896b 100644 --- a/common.mk +++ b/common.mk @@ -82,7 +82,7 @@ verilog: $(sim_vsrcs) ######################################################################################### # helper rules to run simulations ######################################################################################### -.PHONY: run-binary run-fast +.PHONY: run-binary run-binary-fast run-binary-debug run-fast run-binary: $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) From fdb21fc6039e57de88f4c6fe195403bef69d0a8d Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 00:57:24 +0000 Subject: [PATCH 099/160] pull toolchain from firesim --- scripts/build-toolchains.sh | 32 ++++++++++++++++++++++---------- sims/firesim | 2 +- 2 files changed, 23 insertions(+), 11 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 4a8a5d89..e2f741b5 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -15,7 +15,7 @@ function usage echo "usage: ./scripts/build-toolchains.sh [riscv] [hwacha] [ firesim | --firesim] [--submodules-only]" echo " riscv: if set, builds the riscv toolchain (this is also the default)" echo " hwacha: if set, builds esp-tools toolchain" - echo " firesim: if set, pulls in a pre-compiled RISC-V toolchain for an EC2 manager instance" + echo " ec2fast: if set, pulls in a pre-compiled RISC-V toolchain for an EC2 manager instance" } #taken from riscv-tools to check for open-ocd autoconf versions @@ -33,6 +33,7 @@ fi TOOLCHAIN="riscv-tools" FIRESIMINSTALL="false" +EC2FASTINSTALL="false" FASTINSTALL="false" while test $# -gt 0 do @@ -46,6 +47,9 @@ do firesim | --firesim) # I don't want to break this api FIRESIMINSTALL=true ;; + ec2fast | --ec2fast) # I don't want to break this api + EC2FASTINSTALL=true + ;; -h | -H | --help) usage exit @@ -62,9 +66,9 @@ do shift done -if [ "$TOOLCHAIN" = "riscv-tools" ]; then - if [ "$FIRESIMINSTALL" = "true" ]; then - cd sims/firesim/ +if [ "$EC2FASTINSTALL" = "true" ]; then + if [ "$TOOLCHAIN" = "riscv-tools" ]; then + cd $RDIR git clone https://github.com/firesim/firesim-riscv-tools-prebuilt.git cd firesim-riscv-tools-prebuilt git checkout 56a40961c98db5e8f904f15dc6efd0870bfefd9e @@ -72,10 +76,18 @@ if [ "$TOOLCHAIN" = "riscv-tools" ]; then cd $RDIR/toolchains/riscv-tools/ GITHASH="$(git rev-parse HEAD)" cd $RDIR - if [[ $PREBUILTHASH == $GITHASH && "$FIRESIMINSTALL" == "true" ]]; then + echo "prebuilt hash: $PREBUILTHASH" + echo "git hash: $GITHASH" + if [[ $PREBUILTHASH == $GITHASH && "$EC2FASTINSTALL" == "true" ]]; then FASTINSTALL=true - #just call a fireism build-toolchain script? + echo "Using fast pre-compiled install for riscv-tools" + else + echo "Error: hash of precompiled toolchain doesn't match the riscv-tools submodule hash." + exit fi + else + echo "Error: No precompiled toolchain for esp-tools or other non-native riscv-tools." + exit fi fi @@ -88,13 +100,13 @@ RISCV="$(pwd)/$INSTALL_DIR" export RISCV="$RISCV" if [ "$FASTINSTALL" = true ]; then - cd sims/firesim/firesim-riscv-tools-prebuilt + cd firesim-riscv-tools-prebuilt ./installrelease.sh - mv distrib $(pwd)/$INSTALL_DIR + mv distrib $RISCV # copy HASH in case user wants it later - cp HASH $(pwd)/$INSTALL_DIR + cp HASH $RISCV cd $RDIR - rm -rf sims/firesim/firesim-riscv-tools-prebuilt + rm -rf firesim-riscv-tools-prebuilt else git -C $CHIPYARD_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" diff --git a/sims/firesim b/sims/firesim index fe20b389..bb6c51a7 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit fe20b389a9c19ae672500868e850e84fd8671fca +Subproject commit bb6c51a788ba1b947afc159a0f032bfcf8cb7fa5 From f331ec13d0519e3ffb313d30f4ca0f3376255e48 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 01:38:44 +0000 Subject: [PATCH 100/160] move libfesvr script --- scripts/build-toolchains.sh | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index e2f741b5..7bdeb5b6 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -124,7 +124,7 @@ else # build static libfesvr library for linking into firesim driver (or others) cd riscv-fesvr/build - $CHIPYARD_DIR/sims/firesim/scripts/build-static-libfesvr.sh + $CHIPYARD_DIR/scripts/build-static-libfesvr.sh cd $RDIR # build linux toolchain cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN/riscv-gnu-toolchain/build" diff --git a/sims/firesim b/sims/firesim index bb6c51a7..c2e1ad83 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit bb6c51a788ba1b947afc159a0f032bfcf8cb7fa5 +Subproject commit c2e1ad830a3cce9e6dc97adf041e6b566330d7c9 From ac23632ef18746838d4ddcec2a6f193c560c1a57 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 02:23:23 +0000 Subject: [PATCH 101/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index c2e1ad83..565ab98b 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c2e1ad830a3cce9e6dc97adf041e6b566330d7c9 +Subproject commit 565ab98ba690586bf27fe9b2dddc8ab851d93e40 From 9e8eed8db471403549ba332d9c1ac662524152d6 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 02:26:42 +0000 Subject: [PATCH 102/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 565ab98b..0e80ba73 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 565ab98ba690586bf27fe9b2dddc8ab851d93e40 +Subproject commit 0e80ba734e87435a8c6c6d445e83e2c896195134 From 171923d3b60efc9b6acb5b448ee791b53380bbf4 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 02:52:54 +0000 Subject: [PATCH 103/160] fix path --- scripts/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 7bdeb5b6..d75d50ec 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -73,7 +73,7 @@ if [ "$EC2FASTINSTALL" = "true" ]; then cd firesim-riscv-tools-prebuilt git checkout 56a40961c98db5e8f904f15dc6efd0870bfefd9e PREBUILTHASH="$(cat HASH)" - cd $RDIR/toolchains/riscv-tools/ + cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" GITHASH="$(git rev-parse HEAD)" cd $RDIR echo "prebuilt hash: $PREBUILTHASH" From 955903759e0ef00e87fabc90db7b38c89477c7a5 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 03:13:59 +0000 Subject: [PATCH 104/160] add firesim chipyard path --- scripts/build-toolchains.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index d75d50ec..0ba5117f 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -66,6 +66,10 @@ do shift done +if [ "$FIRESIMINSTALL" = "true" ]; then + CHIPYARD_DIR="$RDIR/target-design/chipyard" +fi + if [ "$EC2FASTINSTALL" = "true" ]; then if [ "$TOOLCHAIN" = "riscv-tools" ]; then cd $RDIR From eba7b4ec165529f9ad83e52ae20aa0bb7a356e8b Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 03:28:22 +0000 Subject: [PATCH 105/160] correct libfesvr script --- scripts/build-static-libfesvr.sh | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100755 scripts/build-static-libfesvr.sh diff --git a/scripts/build-static-libfesvr.sh b/scripts/build-static-libfesvr.sh new file mode 100755 index 00000000..5dc0eac3 --- /dev/null +++ b/scripts/build-static-libfesvr.sh @@ -0,0 +1,17 @@ +#!/bin/bash + +# This ungodly script surreptitiously builds an archive from existing fesvr objects +# Invoke from riscv-fesvr/build + +if [ "x$RISCV" = "x" ] +then + echo "Please set the RISCV environment variable to your preferred install path." + exit 1 +fi + +set -e + +objs=$(head -n 1 <(make -f <( echo -e 'include Makefile\n$(info $(value fesvr_objs))') -n)) +ar rcs -o libfesvr.a $objs +cp -f libfesvr.a $RISCV/lib + From 9fa1d8d971a5d0a634356163a00c77381dc34a9d Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 04:12:41 +0000 Subject: [PATCH 106/160] update arg --- scripts/build-toolchains.sh | 4 ---- 1 file changed, 4 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 0ba5117f..d75d50ec 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -66,10 +66,6 @@ do shift done -if [ "$FIRESIMINSTALL" = "true" ]; then - CHIPYARD_DIR="$RDIR/target-design/chipyard" -fi - if [ "$EC2FASTINSTALL" = "true" ]; then if [ "$TOOLCHAIN" = "riscv-tools" ]; then cd $RDIR From d7d25fb840bb0d49f25bcc13e2b136baf05bd68c Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 04:14:11 +0000 Subject: [PATCH 107/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 0e80ba73..4bb74da2 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 0e80ba734e87435a8c6c6d445e83e2c896195134 +Subproject commit 4bb74da2a87a3519d5095a31023cadd256e592a6 From 40203f60a3636e263b6dc02d48fbb9fbd920fd3b Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 04:35:31 +0000 Subject: [PATCH 108/160] update deinit name --- scripts/init-submodules-no-riscv-tools.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 8bf6b300..56934885 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -11,14 +11,14 @@ scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" # ignore riscv-tools for submodule init recursive # you must do this globally (otherwise riscv-tools deep # in the submodule tree will get pulled anyway -git config --global submodule.riscv-tools.update none +git config --global submodule.toolchains/riscv-tools.update none git config --global submodule.esp-tools.update none git config --global submodule.experimental-blocks.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none git submodule update --init --recursive #--jobs 8 # unignore riscv-tools,catapult-shell2 globally -git config --global --unset submodule.riscv-tools.update +git config --global --unset submodule.toolchains/riscv-tools.update git config --global --unset submodule.esp-tools.update git config --global --unset submodule.experimental-blocks.update From 302ffe786905f3e801889693d5a664e4d8d35ec6 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 05:10:18 +0000 Subject: [PATCH 109/160] fix fast init --- scripts/build-toolchains.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index d75d50ec..641fde86 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -66,6 +66,7 @@ do shift done + if [ "$EC2FASTINSTALL" = "true" ]; then if [ "$TOOLCHAIN" = "riscv-tools" ]; then cd $RDIR @@ -73,6 +74,7 @@ if [ "$EC2FASTINSTALL" = "true" ]; then cd firesim-riscv-tools-prebuilt git checkout 56a40961c98db5e8f904f15dc6efd0870bfefd9e PREBUILTHASH="$(cat HASH)" + git -C $CHIPYARD_DIR submodule update --init toolchains/$TOOLCHAIN cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" GITHASH="$(git rev-parse HEAD)" cd $RDIR From 1f0fb1a39954697982f28b2fa580870e9373a792 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 05:28:09 +0000 Subject: [PATCH 110/160] change flag name --- scripts/build-toolchains.sh | 8 ++++---- sims/firesim | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 641fde86..6996b279 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -32,7 +32,7 @@ if [ "$1" == "--help" -o "$1" == "-h" -o "$1" == "-H" ]; then fi TOOLCHAIN="riscv-tools" -FIRESIMINSTALL="false" +EC2INSTALL="false" EC2FASTINSTALL="false" FASTINSTALL="false" while test $# -gt 0 @@ -44,8 +44,8 @@ do hwacha) TOOLCHAIN="esp-tools" ;; - firesim | --firesim) # I don't want to break this api - FIRESIMINSTALL=true + ec2 | --ec2) + EC2INSTALL=true ;; ec2fast | --ec2fast) # I don't want to break this api EC2FASTINSTALL=true @@ -145,7 +145,7 @@ echo "Toolchain Build Complete!" if [ "$FASTINSTALL" = "false" ]; then - if [ "$FIRESIMINSTALL" = "false" ]; then + if [ "$EC2INSTALL" = "false" ]; then echo "Building RISC-V OpenOCD Complete!" check_version automake 1.14 "OpenOCD build" check_version autoconf 2.64 "OpenOCD build" diff --git a/sims/firesim b/sims/firesim index 4bb74da2..536237ba 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4bb74da2a87a3519d5095a31023cadd256e592a6 +Subproject commit 536237ba19249258b7dd1d8c29439417c21396ed From b3f9398faacc585e3e61fcadd990cca1d33267c5 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 06:02:44 +0000 Subject: [PATCH 111/160] fix message --- scripts/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 6996b279..7885dafc 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -146,7 +146,7 @@ echo "Toolchain Build Complete!" if [ "$FASTINSTALL" = "false" ]; then if [ "$EC2INSTALL" = "false" ]; then - echo "Building RISC-V OpenOCD Complete!" + echo "Building RISC-V OpenOCD" check_version automake 1.14 "OpenOCD build" check_version autoconf 2.64 "OpenOCD build" build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --disable-werror From 85aabf62973bbe34d49afc75b656863f37c5ac67 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 07:29:11 +0000 Subject: [PATCH 112/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 536237ba..7019da24 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 536237ba19249258b7dd1d8c29439417c21396ed +Subproject commit 7019da24e2e65b659df9e73e73425f84460bd3d4 From e967667d1b208d835774cfd222cb503f26bcd054 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 21:47:29 +0000 Subject: [PATCH 113/160] remove ec2 arg --- scripts/build-toolchains.sh | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 7885dafc..8fe55960 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -32,7 +32,6 @@ if [ "$1" == "--help" -o "$1" == "-h" -o "$1" == "-H" ]; then fi TOOLCHAIN="riscv-tools" -EC2INSTALL="false" EC2FASTINSTALL="false" FASTINSTALL="false" while test $# -gt 0 @@ -44,9 +43,6 @@ do hwacha) TOOLCHAIN="esp-tools" ;; - ec2 | --ec2) - EC2INSTALL=true - ;; ec2fast | --ec2fast) # I don't want to break this api EC2FASTINSTALL=true ;; @@ -145,7 +141,10 @@ echo "Toolchain Build Complete!" if [ "$FASTINSTALL" = "false" ]; then - if [ "$EC2INSTALL" = "false" ]; then + # commands to run only on EC2 + # see if the instance info page exists. if not, we are not on ec2. + # this is one of the few methods that works without sudo + if wget -T 1 -t 3 -O /dev/null http://169.254.169.254/; then echo "Building RISC-V OpenOCD" check_version automake 1.14 "OpenOCD build" check_version autoconf 2.64 "OpenOCD build" From 4bf789d2bf6be473aaadbccab159b714dcd99026 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 22:34:04 +0000 Subject: [PATCH 114/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 7019da24..37a60cb7 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7019da24e2e65b659df9e73e73425f84460bd3d4 +Subproject commit 37a60cb77b506a88467bdeeddd6f63f398ff2710 From d513d1ac6b8e5a30fac39bb56c7b55c579118568 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 23:00:55 +0000 Subject: [PATCH 115/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 37a60cb7..461b500d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 37a60cb77b506a88467bdeeddd6f63f398ff2710 +Subproject commit 461b500d40d7c366a52486276f20eaaa0c9d5aeb From e29acc2b56e1de087215c06a25555680ad8b028f Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 23:35:53 +0000 Subject: [PATCH 116/160] fix openocd --- scripts/build-toolchains.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 8fe55960..e9b51ae7 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -145,6 +145,8 @@ if [ "$FASTINSTALL" = "false" ]; then # see if the instance info page exists. if not, we are not on ec2. # this is one of the few methods that works without sudo if wget -T 1 -t 3 -O /dev/null http://169.254.169.254/; then + echo "Skipping RISC-V OpenOCD" + else echo "Building RISC-V OpenOCD" check_version automake 1.14 "OpenOCD build" check_version autoconf 2.64 "OpenOCD build" From c35bc3335661b57be5d3084dc4986fe614985611 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 18 Jul 2019 23:37:52 +0000 Subject: [PATCH 117/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 461b500d..671a7cf8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 461b500d40d7c366a52486276f20eaaa0c9d5aeb +Subproject commit 671a7cf88890ec3da0c07dd203d5c944cd16b840 From b47c8a5f30a0a61a5095d7633b56f5e47bce4e84 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 19 Jul 2019 00:24:07 +0000 Subject: [PATCH 118/160] fix usage --- scripts/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index e9b51ae7..cbbfbac7 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -12,7 +12,7 @@ RDIR=$(pwd) function usage { - echo "usage: ./scripts/build-toolchains.sh [riscv] [hwacha] [ firesim | --firesim] [--submodules-only]" + echo "usage: ./scripts/build-toolchains.sh [riscv] [hwacha] [ ec2fast | --ec2fast] " echo " riscv: if set, builds the riscv toolchain (this is also the default)" echo " hwacha: if set, builds esp-tools toolchain" echo " ec2fast: if set, pulls in a pre-compiled RISC-V toolchain for an EC2 manager instance" From b76e89659802bc03a0a1125bee07c777646c5616 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 18 Jul 2019 17:45:13 -0700 Subject: [PATCH 119/160] Update vlsi/Makefile to match variables.mk naming --- vlsi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 7dc797c6..fc0b4ac6 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -44,7 +44,7 @@ ROCKET_SRCS = \ $(ROCKET_SRC_DIR)/plusarg_reader.v \ $(ROCKET_SRC_DIR)/EICG_wrapper.v \ -ALL_RTL = $(ROCKET_SRCS) $(VERILOG_FILE) $(SMEMS_FILE) +ALL_RTL = $(ROCKET_SRCS) $(TOP_FILE) $(TOP_SMEMS_FILE) CLOCK_DOMAINS = $(build_dir)/$(long_name).domains From dc585609cf59a2abb2028f8dfcb75ab91b5b803a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 18 Jul 2019 17:52:37 -0700 Subject: [PATCH 120/160] update hwacha ci to use L2 --- .circleci/defaults.sh | 2 +- generators/example/src/main/scala/Configs.scala | 14 +++++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e777af65..25b365d8 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -41,4 +41,4 @@ mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketCon mapping["boom"]="SUB_PROJECT=boom" mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=BlockDeviceModelRocketConfig TOP=BoomRocketTopWithBlockDevice" -mapping["hwacha"]="SUB_PROJECT=hwacha" +mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaL2Config GENERATOR_PACKAGE=hwacha" diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index c2334ca8..c6cfa7a5 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -63,7 +63,13 @@ class GB1MemoryConfig extends Config( new DefaultRocketConfig) class RocketL2Config extends Config( - new WithInclusiveCache ++ new DefaultRocketConfig) + new WithInclusiveCache ++ + new DefaultRocketConfig) + +class HwachaL2Config extends Config( + new hwacha.DefaultHwachaConfig ++ + new WithInclusiveCache ++ + new DefaultRocketConfig) // ------------ // BOOM Configs @@ -146,7 +152,8 @@ class RV32UnifiedBoomConfig extends Config( new boom.system.SmallRV32UnifiedBoomConfig) class BoomL2Config extends Config( - new WithInclusiveCache ++ new SmallDefaultBoomConfig) + new WithInclusiveCache ++ + new SmallDefaultBoomConfig) // --------------------- // BOOM and Rocket Configs @@ -255,4 +262,5 @@ class RV32BoomAndRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreRocketL2Config extends Config( - new WithInclusiveCache ++ new DualCoreRocketConfig) + new WithInclusiveCache ++ + new DualCoreRocketConfig) From 121c572d72b3384cd8ed9b3ec29c7631a0f2ad71 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 19 Jul 2019 00:54:34 +0000 Subject: [PATCH 121/160] pr comments --- .gitmodules | 6 +++--- scripts/build-toolchains.sh | 6 ++++-- scripts/init-submodules-no-riscv-tools.sh | 4 ++-- sims/firesim | 2 +- 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/.gitmodules b/.gitmodules index 55e8a98b..66bbbce3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,9 +13,6 @@ [submodule "tools/firrtl"] path = tools/firrtl url = https://github.com/freechipsproject/firrtl -[submodule "esp-tools"] - path = toolchains/esp-tools - url = https://github.com/ucb-bar/esp-tools.git [submodule "tools/torture"] path = tools/torture url = https://github.com/ucb-bar/riscv-torture.git @@ -40,3 +37,6 @@ [submodule "toolchains/riscv-tools"] path = toolchains/riscv-tools url = https://github.com/freechipsproject/rocket-tools.git +[submodule "toolchains/esp-tools"] + path = toolchains/esp-tools + url = https://github.com/ucb-bar/esp-tools.git diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index cbbfbac7..36c2abd2 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -10,6 +10,8 @@ unamestr=$(uname) RDIR=$(pwd) : ${CHIPYARD_DIR:=$(pwd)} #default value is the PWD unless overridden +PRECOMPILED_REPO_HASH=56a40961c98db5e8f904f15dc6efd0870bfefd9e + function usage { echo "usage: ./scripts/build-toolchains.sh [riscv] [hwacha] [ ec2fast | --ec2fast] " @@ -68,7 +70,7 @@ if [ "$EC2FASTINSTALL" = "true" ]; then cd $RDIR git clone https://github.com/firesim/firesim-riscv-tools-prebuilt.git cd firesim-riscv-tools-prebuilt - git checkout 56a40961c98db5e8f904f15dc6efd0870bfefd9e + git checkout $PRECOMPILED_REPO_HASH PREBUILTHASH="$(cat HASH)" git -C $CHIPYARD_DIR submodule update --init toolchains/$TOOLCHAIN cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" @@ -141,7 +143,7 @@ echo "Toolchain Build Complete!" if [ "$FASTINSTALL" = "false" ]; then - # commands to run only on EC2 + # commands that can't run on EC2 (specifically, OpenOCD because of autoconf version_ # see if the instance info page exists. if not, we are not on ec2. # this is one of the few methods that works without sudo if wget -T 1 -t 3 -O /dev/null http://169.254.169.254/; then diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 56934885..40f530e6 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -12,14 +12,14 @@ scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" # you must do this globally (otherwise riscv-tools deep # in the submodule tree will get pulled anyway git config --global submodule.toolchains/riscv-tools.update none -git config --global submodule.esp-tools.update none +git config --global submodule.toolchains/esp-tools.update none git config --global submodule.experimental-blocks.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none git submodule update --init --recursive #--jobs 8 # unignore riscv-tools,catapult-shell2 globally git config --global --unset submodule.toolchains/riscv-tools.update -git config --global --unset submodule.esp-tools.update +git config --global --unset submodule.toolchains/esp-tools.update git config --global --unset submodule.experimental-blocks.update # Renable firesim and init only the required submodules to provide diff --git a/sims/firesim b/sims/firesim index 671a7cf8..0d7bc1db 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 671a7cf88890ec3da0c07dd203d5c944cd16b840 +Subproject commit 0d7bc1db078d37731dd3d6c3d137a12a7ac42b0e From b74b23aad0bfdc3a2279b2e55a1f7d2180331c51 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 19 Jul 2019 05:57:43 +0000 Subject: [PATCH 122/160] remove global --- scripts/init-submodules-no-riscv-tools.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 778a991a..cd5924a2 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -11,8 +11,8 @@ scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" # ignore riscv-tools for submodule init recursive # you must do this globally (otherwise riscv-tools deep # in the submodule tree will get pulled anyway -git config --global submodule.toolchains/riscv-tools.update none -git config --global submodule.toolchains/esp-tools.update none +git config submodule.toolchains/riscv-tools.update none +git config submodule.toolchains/esp-tools.update none git config --global submodule.experimental-blocks.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none @@ -20,8 +20,8 @@ git config submodule.sims/firesim.update none git config submodule.vlsi/hammer-cad-plugins.update none git submodule update --init --recursive #--jobs 8 # unignore riscv-tools,catapult-shell2 globally -git config --global --unset submodule.toolchains/riscv-tools.update -git config --global --unset submodule.toolchains/esp-tools.update +git config --unset submodule.toolchains/riscv-tools.update +git config --unset submodule.toolchains/esp-tools.update git config --global --unset submodule.experimental-blocks.update # Renable firesim and init only the required submodules to provide From 265380d960b3dedab7cebf08d787237dd9de3435 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 19 Jul 2019 16:59:40 +0000 Subject: [PATCH 123/160] fix install path --- scripts/build-toolchains.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 36c2abd2..a334c2cf 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -92,7 +92,6 @@ if [ "$EC2FASTINSTALL" = "true" ]; then fi INSTALL_DIR="$TOOLCHAIN-install" -mkdir -p "$(pwd)/$INSTALL_DIR" RISCV="$(pwd)/$INSTALL_DIR" @@ -102,12 +101,13 @@ export RISCV="$RISCV" if [ "$FASTINSTALL" = true ]; then cd firesim-riscv-tools-prebuilt ./installrelease.sh - mv distrib $RISCV + mv distrib "$RISCV" # copy HASH in case user wants it later - cp HASH $RISCV + cp HASH "$RISCV" cd $RDIR rm -rf firesim-riscv-tools-prebuilt else + mkdir -p "$RISCV" git -C $CHIPYARD_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" export MAKEFLAGS="-j16" From e63db54b9c28505779fc726fd0cd6e5b69b5d4dd Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 19 Jul 2019 15:03:28 -0700 Subject: [PATCH 124/160] Add first-time-run instructions to vlsi/README --- scripts/init-vlsi.sh | 6 ++++++ vlsi/README.md | 6 +++++- 2 files changed, 11 insertions(+), 1 deletion(-) create mode 100755 scripts/init-vlsi.sh diff --git a/scripts/init-vlsi.sh b/scripts/init-vlsi.sh new file mode 100755 index 00000000..ab947dd1 --- /dev/null +++ b/scripts/init-vlsi.sh @@ -0,0 +1,6 @@ +# Initialize HAMMER and CAD-plugins +git submodule update --init --recursive vlsi/hammer +git submodule update --init --recursive vlsi/hammer-cad-plugins + +# Initialize HAMMER tech plugin +git submodule update --init --recursive vlsi/hammer-$1-plugin \ No newline at end of file diff --git a/vlsi/README.md b/vlsi/README.md index d09fb5d8..aa07dd0f 100644 --- a/vlsi/README.md +++ b/vlsi/README.md @@ -2,4 +2,8 @@ This is the starting point for a vlsi flow from this repository. This flow will not work without the necessary CAD and technology plugins for HAMMER. -If you are a UCB-affiliate, you may be able to acquire access to the tech-plugins. \ No newline at end of file +If you are a UCB-affiliate, you may be able to acquire access to the tech-plugins. + +# Initial Setup Instructions (For All technologies) +Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-cad-plugins, and the hammer-tech-plugins +```scripts/init-vlsi.sh TECH_NAME``` \ No newline at end of file From b923617f644eed0d1777b1ffa50662f02369acba Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 19 Jul 2019 15:06:51 -0700 Subject: [PATCH 125/160] Fixup init-vlsi.sh --- scripts/init-vlsi.sh | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/scripts/init-vlsi.sh b/scripts/init-vlsi.sh index ab947dd1..294f8628 100755 --- a/scripts/init-vlsi.sh +++ b/scripts/init-vlsi.sh @@ -1,3 +1,10 @@ +#!/usr/bin/env bash +# exit script if any command fails +set -e +set -o pipefail + + + # Initialize HAMMER and CAD-plugins git submodule update --init --recursive vlsi/hammer git submodule update --init --recursive vlsi/hammer-cad-plugins From 0894919404fccc0e34e8f936778f6f053945113e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 19 Jul 2019 15:07:03 -0700 Subject: [PATCH 126/160] Ignore emacs temp files --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 8450e9b8..08493eec 100644 --- a/.gitignore +++ b/.gitignore @@ -10,3 +10,4 @@ target env.sh riscv-tools-install tags +*~ \ No newline at end of file From 6ec5cd4ccdea0acaef2b56a1b2f0ff9237a1b02e Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 10 Jul 2019 13:34:14 -0700 Subject: [PATCH 127/160] replace DefaultBusConfiguration trait with HierarchicalBusTopology trait from FireSim --- .../src/main/scala/TargetMixins.scala | 24 ------------------- .../firechip/src/main/scala/Targets.scala | 8 +++---- 2 files changed, 4 insertions(+), 28 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 5544376f..7b4d5d4f 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -14,30 +14,6 @@ import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} import midas.models.AXI4BundleWithEdge import midas.targetutils.ExcludeInstanceAsserts -/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */ -trait HasDefaultBusConfiguration { - this: BaseSubsystem => - // The sbus masters the cbus; here we convert TL-UH -> TL-UL - sbus.crossToBus(cbus, NoCrossing) - - // The cbus masters the pbus; which might be clocked slower - cbus.crossToBus(pbus, SynchronousCrossing()) - - // The fbus masters the sbus; both are TL-UH or TL-C - FlipRendering { implicit p => - sbus.crossFromBus(fbus, SynchronousCrossing()) - } - - // The sbus masters the mbus; here we convert TL-C -> TL-UH - private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) - private val (in, out, halt) = coherenceManager(this) - if (nBanks != 0) { - sbus.coupleTo("coherence_manager") { in :*= _ } - mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } - } -} - - /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges * associated with each port. This drives FASED functional model sizing */ diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index c9077044..7f8bb830 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -31,7 +31,7 @@ import java.io.File *******************************************************************************/ class FireSim(implicit p: Parameters) extends RocketSubsystem - with HasDefaultBusConfiguration + with HasHierarchicalBusTopology with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -57,7 +57,7 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem - with HasDefaultBusConfiguration + with HasHierarchicalBusTopology with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -81,7 +81,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem - with HasDefaultBusConfiguration + with HasHierarchicalBusTopology with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -107,7 +107,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI with ExcludeInvalidBoomAssertions class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem - with HasDefaultBusConfiguration + with HasHierarchicalBusTopology with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug From 52322376e619d5d2c2e897ebc2c642ac3c270248 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Fri, 19 Jul 2019 16:44:46 -0700 Subject: [PATCH 128/160] Unset the init for `hammer-cad-plugins` This allows the user to not run the `unset` command after the init script to update the submodules. --- scripts/init-submodules-no-riscv-tools.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 99b1b497..50c41f7a 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -23,6 +23,7 @@ git submodule update --init --recursive #--jobs 8 git config --global --unset submodule.riscv-tools.update git config --global --unset submodule.esp-tools.update git config --global --unset submodule.experimental-blocks.update +git config --unset submodule.vlsi/hammer-cad-plugins.update # Renable firesim and init only the required submodules to provide # all required scala deps, without doing a full build-setup From 59bd39a335beb6d1b69433a08d2f73e70a74122f Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 22 Jul 2019 06:46:55 +0000 Subject: [PATCH 129/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 0d7bc1db..ce44b13e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 0d7bc1db078d37731dd3d6c3d137a12a7ac42b0e +Subproject commit ce44b13e976524238746d67b2ff45bde04e4e9ce From 8646283a17c6637379f311e0d412f3ae18b812c0 Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 22 Jul 2019 16:35:15 +0000 Subject: [PATCH 130/160] colin comments --- scripts/build-static-libfesvr.sh | 2 +- scripts/build-toolchains.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/build-static-libfesvr.sh b/scripts/build-static-libfesvr.sh index 5dc0eac3..360028ad 100755 --- a/scripts/build-static-libfesvr.sh +++ b/scripts/build-static-libfesvr.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # This ungodly script surreptitiously builds an archive from existing fesvr objects # Invoke from riscv-fesvr/build diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index a334c2cf..2d78c874 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -50,7 +50,7 @@ do ;; -h | -H | --help) usage - exit + exit 3 ;; --*) echo "ERROR: bad option $1" usage From 9e5ed591b9f1e7d7cd35f18c941252e2543d137b Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 22 Jul 2019 16:54:23 +0000 Subject: [PATCH 131/160] try to fix CI --- .circleci/build-toolchains.sh | 2 +- scripts/build-toolchains.sh | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index d0be57c2..63f47505 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -14,5 +14,5 @@ if [ ! -d "$HOME/$1-install" ]; then cd $HOME # init all submodules including the tools - CHIPYARD_DIR=$LOCAL_CHIPYARD_DIR .$LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 + CHIPYARD_DIR=$LOCAL_CHIPYARD_DIR $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 fi diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 2d78c874..a39c24cd 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -14,7 +14,7 @@ PRECOMPILED_REPO_HASH=56a40961c98db5e8f904f15dc6efd0870bfefd9e function usage { - echo "usage: ./scripts/build-toolchains.sh [riscv] [hwacha] [ ec2fast | --ec2fast] " + echo "usage: ./scripts/build-toolchains.sh [riscv-tools] [esp-tools] [ec2fast | --ec2fast] " echo " riscv: if set, builds the riscv toolchain (this is also the default)" echo " hwacha: if set, builds esp-tools toolchain" echo " ec2fast: if set, pulls in a pre-compiled RISC-V toolchain for an EC2 manager instance" @@ -39,10 +39,10 @@ FASTINSTALL="false" while test $# -gt 0 do case "$1" in - riscv) + riscv-tools) TOOLCHAIN="riscv-tools" ;; - hwacha) + esp-tools) TOOLCHAIN="esp-tools" ;; ec2fast | --ec2fast) # I don't want to break this api From e177fcd41413c8192a32d224acf2f6ef43fcb76e Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 22 Jul 2019 17:41:31 +0000 Subject: [PATCH 132/160] try to fix openocd path --- scripts/build-toolchains.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index a39c24cd..8d5676ce 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -150,6 +150,7 @@ if [ "$FASTINSTALL" = "false" ]; then echo "Skipping RISC-V OpenOCD" else echo "Building RISC-V OpenOCD" + cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" check_version automake 1.14 "OpenOCD build" check_version autoconf 2.64 "OpenOCD build" build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --disable-werror From 72b5df057a241351888c8e793f45c2bff0d2fc53 Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 22 Jul 2019 17:43:51 +0000 Subject: [PATCH 133/160] Return to main dir --- scripts/build-toolchains.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 8d5676ce..ac4316b7 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -155,5 +155,6 @@ if [ "$FASTINSTALL" = "false" ]; then check_version autoconf 2.64 "OpenOCD build" build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --disable-werror echo -e "\\nRISC-V OpenOCD installation completed!" + cd $RDIR fi fi From 3b4f52ab59705ce2c3fa8012d82e29ea17e1a172 Mon Sep 17 00:00:00 2001 From: alonamid Date: Mon, 22 Jul 2019 21:06:52 +0000 Subject: [PATCH 134/160] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index ce44b13e..4cd75833 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ce44b13e976524238746d67b2ff45bde04e4e9ce +Subproject commit 4cd75833dfc1f9f796a1c5505ece6937fd253189 From fe45d9497428444eda1871e5751f615bf5d2e177 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 11 Jul 2019 03:38:11 +0000 Subject: [PATCH 135/160] make sure git submodule update --init run from top-level directories --- scripts/firesim-setup.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/scripts/firesim-setup.sh b/scripts/firesim-setup.sh index 53dee5ab..302294bf 100755 --- a/scripts/firesim-setup.sh +++ b/scripts/firesim-setup.sh @@ -7,12 +7,12 @@ set -o pipefail RDIR=$(pwd) scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" -sims_dir=$scripts_dir/../sims/ + +cd $scripts_dir/.. # Reenable the FireSim submodule git config --unset submodule.sims/firesim.update || true -cd $sims_dir -git submodule update --init firesim -cd firesim +git submodule update --init sims/firesim +cd sims/firesim ./build-setup.sh $@ --library cd $RDIR From ce0806a37148c180edad177d5e41c5169ca8720d Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 24 Jul 2019 10:51:40 -0700 Subject: [PATCH 136/160] Switch submodules to https --- .gitmodules | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 03507b25..20898374 100644 --- a/.gitmodules +++ b/.gitmodules @@ -42,7 +42,7 @@ url = https://github.com/ucb-bar/esp-tools.git [submodule "vlsi/hammer"] path = vlsi/hammer - url = git@github.com:ucb-bar/hammer.git + url = https://github.com/ucb-bar/hammer.git [submodule "vlsi/hammer-cad-plugins"] path = vlsi/hammer-cad-plugins - url = git@github.com:ucb-bar/hammer-cad-plugins + url = https://github.com/ucb-bar/hammer-cad-plugins From 87195152abe742f932e19185a0bd2efb40a9f1ea Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Jul 2019 13:24:32 -0700 Subject: [PATCH 137/160] added .git to end of hammer-cad-plugins --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index 20898374..5bbbedd0 100644 --- a/.gitmodules +++ b/.gitmodules @@ -45,4 +45,4 @@ url = https://github.com/ucb-bar/hammer.git [submodule "vlsi/hammer-cad-plugins"] path = vlsi/hammer-cad-plugins - url = https://github.com/ucb-bar/hammer-cad-plugins + url = https://github.com/ucb-bar/hammer-cad-plugins.git From 288ec15ba5d35ef17d1572709b19444d8ae3a916 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 24 Jul 2019 15:22:06 -0700 Subject: [PATCH 138/160] Fix run-binary-debug verbosity --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index f9d5896b..76baf09c 100644 --- a/common.mk +++ b/common.mk @@ -96,7 +96,7 @@ run-binary-fast: $(sim) # helper rules to run simulator with as much debug info as possible ######################################################################################### run-binary-debug: $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAG) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) run-fast: run-asm-tests-fast run-bmark-tests-fast From 89b312a8891a4df855d82d4accdfb0db20613d65 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Jul 2019 22:42:21 -0700 Subject: [PATCH 139/160] move boom integration to chipyard --- generators/boom | 2 +- .../example/src/main/scala/BoomConfigs.scala | 97 +++++++++++++++++++ .../example/src/main/scala/ConfigMixins.scala | 9 ++ .../example/src/main/scala/Configs.scala | 30 +++--- .../example/src/main/scala/TestHarness.scala | 48 ++++++++- generators/example/src/main/scala/Top.scala | 13 ++- variables.mk | 2 +- 7 files changed, 179 insertions(+), 22 deletions(-) create mode 100644 generators/example/src/main/scala/BoomConfigs.scala diff --git a/generators/boom b/generators/boom index 51bfc070..962e9467 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 51bfc070e8b4750f5401b5db235233421ab8deba +Subproject commit 962e94674ebd859d4798efe44cb6e404be9a5076 diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala new file mode 100644 index 00000000..e8044080 --- /dev/null +++ b/generators/example/src/main/scala/BoomConfigs.scala @@ -0,0 +1,97 @@ +//****************************************************************************** +// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). +// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. +//------------------------------------------------------------------------------ +// Author: Christopher Celio, Abraham Gonzalez, Ben Korpan, Jerry Zhao +//------------------------------------------------------------------------------ + +package example + +import chisel3._ + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.subsystem.{WithJtagDTM} + +import boom.common._ + +// --------------------- +// BOOM Configs +// --------------------- + +class SmallBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallBoomConfig) + +class MediumBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.MediumBoomConfig) + +class LargeBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.LargeBoomConfig) + +class MegaBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.MegaBoomConfig) + +class jtagSmallBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.SmallBoomConfig) + +class jtagMediumBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.MediumBoomConfig) + +class jtagLargeBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.LargeBoomConfig) + +class jtagMegaBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.MegaBoomConfig) + +class SmallDualBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallDualBoomConfig) + +class TracedSmallBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.TracedSmallBoomConfig) + +class SmallRV32UnifiedBoomConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallRV32UnifiedBoomConfig) + +// -------------------------- +// BOOM + Rocket Configs +// -------------------------- + +class SmallBoomAndRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.SmallBoomAndRocketConfig) + +class MediumBoomAndRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.MediumBoomAndRocketConfig) + +class DualMediumBoomAndDualRocketConfig extends Config( + new WithNormalBoomRocketTop ++ + new WithBootROM ++ + new boom.common.DualMediumBoomAndDualRocketConfig) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 895fa86a..17fac94d 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -58,6 +58,15 @@ class WithNormalBoomRocketTop extends Config((site, here, up) => { } }) +/** + * Class to specify a top level BOOM and/or Rocket system with DTM + */ +class WithDTMBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomRocketTopWithDTM()(p)).module) + } +}) + /** * Class to specify a top level BOOM and/or Rocket system with PWM */ diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index c6cfa7a5..c7e70dd2 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -77,11 +77,11 @@ class HwachaL2Config extends Config( class BaseBoomConfig extends Config( new WithBootROM ++ - new boom.system.LargeBoomConfig) + new boom.common.LargeBoomConfig) class SmallBaseBoomConfig extends Config( new WithBootROM ++ - new boom.system.SmallBoomConfig) + new boom.common.SmallBoomConfig) class DefaultBoomConfig extends Config( new WithNormalBoomRocketTop ++ @@ -132,7 +132,7 @@ class DualCoreBoomConfig extends Config( new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) @@ -142,14 +142,14 @@ class DualCoreSmallBoomConfig extends Config( new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) class RV32UnifiedBoomConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ - new boom.system.SmallRV32UnifiedBoomConfig) + new boom.common.SmallRV32UnifiedBoomConfig) class BoomL2Config extends Config( new WithInclusiveCache ++ @@ -161,22 +161,22 @@ class BoomL2Config extends Config( class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(1) ++ + new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class SmallBaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(1) ++ + new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) @@ -223,11 +223,11 @@ class GPIOBoomAndRocketConfig extends Config( class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) @@ -237,12 +237,12 @@ class DualBoomAndOneHwachaRocketConfig extends Config( new WithBootROM ++ new WithMultiRoCC ++ new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket - new boom.system.WithRenumberHarts(rocketFirst = true) ++ + new boom.common.WithRenumberHarts(rocketFirst = true) ++ new hwacha.DefaultHwachaConfig ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(2) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) @@ -250,12 +250,12 @@ class DualBoomAndOneHwachaRocketConfig extends Config( class RV32BoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ - new boom.system.WithRenumberHarts ++ + new boom.common.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ new boom.common.WithRVC ++ new boom.common.WithLargeBooms ++ new boom.common.BaseBoomConfig ++ - new boom.system.WithNBoomCores(1) ++ + new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithRV32 ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index c59a081e..778fcc81 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -8,14 +8,19 @@ import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp +import freechips.rocketchip.devices.debug.{Debug} -// -------------------------- +// ------------------------------- // BOOM and/or Rocket Test Harness -// -------------------------- +// ------------------------------- case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]] +case object BuildBoomRocketTopWithDTM extends Field[(Clock, Bool, Parameters) => BoomRocketTopWithDTMModule[BoomRocketTopWithDTM]] -class BoomRocketTestHarness(implicit val p: Parameters) extends Module { +/** + * Test harness using TSI to bringup the system + */ +class TestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) @@ -24,6 +29,7 @@ class BoomRocketTestHarness(implicit val p: Parameters) extends Module { override def desiredName = "TestHarness" val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p) + dut.debug := DontCare dut.connectSimAXIMem() dut.connectSimAXIMMIO() @@ -41,5 +47,41 @@ class BoomRocketTestHarness(implicit val p: Parameters) extends Module { axi.w.bits := DontCare } }) + io.success := dut.connectSimSerial() } + +/** + * Test harness using the Debug Test Module (DTM) to bringup the system + */ +class TestHarnessWithDTM(implicit p: Parameters) extends Module +{ + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + // force Chisel to rename module + override def desiredName = "TestHarness" + + val dut = p(BuildBoomRocketTopWithDTM)(clock, reset.toBool, p) + + dut.reset := reset.asBool | dut.debug.ndreset + dut.connectSimAXIMem() + dut.connectSimAXIMMIO() + dut.dontTouchPorts() + dut.tieOffInterrupts() + dut.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case core.ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case core.ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + + Debug.connectDebug(dut.debug, clock, reset.asBool, io.success) +} diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index a3fa99f8..b861fdec 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -12,9 +12,9 @@ import testchipip._ import sifive.blocks.devices.gpio._ -// ------------------------------- +// ------------------------------------ // BOOM and/or Rocket Top Level Systems -// ------------------------------- +// ------------------------------------ class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem with HasNoDebug @@ -67,3 +67,12 @@ class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO) extends BoomRocketTopModule(l) with HasPeripheryGPIOModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomRocketTopWithDTM(implicit p: Parameters) extends boom.system.BoomRocketSystem +{ + override lazy val module = new BoomRocketTopWithDTMModule(this) +} + +class BoomRocketTopWithDTMModule[+L <: BoomRocketTopWithDTM](l: L) extends boom.system.BoomRocketSystemModule(l) diff --git a/variables.mk b/variables.mk index a0c6a9af..fa7bb494 100644 --- a/variables.mk +++ b/variables.mk @@ -29,7 +29,7 @@ SUB_PROJECT ?= example ifeq ($(SUB_PROJECT),example) SBT_PROJECT ?= example - MODEL ?= BoomRocketTestHarness + MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultRocketConfig From a8dbc391a15334050aa4b4f658343d8c192565f0 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 24 Jul 2019 22:55:00 -0700 Subject: [PATCH 140/160] remove boom variables | update ci --- .circleci/defaults.sh | 2 +- generators/boom | 2 +- variables.mk | 12 ------------ 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 25b365d8..cdccc3ba 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -38,7 +38,7 @@ declare -A mapping mapping["example"]="SUB_PROJECT=example" mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig" mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig" -mapping["boom"]="SUB_PROJECT=boom" +mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=BlockDeviceModelRocketConfig TOP=BoomRocketTopWithBlockDevice" mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaL2Config GENERATOR_PACKAGE=hwacha" diff --git a/generators/boom b/generators/boom index 962e9467..3a06403d 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 962e94674ebd859d4798efe44cb6e404be9a5076 +Subproject commit 3a06403df71d46f2c42f9baac134a3b2997595e5 diff --git a/variables.mk b/variables.mk index fa7bb494..66eb0518 100644 --- a/variables.mk +++ b/variables.mk @@ -38,18 +38,6 @@ ifeq ($(SUB_PROJECT),example) TB ?= TestDriver TOP ?= BoomRocketTop endif -# for BOOM developers -ifeq ($(SUB_PROJECT),boom) - SBT_PROJECT ?= boom - MODEL ?= TestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= boom.system - CONFIG ?= LargeBoomConfig - CONFIG_PACKAGE ?= boom.system - GENERATOR_PACKAGE ?= boom.system - TB ?= TestDriver - TOP ?= BoomRocketSystem -endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) SBT_PROJECT ?= rocketchip From 495e9d2668cfeb69075b0d4d023019cbec53e412 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 24 Jul 2019 23:19:18 -0700 Subject: [PATCH 141/160] Do not clobber LD_LIBRARY_PATH in env.sh --- scripts/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index ac4316b7..15a615d3 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -138,7 +138,7 @@ cd $RDIR echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" > env.sh echo "export RISCV=$RISCV" >> env.sh echo "export PATH=$RISCV/bin:$RDIR/$DTCversion:\$PATH" >> env.sh -echo "export LD_LIBRARY_PATH=$RISCV/lib" >> env.sh +echo "export LD_LIBRARY_PATH=$RISCV/lib:\$LD_LIBRARY_PATH" >> env.sh echo "Toolchain Build Complete!" From aec0fb73c48616a7bea8528bdea2b03bc5d53bdb Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 25 Jul 2019 01:20:38 -0700 Subject: [PATCH 142/160] docs reorg --- docs/Advanced-Usage/index.rst | 5 --- docs/Chipyard-Basics/Building-A-Chip.rst | 3 ++ .../Chipyard-Components.rst} | 2 +- .../Chipyard-Generator-Mixins.rst | 0 .../Configs-Parameters-Mixins.rst | 0 .../Development-Ecosystem.rst | 0 .../Initial-Repo-Setup.rst | 6 +-- .../Running-A-Simulation.rst | 0 docs/Chipyard-Basics/index.rst | 24 +++++++++++ .../Adding-An-Accelerator.rst} | 8 +++- .../Heterogeneous-SoCs.rst | 0 docs/Customization/Memory-Hierarchy.rst | 4 ++ docs/Customization/index.rst | 17 ++++++++ docs/Getting-Started/index.rst | 21 --------- docs/Quick-Start.rst | 43 +++++++++++++++++++ .../FPGA-Accelerated-Simulators.rst | 35 ++++++++++++++- docs/Simulation/Software-RTL-Simulators.rst | 2 + docs/index.rst | 12 ++++-- 18 files changed, 145 insertions(+), 37 deletions(-) create mode 100644 docs/Chipyard-Basics/Building-A-Chip.rst rename docs/{Getting-Started/Chipyard-Basics.rst => Chipyard-Basics/Chipyard-Components.rst} (99%) rename docs/{Getting-Started => Chipyard-Basics}/Chipyard-Generator-Mixins.rst (100%) rename docs/{Getting-Started => Chipyard-Basics}/Configs-Parameters-Mixins.rst (100%) rename docs/{Getting-Started => Chipyard-Basics}/Development-Ecosystem.rst (100%) rename docs/{Getting-Started => Chipyard-Basics}/Initial-Repo-Setup.rst (88%) rename docs/{Getting-Started => Chipyard-Basics}/Running-A-Simulation.rst (100%) create mode 100644 docs/Chipyard-Basics/index.rst rename docs/{Getting-Started/Adding-An-Accelerator-Tutorial.rst => Customization/Adding-An-Accelerator.rst} (97%) rename docs/{Advanced-Usage => Customization}/Heterogeneous-SoCs.rst (100%) create mode 100644 docs/Customization/Memory-Hierarchy.rst create mode 100644 docs/Customization/index.rst delete mode 100644 docs/Getting-Started/index.rst create mode 100644 docs/Quick-Start.rst diff --git a/docs/Advanced-Usage/index.rst b/docs/Advanced-Usage/index.rst index 62dd11aa..ef8988be 100644 --- a/docs/Advanced-Usage/index.rst +++ b/docs/Advanced-Usage/index.rst @@ -4,8 +4,3 @@ Advanced Usage The following sections are advanced topics about how to use Chipyard and special features of the framework. They expect you to know about Chisel, Parameters, Configs, etc. -.. toctree:: - :maxdepth: 2 - :caption: Getting Started: - - Heterogeneous-SoCs diff --git a/docs/Chipyard-Basics/Building-A-Chip.rst b/docs/Chipyard-Basics/Building-A-Chip.rst new file mode 100644 index 00000000..17fb4512 --- /dev/null +++ b/docs/Chipyard-Basics/Building-A-Chip.rst @@ -0,0 +1,3 @@ +Building A Chip +============================== +TODO diff --git a/docs/Getting-Started/Chipyard-Basics.rst b/docs/Chipyard-Basics/Chipyard-Components.rst similarity index 99% rename from docs/Getting-Started/Chipyard-Basics.rst rename to docs/Chipyard-Basics/Chipyard-Components.rst index c5aa5a62..8285644f 100644 --- a/docs/Getting-Started/Chipyard-Basics.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -1,4 +1,4 @@ -Chipyard Basics +Chipyard Components =============================== Generators diff --git a/docs/Getting-Started/Chipyard-Generator-Mixins.rst b/docs/Chipyard-Basics/Chipyard-Generator-Mixins.rst similarity index 100% rename from docs/Getting-Started/Chipyard-Generator-Mixins.rst rename to docs/Chipyard-Basics/Chipyard-Generator-Mixins.rst diff --git a/docs/Getting-Started/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst similarity index 100% rename from docs/Getting-Started/Configs-Parameters-Mixins.rst rename to docs/Chipyard-Basics/Configs-Parameters-Mixins.rst diff --git a/docs/Getting-Started/Development-Ecosystem.rst b/docs/Chipyard-Basics/Development-Ecosystem.rst similarity index 100% rename from docs/Getting-Started/Development-Ecosystem.rst rename to docs/Chipyard-Basics/Development-Ecosystem.rst diff --git a/docs/Getting-Started/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst similarity index 88% rename from docs/Getting-Started/Initial-Repo-Setup.rst rename to docs/Chipyard-Basics/Initial-Repo-Setup.rst index 58a40d56..7b7042ee 100644 --- a/docs/Getting-Started/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -8,8 +8,8 @@ After cloning this repo, you will need to initialize all of the submodules. .. code-block:: shell - git clone https://github.com/ucb-bar/project-template.git - cd project-template + git clone https://github.com/ucb-bar/chipyard.git + cd chipyard ./scripts/init-submodules-no-riscv-tools.sh Building a Toolchain @@ -26,7 +26,7 @@ But to get a basic installation, just the following steps are necessary. # OR - ./scripts/build-toolchains.sh hwacha # for a hwacha modified risc-v toolchain + ./scripts/build-toolchains.sh esp-tools # for a modified risc-v toolchain with Hwacha vector instructions Once the script is run, a ``env.sh`` file is emitted at sets the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables. You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables. diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Chipyard-Basics/Running-A-Simulation.rst similarity index 100% rename from docs/Getting-Started/Running-A-Simulation.rst rename to docs/Chipyard-Basics/Running-A-Simulation.rst diff --git a/docs/Chipyard-Basics/index.rst b/docs/Chipyard-Basics/index.rst new file mode 100644 index 00000000..be46c627 --- /dev/null +++ b/docs/Chipyard-Basics/index.rst @@ -0,0 +1,24 @@ +Chipyard Basics +================================ + +These guides will walk you through the basics of the Chipyard framework: + +- First, we will go over the components of the framework. + +- Next, we will go over the different configurations available. + +- Then, we will go over initial framework setup. + +- Finally, we will briefly walk through what you can do with the Chipyard tools. + +Hit next to get started! + +.. toctree:: + :maxdepth: 2 + :caption: Chipyard Basics: + + Chipyard-Components + Configs-Parameters-Mixins + Initial-Repo-Setup + Running-A-Simulation + Building-A-Chip diff --git a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst b/docs/Customization/Adding-An-Accelerator.rst similarity index 97% rename from docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst rename to docs/Customization/Adding-An-Accelerator.rst index 4edbde1b..611bf002 100644 --- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst +++ b/docs/Customization/Adding-An-Accelerator.rst @@ -49,7 +49,7 @@ Then add ``yourproject`` to the Chipyard top-level build.sbt file. .. code-block:: scala - lazy val yourproject = project.settings(commonSettings).dependsOn(rocketchip) + lazy val yourproject = (project in file("generators/yourproject")).settings(commonSettings).dependsOn(rocketchip) You can then import the classes defined in the submodule in a new project if you add it as a dependency. For instance, if you want to use this code in @@ -62,6 +62,12 @@ the ``example`` project, change the final line in build.sbt to the following. Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the Chipyard top level. This will allow make to detect that your source files have changed when building the Verilog/FIRRTL files. +.. code-block:: shell + + PACKAGES=$(addprefix generators/, rocket-chip testchipip boom hwacha sifive-blocks sifive-cache example yourproject) \ + $(addprefix sims/firesim/sim/, . firesim-lib midas midas/targetutils) + + MMIO Peripheral ------------------ diff --git a/docs/Advanced-Usage/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst similarity index 100% rename from docs/Advanced-Usage/Heterogeneous-SoCs.rst rename to docs/Customization/Heterogeneous-SoCs.rst diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst new file mode 100644 index 00000000..fc9792c4 --- /dev/null +++ b/docs/Customization/Memory-Hierarchy.rst @@ -0,0 +1,4 @@ +Memory Hierarchy +=============================== +TODO: Talk about SiFive Cache, and integration with L1 and backing main memory models +(maybe even Tilelink) diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst new file mode 100644 index 00000000..c8cb9cc3 --- /dev/null +++ b/docs/Customization/index.rst @@ -0,0 +1,17 @@ +Customization +================================ + +These guides will walk you through customization of your system-on-chip: + +- Contructing heterogenous systems-on-chip using the Chipyard generators and configuration system. + +- Adding custom accelerators to your system-on-chip. + +Hit next to get started! + +.. toctree:: + :maxdepth: 2 + :caption: Customization: + Heterogeneous-SoCs + Adding-An-Accelerator + Memory-Hierarchy diff --git a/docs/Getting-Started/index.rst b/docs/Getting-Started/index.rst deleted file mode 100644 index dcfe0802..00000000 --- a/docs/Getting-Started/index.rst +++ /dev/null @@ -1,21 +0,0 @@ -Getting Started -================================ - -These guides will walk you through the basics of the Chipyard framework: - -- First, we will go over the different configurations available. - -- Then, we will walk through adding a custom accelerator. - -Hit next to get started! - -.. toctree:: - :maxdepth: 2 - :caption: Getting Started: - - Chipyard-Basics - Configs-Parameters-Mixins - Adding-An-Accelerator-Tutorial - Initial-Repo-Setup - Running-A-Simulation - Chipyard-Generator-Mixins diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst new file mode 100644 index 00000000..e319a3d4 --- /dev/null +++ b/docs/Quick-Start.rst @@ -0,0 +1,43 @@ +Quick Start +=============================== + +Setting up the Chipyard Repo +------------------------------------------- + +Start by fetching Chipyard's sources. Run: + +.. code-block:: shell + + git clone https://github.com/ucb-bar/chipyard.git + cd chipyard + ./scripts/init-submodules-no-riscv-tools.sh + +This will have initialized submodules and installed the RISC-V tools and +other dependencies. + +Installing the RISC-V Tools +------------------------------------------- + +We need to install the RISC-V toolchain in order to be able to run RISC-V programs using the Chipyard infrastructure. +This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. +TO build the toolchains, you should run: + +:: + + ./scripts/build-toolchains.sh + +.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchains by adding the ``esp-tools`` argument to the script above. + If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expediated installation of a pre-compiled toolchain. + + +What's Next? +------------------------------------------- + +This depends on what you are planning to do with Chipyard. +- If you want to learn about the structure of Chipyard, go to <>. +- If you intend to build one of the vanilla Chipyard examples, go to <> and follow the instructions. +- If you intend to add a new accelerator, go to <> and follow the instructions. +- If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. +- If you intend to run a simulation of a custom Chipyard SoC Configuration, go to <> and follow the instructions. +- If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. +- If you intend to run a VLSI flow using one of the vanilla Chipyard examples, go to <> and follow the instructions. diff --git a/docs/Simulation/FPGA-Accelerated-Simulators.rst b/docs/Simulation/FPGA-Accelerated-Simulators.rst index 6dab6378..ed13d629 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulators.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulators.rst @@ -1,3 +1,5 @@ +.. _firesim-sim-intro: + FPGA-Accelerated Simulators ============================== @@ -50,8 +52,37 @@ cannot build a FireSim simulator from any generator project in Chipyard except ` which properly invokes MIDAS on the target RTL. In the interim, workaround this limitation by importing Config and Module -classes from other generator projects into FireChip. You should then be able to -refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG`` +classes from other generator projects into FireChip. For example, assuming you Chipyard +config looks as following: + +.. code-block:: scala + class CustomConfig extends Config( + new WithInclusiveCache ++ + new myproject.MyCustomConfig ++ + new DefaultRocketConfig + ) + +Then the equivalent FireChip config (in `generators/firechip/src/main/scala/TargetConfigs.scala`) based on `FireSimRocketChipConfig` +will look as follows: + +.. code-block:: scala + class FireSimCustomConfig extends Config( + new WithBootROM ++ + new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ + new WithExtMemSize(0x400000000L) ++ // 16GB + new WithoutTLMonitors ++ + new WithUARTKey ++ + new WithNICKey ++ + new WithBlockDevice ++ + new WithRocketL2TLBs(1024) ++ + new WithPerfCounters ++ + new WithoutClockGating ++ + new WithInclusiveCache ++ + new myproject.MyCustomConfig ++ + new freechips.rocketchip.system.DefaultConfig) + + +You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG`` variables. Note that if your target machine has I/O not provided in the default FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need to write a custom endpoint. diff --git a/docs/Simulation/Software-RTL-Simulators.rst b/docs/Simulation/Software-RTL-Simulators.rst index cef1b1f3..89bd337c 100644 --- a/docs/Simulation/Software-RTL-Simulators.rst +++ b/docs/Simulation/Software-RTL-Simulators.rst @@ -1,3 +1,5 @@ +.. _sw-rtl-sim-intro: + Software RTL Simulators =================================== diff --git a/docs/index.rst b/docs/index.rst index b2fa001a..6a918039 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -8,14 +8,18 @@ Welcome to Chipyard's documentation! Chipyard is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. -New to Chipyard? Jump to the :ref:`Getting Started` page for more info. +New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info. + + +.. include:: Quick-Start.rst + .. toctree:: :maxdepth: 3 :caption: Contents: :numbered: - Getting-Started/index + Chipyard-Basics/index :maxdepth: 3 :caption: Simulation: @@ -38,9 +42,9 @@ New to Chipyard? Jump to the :ref:`Getting Started` page for more info. VLSI/index :maxdepth: 3 - :caption: Advanced Usage: + :caption: Customization: :numbered: - Advanced-Usage/index + Customization/index Indices and tables ================== From 6156716876f521a43ef59f1eb78c6ae0fb066d58 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 25 Jul 2019 07:59:21 -0700 Subject: [PATCH 143/160] hammer docs outline --- docs/VLSI/HAMMER.rst | 35 ++++++++++++++++++++++++++++++++++- docs/VLSI/index.rst | 8 ++++---- 2 files changed, 38 insertions(+), 5 deletions(-) diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst index a206fe93..ffd880be 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/HAMMER.rst @@ -1,7 +1,40 @@ -HAMMER +Core HAMMER ================================ `HAMMER `__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs. HAMMER allows for reusability in ASIC design while still providing the designers leeway to make their own modifications. For more information, read the `HAMMER paper `__ and see the `GitHub repository `__. + +Actions +------- + +Actions are the top-level tasks Hammer is capable of executing (e.g. synthesis, place-and-route, etc.) + +Steps +------- + +Steps are the sub-components of actions that individually addressable in Hammer (e.g. placement in the place-and-route action). + +Hooks +------- + +Hooks are modifications to steps or actions that are programmaticly defined in a Hammer configuration. + +Tool Plugins +============ + +Hammer supports separatly managed plugins for different CAD tool vendors. + +Technology Plugins +================== + +Hammer supports separately managed plugins for different technologies. + + +Configuration +============= + +To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs. + +You can see the current set of all avaialable Hammer APIs `here `. diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 464d9828..259966d8 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -1,11 +1,11 @@ -VLSI Production +VLSI Flow ================================ -The Chipyard framework aim to provide wrappers to a general VLSI flow. -In particular, we aim to support the HAMMER flow. +The Chipyard framework aims to provide wrappers for a general VLSI flow. +In particular, we aim to support the HAMMER physical deisgn generator flow. .. toctree:: :maxdepth: 2 - :caption: VLSI Production: + :caption: VLSI Flow: HAMMER From 60f603e7c8d1dc223123d3140e1a697c8cf81728 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 25 Jul 2019 15:19:59 -0700 Subject: [PATCH 144/160] Safer LD_LIBRARY_PATH --- scripts/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 15a615d3..e743afe4 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -138,7 +138,7 @@ cd $RDIR echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" > env.sh echo "export RISCV=$RISCV" >> env.sh echo "export PATH=$RISCV/bin:$RDIR/$DTCversion:\$PATH" >> env.sh -echo "export LD_LIBRARY_PATH=$RISCV/lib:\$LD_LIBRARY_PATH" >> env.sh +echo "export LD_LIBRARY_PATH=$RISCV/lib\${LD_LIBRARY_PATH:+":${LD_LIBRARY_PATH}"}" >> env.sh echo "Toolchain Build Complete!" From c6f4f36f07c17add3bd81c8257c435cba2c85054 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 26 Jul 2019 16:34:49 -0700 Subject: [PATCH 145/160] Switch to auto-generated hammer makefile fragment (#181) * Switch to auto-generated hammer makefile fragment * Add hammer_d_deps Co-Authored-By: John Wright --- vlsi/Makefile | 147 +++++++++++++++++++++++--------------------------- vlsi/hammer | 2 +- 2 files changed, 67 insertions(+), 82 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index fc0b4ac6..519d1448 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -14,109 +14,94 @@ sim_dir=$(abspath .) ######################################################################################### include $(base_dir)/variables.mk +######################################################################################### +# vlsi types and rules +######################################################################################### +sim_name ?= vcs # needed for GenerateSimFiles, but is unused +tech_name ?= +tech_dir ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name) +SMEMS_COMP ?= $(tech_dir)/sram-compiler.json +SMEMS_CACHE ?= $(tech_dir)/sram-cache.json +SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json +MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) +OBJ_DIR ?= $(vlsi_dir)/build +ENV_YML ?= $(vlsi_dir)/bwrc-env.yml +INPUT_CONFS ?= example.yml $(dir $(tech_dir))/bwrc.yml +HAMMER_EXEC ?= ./example-vlsi + +######################################################################################### +# general rules +######################################################################################### +ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) $(extra_v_includes) +extra_v_includes = $(build_dir)/EICG_wrapper.v + +.PHONY: default verilog +default: all + +all: drc lvs + +verilog: $(ALL_RTL) + ######################################################################################### # import other necessary rules and variables ######################################################################################### include $(base_dir)/common.mk ######################################################################################### -# vlsi types and rules +# srams ######################################################################################### +SRAM_GENERATOR_CONF = $(build_dir)/sram_generator-input.yml +SRAM_CONF=$(build_dir)/sram_generator-output.json -#sim_name is unused, but GenerateSimFiles expects it -sim_name ?= vcs -tech_name ?= -tech_dir ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name) -SMEMS_COMP ?= $(tech_dir)/sram-compiler.json -SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json -MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) -OBJ_DIR ?= $(vlsi_dir)/build -ENV_YML ?= $(vlsi_dir)/bwrc-env.yml -INPUT_CONFS ?= example.yml $(dir $(tech_dir))/bwrc.yml -HAMMER_EXEC ?= ./example-vlsi +## SRAM Generator +.PHONY: sram_generator srams +srams: sram_generator +sram_generator: $(SRAM_CONF) -ROCKET_SRC_DIR=$(ROCKETCHIP_DIR)/src/main/resources/vsrc +# This should be built alongside $(SMEMS_FILE) +$(SMEMS_HAMMER): $(SMEMS_FILE) -ROCKET_SRCS = \ - $(ROCKET_SRC_DIR)/ClockDivider2.v \ - $(ROCKET_SRC_DIR)/ClockDivider3.v \ - $(ROCKET_SRC_DIR)/AsyncResetReg.v \ - $(ROCKET_SRC_DIR)/plusarg_reader.v \ - $(ROCKET_SRC_DIR)/EICG_wrapper.v \ +$(SRAM_GENERATOR_CONF): $(SMEMS_HAMMER) + mkdir -p $(dir $@) + echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@ + echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@ -ALL_RTL = $(ROCKET_SRCS) $(TOP_FILE) $(TOP_SMEMS_FILE) +$(SRAM_CONF): $(SRAM_GENERATOR_CONF) + cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator + cd $(vlsi_dir) && cp output.json $@ -CLOCK_DOMAINS = $(build_dir)/$(long_name).domains +######################################################################################### +# synthesis input configuration +######################################################################################### +SYN_CONF = $(OBJ_DIR)/inputs.yml +GENERATED_CONFS = $(SYN_CONF) $(SRAM_CONF) -.PHONY: default -default: all - -all: drc lvs - - -###################################################### SYN ############################################################ - -SYNTH_CONF = $(OBJ_DIR)/inputs.yml - -$(SYNTH_CONF): +$(SYN_CONF): $(ALL_RTL) $(extra_v_includes) $(sim_top_blackboxes) mkdir -p $(dir $@) echo "synthesis.inputs:" > $@ echo " top_module: $(TOP)" >> $@ echo " input_files:" >> $@ - for x in $(ALL_RTL); do \ + for x in $(ALL_RTL) $(extra_v_includes) `cat $(sim_top_blackboxes)`; do \ echo ' - "'$$x'"' >> $@; \ done -GENERATED_CONFS=$(SYNTH_CONF) $(SRAM_CONF) +######################################################################################### +# AUTO BUILD FLOW +######################################################################################### -.PHONY: syn synthesis -syn: $(OBJ_DIR)/syn-rundir/$(TOP).mapped.v -synthesis: syn +.PHONY: buildfile +buildfile: $(OBJ_DIR)/hammer.d +# Tip: Set HAMMER_D_DEPS to an empty string to avoid unnecessary RTL rebuilds +# TODO: make this dependency smarter so that we don't need this at all +HAMMER_D_DEPS ?= $(GENERATED_CONFS) +$(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build -$(OBJ_DIR)/syn-rundir/$(TOP).mapped.v $(OBJ_DIR)/syn-rundir/syn-output.json: $(ENV_YML) $(INPUT_CONFS) $(GENERATED_CONFS) $(ALL_RTL) - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) syn - -$(OBJ_DIR)/par-input.json: $(OBJ_DIR)/syn-rundir/syn-output.json - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $<, -p $(x)) -o $@ syn_to_par - -###################################################### PAR ############################################################ - -.PHONY: par place-and-route -par: $(OBJ_DIR)/par-rundir/$(TOP).gds -place-and-route: par - -$(OBJ_DIR)/par-rundir/$(TOP).gds $(OBJ_DIR)/par-rundir/par-output.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/syn-rundir/$(TOP).mapped.v - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) par - -$(OBJ_DIR)/drc-input.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/par-rundir/par-output.json - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$^, -p $(x)) -o $@ --obj_dir $(OBJ_DIR) par_to_drc - -###################################################### DRC ############################################################ -# TODO unimplemented -.PHONY: drc -drc: $(OBJ_DIR)/drc-rundir/drc_results.db - -$(OBJ_DIR)/drc-rundir/drc_results.db: $(OBJ_DIR)/drc-input.json $(OBJ_DIR)/par-rundir/$(TOP).gds - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) drc - -###################################################### LVS ############################################################ -# TODO unimplemented -$(OBJ_DIR)/lvs-input.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/par-rundir/par-output.json - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$^, -p $(x)) -o $@ --obj_dir $(OBJ_DIR) par_to_lvs - -.PHONY: lvs -lvs: $(OBJ_DIR)/lvs-rundir/lvs_results.rpt - -$(OBJ_DIR)/lvs-rundir/lvs_results.rpt: $(OBJ_DIR)/lvs-input.json $(OBJ_DIR)/par-rundir/$(TOP).gds - mkdir -p $(dir $@) - $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) lvs +-include $(OBJ_DIR)/hammer.d +######################################################################################### +# general cleanup rule +######################################################################################### .PHONY: clean clean: - rm -rf $(OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) generated-src + rm -rf $(OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) diff --git a/vlsi/hammer b/vlsi/hammer index 873b2c1a..a27886fb 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 873b2c1af0a54cb339a19a7c8cf3a1e7905feb58 +Subproject commit a27886fb42c121f3ba5f684acaf5856b2ec293e1 From 51bffaff45593965093529fa009d64eb0fd1b996 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sat, 27 Jul 2019 17:47:09 -0700 Subject: [PATCH 146/160] fix expedited typo --- docs/Quick-Start.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst index e319a3d4..5df1adeb 100644 --- a/docs/Quick-Start.rst +++ b/docs/Quick-Start.rst @@ -27,7 +27,7 @@ TO build the toolchains, you should run: ./scripts/build-toolchains.sh .. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchains by adding the ``esp-tools`` argument to the script above. - If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expediated installation of a pre-compiled toolchain. + If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain. What's Next? From 91107ce04370a97606557dd83429c294e9769244 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 29 Jul 2019 15:33:31 -0700 Subject: [PATCH 147/160] Ignore emacs temp files --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 8450e9b8..af37395a 100644 --- a/.gitignore +++ b/.gitignore @@ -5,6 +5,8 @@ target *.stamp *.vcd *.swp +*# +*~ .idea .DS_Store env.sh From 7dc05e678fcf308e1171a413571c931322645fbb Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Tue, 30 Jul 2019 13:58:11 -0700 Subject: [PATCH 148/160] Bump firrtl, filter Emitted and Circuit annotations to save heap space (#183) --- tools/barstools | 2 +- tools/firrtl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/barstools b/tools/barstools index 82636b3f..e3c82270 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 82636b3ff43ecf6a0f0a7d46ebc2456b31e9703f +Subproject commit e3c822709be39090ea9dad74d55239d5fc560d25 diff --git a/tools/firrtl b/tools/firrtl index 99ae1d66..84a1c7b1 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit 99ae1d6649f1731c5dec2098b10733735232b72c +Subproject commit 84a1c7b1f7311ce036cb7d3d5eb652466b87dce4 From c487ca2f66dcc512c9066f4255247f00e9f5dce5 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Wed, 31 Jul 2019 09:36:52 -0700 Subject: [PATCH 149/160] Coordinate Top and Harness generation (#168) * Coordinate Top and Harness generation * Bump barstools --- common.mk | 17 +++++++---------- tools/barstools | 2 +- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/common.mk b/common.mk index 76baf09c..2be99ffe 100644 --- a/common.mk +++ b/common.mk @@ -47,16 +47,13 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_files) # create verilog files rules and variables ######################################################################################### REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF) -HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF) +HARNESS_CONF_FLAGS = -thconf $(HARNESS_SMEMS_CONF) -$(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(TOP_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" - grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_top_blackboxes) +TOP_TARGETS = $(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes) +HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes) -# note: this depends on sim_top_blackboxes to avoid race condition where firrtl_black_box_resource_files.f is created at the same time -$(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)" - grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) +$(TOP_TARGETS) $(HARNESS_TARGETS): $(FIRRTL_FILE) $(ANNO_FILE) + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTopAndHarness -o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)" # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs MACROCOMPILER_MODE ?= --mode synflops @@ -70,7 +67,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) ######################################################################################## # remove duplicate files in blackbox/simfiles ######################################################################################## -$(sim_common_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_files) +$(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes) awk '{print $1;}' $^ | sort -u > $@ ######################################################################################### @@ -96,7 +93,7 @@ run-binary-fast: $(sim) # helper rules to run simulator with as much debug info as possible ######################################################################################### run-binary-debug: $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAG) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) run-fast: run-asm-tests-fast run-bmark-tests-fast diff --git a/tools/barstools b/tools/barstools index e3c82270..26096e07 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit e3c822709be39090ea9dad74d55239d5fc560d25 +Subproject commit 26096e07f6ce3e12b2114132c2859ef56fb0cfaf From a18d3ed92040b5bfac803216716fe10f12b84c3b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 29 Jul 2019 22:37:21 -0700 Subject: [PATCH 150/160] Remove commit-on-master check We decided this was a bad idea, and that submodules should just avoid rebase-commits. --- .circleci/config.yml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index db4eb614..1ae4a000 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -439,10 +439,20 @@ jobs: # Order and dependencies of jobs to run workflows: version: 2 + submodules-on-master: + jobs: + # Check to make sure submodule commits are on master branches + - commit-on-master-check + triggers: + - schedule: + cron: "0 0 * * *" + filters: + branches: + only: + - master + build-and-test-chipyard-integration: jobs: - # check to make sure commits are on master - - commit-on-master-check # Make the toolchains - install-riscv-toolchain From 6d8a6b2412fb3f45fef470b401275b721658c3c7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 1 Aug 2019 11:22:05 -0700 Subject: [PATCH 151/160] remove header from BoomConfigs.scala --- generators/example/src/main/scala/BoomConfigs.scala | 7 ------- 1 file changed, 7 deletions(-) diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/example/src/main/scala/BoomConfigs.scala index e8044080..f328b902 100644 --- a/generators/example/src/main/scala/BoomConfigs.scala +++ b/generators/example/src/main/scala/BoomConfigs.scala @@ -1,10 +1,3 @@ -//****************************************************************************** -// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). -// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. -//------------------------------------------------------------------------------ -// Author: Christopher Celio, Abraham Gonzalez, Ben Korpan, Jerry Zhao -//------------------------------------------------------------------------------ - package example import chisel3._ From cd48271b5314d0605bea01223a3f97b091ef63b8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 1 Aug 2019 22:33:21 -0700 Subject: [PATCH 152/160] Added DTM docs | bumped BOOM --- docs/Advanced-Usage/DTM-Debugging.rst | 48 +++++++++++++++++++++++++++ docs/Advanced-Usage/index.rst | 1 + generators/boom | 2 +- 3 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 docs/Advanced-Usage/DTM-Debugging.rst diff --git a/docs/Advanced-Usage/DTM-Debugging.rst b/docs/Advanced-Usage/DTM-Debugging.rst new file mode 100644 index 00000000..953e9cbd --- /dev/null +++ b/docs/Advanced-Usage/DTM-Debugging.rst @@ -0,0 +1,48 @@ +Debugging with DTM/JTAG +=============================== + +By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core. +Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation). +However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system. + +Creating a DTM/JTAG Config +------------------------------------------- + +First, a DTM config must be created for the system that you want to create. +This involves specifying the SoC top-level to add a DTM as well as configuring that DTM to use JTAG. + +.. code-block:: scala + + class DTMBoomConfig extends Config( + new WithDTMBoomRocketTop ++ + new WithBootROM ++ + new WithJtagDTM ++ + new boom.common.SmallBoomConfig) + +In this example, the ``WithDTMBoomRocketTop`` mixin specifies that the top-level SoC will instantiate a DTM. +The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup). +The rest of the mixins specify the rest of the system (cores, accelerators, etc). + +Starting the DTM Simulation +------------------------------------------- + +After creating the config, call the ``make`` command like the following: + +.. code-block:: bash + + cd sims/verilator + # or + cd sims/vcs + + make CONFIG=DTMBoomConfig TOP=BoomRocketTopWithDTM MODEL=TestHarnessWithDTM + +In this example, this will use the config that you previously specified, as well as set the other parameters that are needed to satisfy the build system. +After that point, you should have a JTAG enabled simulation that you can attach to using OpenOCD and GDB! + +Debugging with JTAG +------------------------------------------------------- + +Please refer to the following resources on how to debug with JTAG. + +* https://github.com/chipsalliance/rocket-chip#-debugging-with-gdb +* https://github.com/riscv/riscv-isa-sim#debugging-with-gdb diff --git a/docs/Advanced-Usage/index.rst b/docs/Advanced-Usage/index.rst index 62dd11aa..1f313e60 100644 --- a/docs/Advanced-Usage/index.rst +++ b/docs/Advanced-Usage/index.rst @@ -9,3 +9,4 @@ They expect you to know about Chisel, Parameters, Configs, etc. :caption: Getting Started: Heterogeneous-SoCs + DTM-Debugging diff --git a/generators/boom b/generators/boom index 3a06403d..609cf36e 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 3a06403df71d46f2c42f9baac134a3b2997595e5 +Subproject commit 609cf36eea7da73aad9f7abf379320615ae7e554 From 3baad45dce3e4fc90b623bc035ace567725d751c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 2 Aug 2019 21:43:23 -0700 Subject: [PATCH 153/160] update boom to master --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 609cf36e..96616414 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 609cf36eea7da73aad9f7abf379320615ae7e554 +Subproject commit 96616414e17474c4196ddea00ce9ea41d52dc143 From 717c4658ffa22717431db543bf5fc40770aca5cf Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 6 Aug 2019 10:44:31 -0700 Subject: [PATCH 154/160] update boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 96616414..4e9d496d 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 96616414e17474c4196ddea00ce9ea41d52dc143 +Subproject commit 4e9d496d3678cc5ae005669a448ae9e89f8ae847 From 34f76056effe17f939caf52a92a6b334899f09aa Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 6 Aug 2019 22:57:49 -0600 Subject: [PATCH 155/160] Update docs/Advanced-Usage/DTM-Debugging.rst Co-Authored-By: Jerry Zhao --- docs/Advanced-Usage/DTM-Debugging.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/Advanced-Usage/DTM-Debugging.rst b/docs/Advanced-Usage/DTM-Debugging.rst index 953e9cbd..bf033fec 100644 --- a/docs/Advanced-Usage/DTM-Debugging.rst +++ b/docs/Advanced-Usage/DTM-Debugging.rst @@ -3,6 +3,8 @@ Debugging with DTM/JTAG By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core. Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation). +TSI simulations use the SimSerial interface to directly write the test binary into memory, while the DTM +executes a small loop of code to write the test binary byte-wise into memory. However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system. Creating a DTM/JTAG Config From 9844fcf43bcfc3590891971934ebdfcf29bad00d Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 6 Aug 2019 22:16:46 -0700 Subject: [PATCH 156/160] re-add testsuites to compile --- .../example/src/main/scala/Generator.scala | 2 - .../example/src/main/scala/TestSuites.scala | 142 ++++++++++++++++++ 2 files changed, 142 insertions(+), 2 deletions(-) create mode 100644 generators/example/src/main/scala/TestSuites.scala diff --git a/generators/example/src/main/scala/Generator.scala b/generators/example/src/main/scala/Generator.scala index 92658038..34f16e4e 100644 --- a/generators/example/src/main/scala/Generator.scala +++ b/generators/example/src/main/scala/Generator.scala @@ -5,8 +5,6 @@ import chisel3._ import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.util.{GeneratorApp} -import boom.system.{BoomTilesKey, TestSuiteHelper} - object Generator extends GeneratorApp { // add unique test suites override def addTestSuites { diff --git a/generators/example/src/main/scala/TestSuites.scala b/generators/example/src/main/scala/TestSuites.scala new file mode 100644 index 00000000..11425bdb --- /dev/null +++ b/generators/example/src/main/scala/TestSuites.scala @@ -0,0 +1,142 @@ +package example + +import scala.collection.mutable.{LinkedHashSet} + +import freechips.rocketchip.subsystem.{RocketTilesKey} +import freechips.rocketchip.tile.{XLen} +import freechips.rocketchip.config.{Parameters} +import freechips.rocketchip.util.{GeneratorApp} +import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} + +import boom.system.{BoomTilesKey} + +/** + * A set of pre-chosen regression tests + */ +object RegressionTestSuites +{ + val rv64RegrTestNames = LinkedHashSet( + "rv64ud-v-fcvt", + "rv64ud-p-fdiv", + "rv64ud-v-fadd", + "rv64uf-v-fadd", + "rv64um-v-mul", + "rv64mi-p-breakpoint", + "rv64uc-v-rvc", + "rv64ud-v-structural", + "rv64si-p-wfi", + "rv64um-v-divw", + "rv64ua-v-lrsc", + "rv64ui-v-fence_i", + "rv64ud-v-fcvt_w", + "rv64uf-v-fmin", + "rv64ui-v-sb", + "rv64ua-v-amomax_d", + "rv64ud-v-move", + "rv64ud-v-fclass", + "rv64ua-v-amoand_d", + "rv64ua-v-amoxor_d", + "rv64si-p-sbreak", + "rv64ud-v-fmadd", + "rv64uf-v-ldst", + "rv64um-v-mulh", + "rv64si-p-dirty") + + val rv32RegrTestNames = LinkedHashSet( + "rv32mi-p-ma_addr", + "rv32mi-p-csr", + "rv32ui-p-sh", + "rv32ui-p-lh", + "rv32uc-p-rvc", + "rv32mi-p-sbreak", + "rv32ui-p-sll") +} + +/** + * Helper functions to add BOOM or Rocket tests + */ +object TestSuiteHelper +{ + import freechips.rocketchip.system.DefaultTestSuites._ + import RegressionTestSuites._ + + /** + * Add BOOM tests (asm, bmark, regression) + */ + def addBoomTestSuites(implicit p: Parameters) = { + val xlen = p(XLen) + p(BoomTilesKey).find(_.hartId == 0).map { tileParams => + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) { + TestGeneration.addSuites(env.map(rv32ud)) + } + } else if (cfg.fLen >= 64) { + TestGeneration.addSuites(env.map(rv64ud)) + TestGeneration.addSuites(env.map(rv64uf)) + TestGeneration.addSuite(rv32udBenchmarks) + } + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) { + TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + } else { + TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + } + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites(rvu.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + } + + /** + * Add Rocket tests (asm, bmark, regression) + */ + def addRocketTestSuites(implicit p: Parameters) = { + val xlen = p(XLen) + p(RocketTilesKey).find(_.hartId == 0).map { tileParams => + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv32ud)) + } else { + TestGeneration.addSuite(rv32udBenchmarks) + TestGeneration.addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv64ud)) + } + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + } +} From 80b6976be9beb13329cbd9bd5792ee00bd70cd63 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 8 Aug 2019 08:01:24 -0700 Subject: [PATCH 157/160] Add start of tool-plugin section. --- docs/VLSI/HAMMER.rst | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst index ffd880be..162b703c 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/HAMMER.rst @@ -25,6 +25,26 @@ Tool Plugins ============ Hammer supports separatly managed plugins for different CAD tool vendors. +The types of tools(in there hammer names) supported currently include: + +* synthesis +* par +* drc +* lvs +* sram_generator +* pcb + +In order to configure your tool plugin of choice you will need to set several configuration variables. +First you should select which specific tool you want to use by setting ``vlsi.core._tool`` to the name of your tool. +For example ``vlsi.core.par_tool: "innovus"``. +You will also need to point hammer to the folder that contains your tool plugin by setting ``vlsi.core._tool_path``. +This directory should include a folder with the name of the tool as specified previously, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml`` specifing the default values for any tool specific variables. +In addition you can also customize the version of the tools you use by setting ``..version`` to a tool specific string. +Looking at the tools ``defaults.yml`` will inform you if there are other variables you would like to set for your use of this tool. + +The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tools Hammer support. +This class should be a subclass of ``HammerTool``, which will be a subclass of ``HammerTool``. + Technology Plugins ================== @@ -37,4 +57,4 @@ Configuration To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs. -You can see the current set of all avaialable Hammer APIs `here `. +You can see the current set of all avaialable Hammer APIs `here `__. From 9538257be14e421d171c5e35e8d262f12cc94ec9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 8 Aug 2019 11:19:57 -0700 Subject: [PATCH 158/160] grammer + spell check --- docs/VLSI/HAMMER.rst | 16 +++++++--------- docs/VLSI/index.rst | 2 +- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst index 162b703c..c0c77824 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/HAMMER.rst @@ -19,13 +19,13 @@ Steps are the sub-components of actions that individually addressable in Hammer Hooks ------- -Hooks are modifications to steps or actions that are programmaticly defined in a Hammer configuration. +Hooks are modifications to steps or actions that are programmatically defined in a Hammer configuration. Tool Plugins ============ -Hammer supports separatly managed plugins for different CAD tool vendors. -The types of tools(in there hammer names) supported currently include: +Hammer supports separately managed plugins for different CAD tool vendors. +The types of tools (in there hammer names) supported currently include: * synthesis * par @@ -34,27 +34,25 @@ The types of tools(in there hammer names) supported currently include: * sram_generator * pcb -In order to configure your tool plugin of choice you will need to set several configuration variables. -First you should select which specific tool you want to use by setting ``vlsi.core._tool`` to the name of your tool. +In order to configure your tool plugin of choice, you will need to set several configuration variables. +First, you should select which specific tool you want to use by setting ``vlsi.core._tool`` to the name of your tool. For example ``vlsi.core.par_tool: "innovus"``. You will also need to point hammer to the folder that contains your tool plugin by setting ``vlsi.core._tool_path``. -This directory should include a folder with the name of the tool as specified previously, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml`` specifing the default values for any tool specific variables. +This directory should include a folder with the name of the tool as specified previously, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml`` specifying the default values for any tool specific variables. In addition you can also customize the version of the tools you use by setting ``..version`` to a tool specific string. Looking at the tools ``defaults.yml`` will inform you if there are other variables you would like to set for your use of this tool. The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tools Hammer support. This class should be a subclass of ``HammerTool``, which will be a subclass of ``HammerTool``. - Technology Plugins ================== Hammer supports separately managed plugins for different technologies. - Configuration ============= To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs. -You can see the current set of all avaialable Hammer APIs `here `__. +You can see the current set of all available Hammer APIs `here `__. diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 259966d8..f8bdb7a8 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -2,7 +2,7 @@ VLSI Flow ================================ The Chipyard framework aims to provide wrappers for a general VLSI flow. -In particular, we aim to support the HAMMER physical deisgn generator flow. +In particular, we aim to support the HAMMER physical design generator flow. .. toctree:: :maxdepth: 2 From 8ba73d13b8bcf93e2a9c616dd2be54169086f56b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 8 Aug 2019 17:19:10 -0700 Subject: [PATCH 159/160] fix the doc warnings --- docs/Chipyard-Basics/Building-A-Chip.rst | 1 + docs/Customization/index.rst | 1 + docs/Quick-Start.rst | 2 +- docs/Simulation/FPGA-Accelerated-Simulators.rst | 10 ++++++---- docs/index.rst | 2 -- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/docs/Chipyard-Basics/Building-A-Chip.rst b/docs/Chipyard-Basics/Building-A-Chip.rst index dc2d37ce..3fbbd9ea 100644 --- a/docs/Chipyard-Basics/Building-A-Chip.rst +++ b/docs/Chipyard-Basics/Building-A-Chip.rst @@ -2,4 +2,5 @@ Building A Chip ============================== + TODO diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index c8cb9cc3..8d61801e 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -12,6 +12,7 @@ Hit next to get started! .. toctree:: :maxdepth: 2 :caption: Customization: + Heterogeneous-SoCs Adding-An-Accelerator Memory-Hierarchy diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst index 26589204..e8ead617 100644 --- a/docs/Quick-Start.rst +++ b/docs/Quick-Start.rst @@ -21,7 +21,7 @@ We need to install the RISC-V toolchain in order to be able to run RISC-V progra This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. To build the toolchains, you should run: -:: +.. code-block:: shell ./scripts/build-toolchains.sh diff --git a/docs/Simulation/FPGA-Accelerated-Simulators.rst b/docs/Simulation/FPGA-Accelerated-Simulators.rst index ed13d629..29f42880 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulators.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulators.rst @@ -48,24 +48,26 @@ Current Limitations: ++++++++++++++++++++ FireSim integration in Chipyard is still a work in progress. Presently, you -cannot build a FireSim simulator from any generator project in Chipyard except ``firechip``, +cannot build a FireSim simulator from any generator project in Chipyard except ``firechip``, which properly invokes MIDAS on the target RTL. In the interim, workaround this limitation by importing Config and Module -classes from other generator projects into FireChip. For example, assuming you Chipyard +classes from other generator projects into FireChip. For example, assuming you Chipyard config looks as following: .. code-block:: scala + class CustomConfig extends Config( new WithInclusiveCache ++ new myproject.MyCustomConfig ++ new DefaultRocketConfig ) -Then the equivalent FireChip config (in `generators/firechip/src/main/scala/TargetConfigs.scala`) based on `FireSimRocketChipConfig` +Then the equivalent FireChip config (in `generators/firechip/src/main/scala/TargetConfigs.scala`) based on `FireSimRocketChipConfig` will look as follows: .. code-block:: scala + class FireSimCustomConfig extends Config( new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ @@ -80,7 +82,7 @@ will look as follows: new WithInclusiveCache ++ new myproject.MyCustomConfig ++ new freechips.rocketchip.system.DefaultConfig) - + You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG`` variables. Note that if your target machine has I/O not provided in the default diff --git a/docs/index.rst b/docs/index.rst index c44f118f..1f41b4ed 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -10,10 +10,8 @@ Chipyard is a a framework for designing and evaluating full-system hardware usin It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info. - .. include:: Quick-Start.rst - .. toctree:: :maxdepth: 3 :caption: Contents: From 5f3ff3627b15e25a7102fee07756d52e4b7ad3e2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 9 Aug 2019 10:18:50 -0700 Subject: [PATCH 160/160] update bullet points in quick-start --- docs/Quick-Start.rst | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst index e8ead617..936597e6 100644 --- a/docs/Quick-Start.rst +++ b/docs/Quick-Start.rst @@ -33,10 +33,17 @@ What's Next? ------------------------------------------- This depends on what you are planning to do with Chipyard. -- If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`. -- If you intend to build one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. -- If you intend to add a new accelerator, go to :ref:`adding-an-accelerator` and follow the instructions. -- If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. -- If you intend to run a simulation of a custom Chipyard SoC Configuration, go to <> and follow the instructions. -- If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. -- If you intend to run a VLSI flow using one of the vanilla Chipyard examples, go to <> and follow the instructions. + +* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`. + +* If you intend to build one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. + +* If you intend to add a new accelerator, go to :ref:`adding-an-accelerator` and follow the instructions. + +* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. + +* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to <> and follow the instructions. + +* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. + +* If you intend to run a VLSI flow using one of the vanilla Chipyard examples, go to <> and follow the instructions.