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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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Schuyler Eldridge
2019-10-11 11:20:42 -04:00
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docs/Tools/Chisel.rst
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Chisel
===========================
`Chisel <https://chisel.eecs.berkeley.edu/>`__ is an open-source hardware description language embedded in Scala.
`Chisel <https://chisel-lang.org/>`__ is an open-source hardware description language embedded in Scala.
It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM.
After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog.
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See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog.
For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp <https://github.com/freechipsproject/chisel-bootcamp>`__.
Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel.eecs.berkeley.edu/>`__.
Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel-lang.org/>`__.