wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

[firechip] Update regfile optimization mixins

Browse Source
This commit is contained in:
David Biancolin
2019-09-09 06:41:15 +00:00
parent d4be303df5
commit 9bf174afb3
2 changed files with 13 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
generators/firechip/src/main/scala/TargetMixins.scala
View File

@@ -105,10 +105,10 @@ trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
}
trait CanHaveBoomMultiCycleRegfileImp {
val outer: boom.system.BoomRocketSubsystem
val cores = outer.boomTiles.map(tile => tile.module.core)
cores.foreach({ core =>
trait CanHaveMultiCycleRegfileImp {
val outer: utilities.HasBoomAndRocketTiles
val boomCores = outer.boomTiles.map(tile => tile.module.core)
boomCores.foreach({ core =>
core.iregfile match {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case _ => Nil
@@ -118,11 +118,8 @@ trait CanHaveBoomMultiCycleRegfileImp {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case _ => Nil
}
})
})
}
trait CanHaveRocketMultiCycleRegfileImp {
val outer: RocketSubsystem
outer.rocketTiles.foreach({ tile =>
annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf))
tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))