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Merge remote-tracking branch 'origin/dev' into chisel-3.5-published

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abejgonzalez
2022-01-21 14:21:53 -08:00
parent 0c369c4782 9adb1036a3
commit 98b4ba96e4
2 changed files with 4 additions and 2 deletions
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2
generators/firechip/src/test/scala/ScalaTestSuite.scala
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@@ -65,7 +65,7 @@ abstract class FireSimTestSuite(
Await result (Future sequence subresults, Duration.Inf) Await result (Future sequence subresults, Duration.Inf)
} }
results.flatten foreach { case (name, exitcode) => results.flatten foreach { case (name, exitcode) =>
assert(exitcode == 0, "Failed $name") assert(exitcode == 0, s"Failed $name")
} }
} }
} else { } else {

4
variables.mk
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@@ -25,7 +25,9 @@ HELP_PROJECT_VARIABLES = \
HELP_SIMULATION_VARIABLES = \ HELP_SIMULATION_VARIABLES = \
" BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \ " BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \
" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" " VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \
" timeout_cycles = number of clock cycles before simulator times out, defaults to 10000000" \
" bmark_timeout_cycles = number of clock cycles before benchmark simulator times out, defaults to 100000000"
# include default simulation rules # include default simulation rules
HELP_COMMANDS = \ HELP_COMMANDS = \