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Filter compiler libraries before mapping

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The filter is always by family and maskability and then by any
integral mappings.
This commit is contained in:
Colin Schmidt
2019-03-16 02:42:05 -07:00
committed by Colin Schmidt
parent a0510e6664
commit 98a410812c
2 changed files with 49 additions and 7 deletions
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14
macros/src/main/scala/Utils.scala
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@@ -78,9 +78,18 @@ object Utils {
}
def readConfFromString(str: String): Seq[mdf.macrolib.Macro] = {
MemConf.fromString(str).map { m:MemConf =>
SRAMMacro(m.name, m.width, m.depth, "", Utils.portSpecToMacroPort(m.width, m.depth, m.maskGranularity, m.ports), Seq.empty[MacroExtraPort])
SRAMMacro(m.name, m.width, m.depth, Utils.portSpecToFamily(m.ports), Utils.portSpecToMacroPort(m.width, m.depth, m.maskGranularity, m.ports), Seq.empty[MacroExtraPort])
}
}
def portSpecToFamily(ports: Seq[MemPort]): String = {
val numR = ports.count(_ match { case ReadPort => true; case _ => false})
val numW = ports.count(_ match { case WritePort|MaskedWritePort => true; case _ => false})
val numRW = ports.count(_ match { case ReadWritePort|MaskedReadWritePort => true; case _ => false})
val numRStr = if(numR > 0) s"${numR}r" else ""
val numWStr = if(numW > 0) s"${numW}w" else ""
val numRWStr = if(numRW > 0) s"${numRW}rw" else ""
return numRStr + numWStr + numRWStr
}
// This translates between two represenations of ports
def portSpecToMacroPort(width: Int, depth: Int, maskGran: Option[Int], ports: Seq[MemPort]): Seq[MacroPort] = {
var numR = 0
@@ -160,6 +169,9 @@ object Utils {
for (g <- s.groups; d <- g.depth; w <- g.width; vt <- g.vt)
yield mdf.macrolib.SRAMMacro(makeName(g, d, w, vt), w, d, g.family, g.ports.map(_.copy(width=Some(w), depth=Some(d))), g.extraPorts)
}
def buildSRAMMacro(g: mdf.macrolib.SRAMGroup, d: Int, w: Int, vt: String): mdf.macrolib.SRAMMacro = {
return mdf.macrolib.SRAMMacro(makeName(g, d, w, vt), w, d, g.family, g.ports.map(_.copy(width=Some(w), depth=Some(d))), g.extraPorts)
}
def makeName(g: mdf.macrolib.SRAMGroup, depth: Int, width: Int, vt: String): String = {
g.name.foldLeft(""){ (builder, next) =>
next match {