wu-arch/chipyard
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Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
This commit is contained in:
Jerry Zhao
2023-07-05 14:55:03 -07:00
parent 927d236d1f
commit 984ea24650
4 changed files with 5 additions and 5 deletions
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4
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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@@ -21,7 +21,7 @@ case class ChipyardPRCIControlParams(
baseAddress: BigInt = 0x100000, baseAddress: BigInt = 0x100000,
enableTileClockGating: Boolean = true, enableTileClockGating: Boolean = true,
enableTileResetSetting: Boolean = true, enableTileResetSetting: Boolean = true,
enableResetSynchronizers: Boolean = true // this should only be disable to work around verilator async-reset initialziation problems enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems
) { ) {
def generatePRCIXBar = enableTileClockGating || enableTileResetSetting def generatePRCIXBar = enableTileClockGating || enableTileResetSetting
} }
@@ -110,7 +110,7 @@ PROPERLY AS ASIC OR FPGA.
THESE SHOULD ONLY BE DISABLED TO WORK AROUND THESE SHOULD ONLY BE DISABLED TO WORK AROUND
LIMITATIONS IN ASYNC RESET INITIALIZATION IN LIMITATIONS IN ASYNC RESET INITIALIZATION IN
RTL SIMULATORS. RTL SIMULATORS, NAMELY VERILATOR.
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
""" + Console.RESET) """ + Console.RESET)

2
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -35,7 +35,7 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithSPIIOCells ++ new chipyard.iobinders.WithSPIIOCells ++
new chipyard.iobinders.WithExtInterruptIOCells ++ new chipyard.iobinders.WithExtInterruptIOCells ++
new chipyard.iobinders.WithCustomBootPin ++ new chipyard.iobinders.WithCustomBootPin ++
// The "punchtrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO // The "punchthrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO
// Instead, they directly pass through the DigitalTop ports to ports in the ChipTop // Instead, they directly pass through the DigitalTop ports to ports in the ChipTop
new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithAXI4MemPunchthrough ++
new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ new chipyard.iobinders.WithAXI4MMIOPunchthrough ++

2
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -60,7 +60,7 @@ class ChipBringupHostConfig extends Config(
new testchipip.WithSerialTLWidth(4) ++ // match width with the chip new testchipip.WithSerialTLWidth(4) ++ // match width with the chip
new testchipip.WithSerialTLMem(base = 0x0, size = 0x80000000L, // accessible memory of the chip that doesn't come from the tethered host new testchipip.WithSerialTLMem(base = 0x0, size = 0x80000000L, // accessible memory of the chip that doesn't come from the tethered host
idBits = 4, isMainMemory = false) ++ // This assumes off-chip mem starts at 0x8000_0000 idBits = 4, isMainMemory = false) ++ // This assumes off-chip mem starts at 0x8000_0000
new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 50MHz clock new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
//============================ //============================
// Setup bus topology on the bringup system // Setup bus topology on the bringup system

0
generators/chipyard/src/main/scala/harness/MultiHarnesBinders.scala → generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
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