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using dp(ExtTLMem).get.master.beatBytes to obtain MemoryBus data width

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jerryho
2023-05-27 18:12:56 +08:00
parent 34adb9943b
commit 9844deb172
1 changed files with 2 additions and 2 deletions
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4
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -84,8 +84,8 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
name = "chip_ddr", name = "chip_ddr",
sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits) sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
))))) )))))
ddrNode := TLWidthWidget(dp(XLen)/8) := ddrClient ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient
// module implementation // module implementation
override lazy val module = new VCU118FPGATestHarnessImp(this) override lazy val module = new VCU118FPGATestHarnessImp(this)
} }