Merge branch 'dev' of github.com:ucb-bar/chipyard into custom-core-doc

.circleci/config.yml

@@ -287,6 +287,11 @@ jobs:
         steps:
             - prepare-rtl:
                 project-key: "chipyard-spiflashread"
+    prepare-chipyard-mmios:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                project-key: "chipyard-mmios"
     chipyard-rocket-run-tests:
         executor: main-env
         steps:
@@ -531,6 +536,10 @@ workflows:
                     - install-riscv-toolchain
                     - install-verilator
 
+            - prepare-chipyard-mmios:
+                requires:
+                    - install-riscv-toolchain
+
             # Run the respective tests
 
             # Run the example tests

.circleci/defaults.sh

@@ -47,23 +47,25 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
 
 # key value store to get the build strings
 declare -A mapping
-mapping["chipyard-rocket"]="SUB_PROJECT=chipyard"
+mapping["chipyard-rocket"]=""
-mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig"
+mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
-mapping["chipyard-streaming-fir"]="SUB_PROJECT=chipyard CONFIG=StreamingFIRRocketConfig"
+mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig"
-mapping["chipyard-streaming-passthrough"]="SUB_PROJECT=chipyard CONFIG=StreamingPassthroughRocketConfig"
+mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig"
-mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig"
+mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig"
-mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig"
+mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig"
-mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig"
+mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
-mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig"
+mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
-mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig"
+mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
-mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig"
+mapping["chipyard-ariane"]=" CONFIG=ArianeConfig"
-mapping["chipyard-spiflashread"]="SUB_PROJECT=chipyard CONFIG=LargeSPIFlashROMRocketConfig"
+mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
-mapping["chipyard-spiflashwrite"]="SUB_PROJECT=chipyard CONFIG=SmallSPIFlashRocketConfig"
+mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
-mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem"
+mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
-mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem"
+mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem"
-mapping["chipyard-nvdla"]="SUB_PROJECT=chipyard CONFIG=SmallNVDLARocketConfig"
+mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig TOP=TraceGenSystem"
+mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"
 mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
 mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"
 mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
 mapping["icenet"]="SUB_PROJECT=icenet"
 mapping["testchipip"]="SUB_PROJECT=testchipip"
+

docs/Customization/Heterogeneous-SoCs.rst

@@ -10,7 +10,7 @@ Creating a Rocket and BOOM System
 -------------------------------------------
 
 Instantiating an SoC with Rocket and BOOM cores is all done with the configuration system and two specific config fragments.
-Both BOOM and Rocket have config fragments labelled ``WithNBoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_.
+Both BOOM and Rocket have config fragments labelled ``WithN{Small|Medium|Large|etc.}BoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_.
 When used together you can create a heterogeneous system.
 
 The following example shows a dual core BOOM with a single core Rocket.
@@ -20,52 +20,6 @@ The following example shows a dual core BOOM with a single core Rocket.
     :start-after: DOC include start: DualBoomAndRocket
     :end-before: DOC include end: DualBoomAndRocket
 
-In this example, the ``WithNBoomCores`` and ``WithNBigCores`` config fragments set up the default parameters for the multiple BOOM and Rocket cores, respectively.
-However, for BOOM, an extra config fragment called ``WithLargeBooms`` is added to override the default parameters with a different set of more common default parameters.
-This config fragment applies to all BOOM cores in the system and changes the parameters for each.
-
-Great! Now you have a heterogeneous setup with BOOMs and Rockets.
-The final thing you need to make this system work is to renumber the ``hartId``'s of the cores so that each core has a unique ``hartId`` (a ``hartId`` is the hardware thread id of the core).
-The ``WithRenumberHarts`` config fragment solves this by assigning a unique ``hartId`` to all cores in the system (it can label the Rocket cores first or the BOOM cores first).
-The reason this is needed is because by default the ``WithN...Cores(X)`` config fragment assumes that there are only BOOM or only Rocket cores in the system.
-Thus, without the ``WithRenumberHarts`` config fragment, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``.
-
-Another alternative option to create a multi heterogeneous core system is to override the parameters yourself so you can specify the core parameters per core.
-The config fragment to add to your system would look something like the following.
-
-.. code-block:: scala
-
-    // create 6 cores (4 boom and 2 rocket)
-    class WithHeterCoresSetup extends Config((site, here, up) => {
-      case BoomTilesKey => {
-        val boomTile0 = BoomTileParams(...) // params for boom core 0
-        val boomTile1 = BoomTileParams(...) // params for boom core 1
-        val boomTile2 = BoomTileParams(...) // params for boom core 2
-        val boomTile3 = BoomTileParams(...) // params for boom core 3
-        Seq(boomTile0, boomTile1, boomTile2, boomTile3)
-      }
-
-      case RocketTilesKey => {
-        val rocketTile0 = RocketTileParams(...) // params for rocket core 0
-        val rocketTile1 = RocketTileParams(...) // params for rocket core 1
-        Seq(rocketTile0, rocketTile1)
-      }
-    })
-
-Then you could use this new config fragment like the following.
-
-.. code-block:: scala
-
-    class SixCoreConfig extends Config(
-      new WithTSI ++
-      new WithBootROM ++
-      new WithUART ++
-      new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-      new freechips.rocketchip.subsystem.WithNoSlavePort ++
-      new WithHeterCoresSetup ++
-      new freechips.rocketchip.system.BaseConfig)
-
-Note, in this setup you need to specify the ``hartId`` of each core in the "TileParams", where each ``hartId`` is unique.
 
 Adding Hwachas
 -------------------------------------------
@@ -94,8 +48,7 @@ An example is shown below with two BOOM cores, and one Rocket tile with a RoCC a
     :start-after: DOC include start: DualBoomAndRocketOneHwacha
     :end-before: DOC include end: DualBoomAndRocketOneHwacha
 
-In this example, the ``WithRenumberHarts`` relabels the ``hartId``'s of all the BOOM/Rocket cores.
+The ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core).
-Then after that is applied to the parameters, the ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core).
 Finally, the ``WithMultiRoCC`` config fragment is called.
 This config fragment sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default.
 This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter.

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -25,7 +25,7 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
 
-import chipyard.{BuildTop, BuildSystem}
+import chipyard.{BuildTop, BuildSystem, TestSuitesKey, TestSuiteHelper}
 
 /**
  * TODO: Why do we need this?
@@ -51,9 +51,9 @@ class WithGPIO extends Config((site, here, up) => {
 })
 // DOC include end: gpio config fragment
 
-class WithUART extends Config((site, here, up) => {
+class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => {
   case PeripheryUARTKey => Seq(
-    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256))
+    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
 })
 
 class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => {
@@ -99,16 +99,18 @@ class WithMultiRoCC extends Config((site, here, up) => {
  *
  * @param harts harts to specify which will get a Hwacha
  */
-class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
+class WithMultiRoCCHwacha(harts: Int*) extends Config(
-  case MultiRoCCKey => {
+  new chipyard.config.WithHwachaTest ++
-    up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
+  new Config((site, here, up) => {
-      (i -> Seq((p: Parameters) => {
+    case MultiRoCCKey => {
-        LazyModule(new Hwacha()(p)).suggestName("hwacha")
+      up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
-      }))
+        (i -> Seq((p: Parameters) => {
+          LazyModule(new Hwacha()(p)).suggestName("hwacha")
+        }))
+      }
     }
-  }
+  })
-})
+)
-
 
 class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
@@ -130,3 +132,27 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
     case other => other
   }
 })
+
+class WithRocketICacheScratchpad extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x100000 + r.hartId * 0x10000))))
+  }
+})
+
+class WithRocketDCacheScratchpad extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(dcache = r.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + r.hartId * 0x10000))))
+  }
+})
+
+class WithHwachaTest extends Config((site, here, up) => {
+  case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
+    up(TestSuitesKey).apply(tileParams, suiteHelper, p)
+    import hwacha.HwachaTestSuites._
+    suiteHelper.addSuites(rv64uv.map(_("p")))
+    suiteHelper.addSuites(rv64uv.map(_("vp")))
+    suiteHelper.addSuite(rv64sv("p"))
+    suiteHelper.addSuite(hwachaBmarks)
+    "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha"
+  }
+})

generators/chipyard/src/main/scala/IOBinders.scala

@@ -5,11 +5,11 @@ import chisel3._
 import chisel3.experimental.{Analog, IO}
 
 import freechips.rocketchip.config.{Field, Config, Parameters}
-import freechips.rocketchip.diplomacy.{LazyModule}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.{SimAXIMem}
-import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters}
+import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
 import freechips.rocketchip.util._
 import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
 
@@ -52,6 +52,21 @@ case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]](
   Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil)
 )
 
+// Note: The parameters instance is accessible only through LazyModule
+// or LazyModuleImpLike. The self-type requirement in traits like
+// CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder
+// As a result, IOBinders only work on Modules which inherit LazyModule or
+// or LazyModuleImpLike
+object GetSystemParameters {
+  def apply(s: Any): Parameters = {
+    s match {
+      case s: LazyModule => s.p
+      case s: LazyModuleImpLike => s.p
+      case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike")
+    }
+  }
+}
+
 // This macro overrides previous matches on some Top mixin. This is useful for
 // binders which drive IO, since those typically cannot be composed
 class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
@@ -185,10 +200,19 @@ object AddIOCells {
     (port, ios)
   }
 
-  def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = {
+  def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = {
     io.zip(node.in).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => {
-      val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_mem_axi4_${i}"))
+      val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_slave_${i}"))
-      port.suggestName(s"mem_axi4_${i}")
+      port.suggestName(s"${name}_axi4_slave_${i}")
+      (port, edge, ios)
+    }}
+  }
+  def axi4(io: Seq[AXI4Bundle], node: AXI4MasterNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = {
+    io.zip(node.out).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => {
+      //val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_master_${i}"))
+      val port = IO(Flipped(AXI4Bundle(edge.bundle)))
+      val ios = IOCell.generateFromSignal(mem_axi4, port, Some(s"iocell_${name}_axi4_master_${i}"))
+      port.suggestName(s"${name}_axi4_master_${i}")
       (port, edge, ios)
     }}
   }
@@ -256,22 +280,19 @@ class WithSimNIC extends OverrideIOBinder({
   (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil
 })
 
-// Note: The parameters instance is accessible only through the BaseSubsystem
-// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The
-// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it
-// accessible to the IOBinder
 // DOC include start: WithSimAXIMem
 class WithSimAXIMem extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
+  (system: CanHaveMasterAXI4MemPort) => {
-    val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node)
+    implicit val p: Parameters = GetSystemParameters(system)
+    val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem")
     // TODO: we are inlining the connectMem method of SimAXIMem because
     //   it takes in a dut rather than seq of axi4 ports
     val harnessFn = (th: chipyard.TestHarness) => {
       peiTuples.map { case (port, edge, ios) =>
-        val mem = LazyModule(new SimAXIMem(edge, size = system.p(ExtMem).get.master.size)(system.p))
+        val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size))
         Module(mem.module).suggestName("mem")
         mem.io_axi4.head <> port
-        }
+      }
       Nil
     }
     Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn)))
@@ -280,12 +301,13 @@ class WithSimAXIMem extends OverrideIOBinder({
 // DOC include end: WithSimAXIMem
 
 class WithBlackBoxSimMem extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
+  (system: CanHaveMasterAXI4MemPort) => {
-    val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node)
+    implicit val p: Parameters = GetSystemParameters(system)
+    val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem")
     val harnessFn = (th: chipyard.TestHarness) => {
       peiTuples.map { case (port, edge, ios) =>
-        val memSize = system.p(ExtMem).get.master.size
+        val memSize = p(ExtMem).get.master.size
-        val lineSize = system.p(CacheBlockBytes)
+        val lineSize = p(CacheBlockBytes)
         val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle))
         mem.io.axi <> port
         mem.io.clock := th.clock
@@ -298,7 +320,19 @@ class WithBlackBoxSimMem extends OverrideIOBinder({
 })
 
 class WithSimAXIMMIO extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MMIOPort with BaseSubsystem) => SimAXIMem.connectMMIO(system)(system.p); Nil
+  (system: CanHaveMasterAXI4MMIOPort) => {
+    implicit val p: Parameters = GetSystemParameters(system)
+    val peiTuples = AddIOCells.axi4(system.mmio_axi4, system.mmioAXI4Node, "mmio_mem")
+    val harnessFn = (th: chipyard.TestHarness) => {
+      peiTuples.zipWithIndex.map { case ((port, edge, ios), i) =>
+        val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096))
+        Module(mmio_mem.module).suggestName(s"mmio_mem_${i}")
+        mmio_mem.io_axi4.head <> port
+      }
+      Nil
+    }
+    Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn)))
+  }
 })
 
 class WithDontTouchPorts extends OverrideIOBinder({
@@ -315,21 +349,16 @@ class WithTieOffInterrupts extends OverrideIOBinder({
 })
 
 class WithTieOffL2FBusAXI extends OverrideIOBinder({
-  (system: CanHaveSlaveAXI4Port with BaseSubsystem) => {
+  (system: CanHaveSlaveAXI4Port) => {
-    system.l2_frontend_bus_axi4.foreach(axi => {
+    val peiTuples = AddIOCells.axi4(system.l2_frontend_bus_axi4, system.l2FrontendAXI4Node, "l2_fbus")
-      axi.tieoff()
+    val harnessFn = (th: chipyard.TestHarness) => {
-      experimental.DataMirror.directionOf(axi.ar.ready) match {
+      peiTuples.zipWithIndex.map { case ((port, edge, ios), i) =>
-        case ActualDirection.Input =>
+        port := DontCare // tieoff doesn't completely tie-off, for some reason
-          axi.r.bits := DontCare
+        port.tieoff()
-          axi.b.bits := DontCare
-        case ActualDirection.Output =>
-          axi.aw.bits := DontCare
-          axi.ar.bits := DontCare
-          axi.w.bits := DontCare
-        case _ => throw new Exception("Unknown AXI port direction")
       }
-    })
+      Nil
-    Nil
+    }
+    Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn)))
   }
 })
 

generators/chipyard/src/main/scala/TestSuites.scala

@@ -3,8 +3,8 @@ package chipyard
 import scala.collection.mutable.{LinkedHashSet}
 
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.tile.{XLen}
+import freechips.rocketchip.tile.{XLen, TileParams}
-import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
 import boom.common.{BoomTileAttachParams}
@@ -64,133 +64,51 @@ class TestSuiteHelper
   def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
 
   /**
-  * Add BOOM tests (asm, bmark, regression)
+  * Add generic tests (asm, bmark, regression) for all cores.
   */
-  def addBoomTestSuites(implicit p: Parameters) = {
+  def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = {
     val xlen = p(XLen)
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
+    tiles.find(_.hartId == 0).map { tileParams =>
-      case tp: BoomTileAttachParams => {
+      val coreParams = tileParams.core
-        val tileParams = tp.tileParams
+      val vm = coreParams.useVM
-        val coreParams = tileParams.core
+      val env = if (vm) List("p","v") else List("p")
-        val vm = coreParams.useVM
+      coreParams.fpu foreach { case cfg =>
-        val env = if (vm) List("p","v") else List("p")
+        if (xlen == 32) {
-        coreParams.fpu foreach { case cfg =>
+          addSuites(env.map(rv32uf))
-          if (xlen == 32) {
+          if (cfg.fLen >= 64)
-            addSuites(env.map(rv32uf))
+            addSuites(env.map(rv32ud))
-            if (cfg.fLen >= 64) {
+        } else {
-              addSuites(env.map(rv32ud))
+          addSuite(rv32udBenchmarks)
-            }
+          addSuites(env.map(rv64uf))
-          } else if (cfg.fLen >= 64) {
+          if (cfg.fLen >= 64)
             addSuites(env.map(rv64ud))
-            addSuites(env.map(rv64uf))
-            addSuite(rv32udBenchmarks)
-          }
         }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          } else {
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-          }
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites(rvu.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
       }
-      case _ =>
+      if (coreParams.useAtomics) {
-    }
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-  }
+          addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-
+        else
-  /**
+          addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-  * Add Rocket tests (asm, bmark, regression)
-  */
-  def addRocketTestSuites(implicit p: Parameters) = {
-    val xlen = p(XLen)
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
-      case tp: RocketTileAttachParams => {
-        val tileParams = tp.tileParams
-        val coreParams = tileParams.core
-        val vm = coreParams.useVM
-        val env = if (vm) List("p","v") else List("p")
-        coreParams.fpu foreach { case cfg =>
-          if (xlen == 32) {
-            addSuites(env.map(rv32uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv32ud))
-          } else {
-            addSuite(rv32udBenchmarks)
-            addSuites(env.map(rv64uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv64ud))
-          }
-        }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          else
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
       }
-      case _ =>
+      if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-    }
+      val (rvi, rvu) =
-  }
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
 
-  /**
+      addSuites(rvi.map(_("p")))
-  * Add Ariane tests (asm, bmark, regression)
+      addSuites(rvu.map(_("p")))
-  */
+      addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-  def addArianeTestSuites(implicit p: Parameters) = {
+      addSuite(benchmarks)
-    val xlen = p(XLen)
+      addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
-      case tp: ArianeTileAttachParams => {
-        val tileParams = tp.tileParams
-        val coreParams = tileParams.core
-        val vm = coreParams.useVM
-        val env = if (vm) List("p","v") else List("p")
-        coreParams.fpu foreach { case cfg =>
-          if (xlen == 32) {
-            addSuites(env.map(rv32uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv32ud))
-          } else {
-            addSuite(rv32udBenchmarks)
-            addSuites(env.map(rv64uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv64ud))
-          }
-        }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          else
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
-      }
-      case _ =>
     }
   }
 }
+
+/**
+ * Config key of custom test suite.
+ */
+case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => String]((tiles, helper, p) => {
+  helper.addGenericTestSuites(tiles)(p)
+  // Return an empty string as makefile additional snippets
+  ""
+})

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -0,0 +1,26 @@
+package chipyard.config
+
+import freechips.rocketchip.config.{Config}
+
+// --------------
+// Chipyard abstract ("base") configuration
+// NOTE: This configuration is NOT INSTANTIABLE, as it defines a empty system with no tiles
+// --------------
+
+class AbstractConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a blackbox DRAMSim model
+  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
+  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
+  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new chipyard.config.WithBootROM ++                             // use default bootrom
+  new chipyard.config.WithUART ++                                // add a UART
+  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
+  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
+

generators/chipyard/src/main/scala/config/ArianeConfigs.scala

@@ -9,34 +9,11 @@ import freechips.rocketchip.config.{Config}
 // ---------------------
 
 class ArianeConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithSimAXIMem ++                        // drive the master AXI4 memory with a SimAXIMem
-  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
-  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
-  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithBootROM ++                             // use default bootrom
-  new chipyard.config.WithUART ++                                // add a UART
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
-  new ariane.WithNArianeCores(1) ++                              // single Ariane core
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
-  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
 
 class dmiArianeConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTiedOffSerial ++          // Tie off the serial port, override default instantiation of SimSerial
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation, override default tie-off debug
-  new chipyard.iobinders.WithSimAXIMem ++
+  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.iobinders.WithTiedOffSerial ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new ariane.WithNArianeCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -7,151 +7,39 @@ import freechips.rocketchip.config.{Config}
 // ---------------------
 
 class SmallBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
-  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
-  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a SimAXIMem
-  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
-  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
-  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithBootROM ++                             // use default bootrom
-  new chipyard.config.WithUART ++                                // add a UART
-  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
   new boom.common.WithNSmallBooms(1) ++                          // small boom config
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
 
 class MediumBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new boom.common.WithNMediumBooms(1) ++                         // medium boom config
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new boom.common.WithNMediumBooms(1) ++                             // medium boom config
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 
 class LargeBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new boom.common.WithNLargeBooms(1) ++                          // large boom config
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class MegaBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new boom.common.WithNMegaBooms(1) ++                           // mega boom config
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new boom.common.WithNMegaBooms(1) ++                        // mega boom config
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 
 class DualSmallBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new boom.common.WithNSmallBooms(2) ++                          // 2 boom cores
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new boom.common.WithNSmallBooms(2) ++                         // 2 boom cores
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 
 class HwachaLargeBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.config.WithHwachaTest ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new hwacha.DefaultHwachaConfig ++                         // use Hwacha vector accelerator
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new boom.common.WithNLargeBooms(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class LoopbackNICLargeBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithLoopbackNIC ++                      // drive NIC IOs with loopback
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new icenet.WithIceNIC ++                                       // build a NIC
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new chipyard.iobinders.WithLoopbackNIC ++                        // drive NIC IOs with loopback
-  new testchipip.WithTSI ++
-  new icenet.WithIceNIC ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new boom.common.WithNLargeBooms(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class DromajoBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithSimDromajoBridge ++                 // attach Dromajo
-  new testchipip.WithTSI ++
   new chipyard.config.WithTraceIO ++                             // enable the traceio
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new boom.common.WithNSmallBooms(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
-

generators/chipyard/src/main/scala/config/HeteroConfigs.scala

@@ -7,108 +7,39 @@ import freechips.rocketchip.config.{Config}
 // ---------------------
 
 class LargeBoomAndRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
-  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
-  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a SimAXIMem
-  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
-  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
-  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithBootROM ++                             // use default bootrom
-  new chipyard.config.WithUART ++                                // add a UART
-  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
   new boom.common.WithNLargeBooms(1) ++                          // single-core boom
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
 
 // DOC include start: BoomAndRocketWithHwacha
 class HwachaLargeBoomAndHwachaRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.config.WithHwachaTest ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new hwacha.DefaultHwachaConfig ++                          // add hwacha to all harts
-  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new boom.common.WithNLargeBooms(1) ++                      // add 1 boom core
-  new chipyard.iobinders.WithTiedOffDebug ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++     // add 1 rocket core
-  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.config.AbstractConfig)
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new hwacha.DefaultHwachaConfig ++                      // add hwacha to all harts
-  new boom.common.WithNLargeBooms(1) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: BoomAndRocketWithHwacha
-// DOC include start: DualBoomAndRocketOneHwacha
 
+// DOC include start: DualBoomAndRocketOneHwacha
 class LargeBoomAndHwachaRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
   new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
   new chipyard.config.WithMultiRoCCHwacha(1) ++                         // put hwacha on hart-1 (rocket)
-  new chipyard.config.WithL2TLBs(1024) ++
+  new hwacha.DefaultHwachaConfig ++                                     // set default hwacha config keys
-  new boom.common.WithNLargeBooms(1) ++
+  new boom.common.WithNLargeBooms(1) ++                                 // add 1 boom core
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++                // add 1 rocket core
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: DualBoomAndRocketOneHwacha
 
 
 // DOC include start: DualBoomAndRocket
 class DualLargeBoomAndDualRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new boom.common.WithNLargeBooms(2) ++                   // add 2 boom cores
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new freechips.rocketchip.subsystem.WithNBigCores(2) ++  // add 2 rocket cores
-  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new boom.common.WithNLargeBooms(2) ++                   // 2 boom cores
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(2) ++   // 2 rocket cores
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: DualBoomAndRocket
 
 class LargeBoomAndRocketWithControlCoreConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small "control" core
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new boom.common.WithNLargeBooms(1) ++                    // Add 1 boom core
-  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // add 1 rocket core
-  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small control core
-  new boom.common.WithNLargeBooms(1) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
-

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -7,538 +7,180 @@ import freechips.rocketchip.config.{Config}
 // --------------
 
 class RocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
-  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
-  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a blackbox DRAMSim model
-  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
-  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
-  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithBootROM ++                             // use default bootrom
-  new chipyard.config.WithUART ++                                // add a UART
-  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
 
 class HwachaRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.config.WithHwachaTest ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new hwacha.DefaultHwachaConfig ++                        // use Hwacha vector accelerator
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 // DOC include start: GemminiRocketConfig
 class GemminiRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new gemmini.DefaultGemminiConfig ++                        // use Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GemminiRocketConfig
 
-class RoccRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithRoccExample ++    // use example RoCC-based accelerator
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
-
 // DOC include start: JtagRocket
 class jtagRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithSimDebug ++                   // add SimDebug, in addition to default SimSerial
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithSimDebug ++    // add SimJtag and SimSerial, use both to drive sim
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new freechips.rocketchip.subsystem.WithJtagDTM ++        // sets DTM communication interface to JTAG
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: JtagRocket
 
 // DOC include start: DmiRocket
 class dmiRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTiedOffSerial ++          // tie-off serial, override default add SimSerial
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithSimDebug ++               // add SimDebug, override default tie-off debug
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffSerial ++
-  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: DmiRocket
 
 // DOC include start: GCDTLRocketConfig
 class GCDTLRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++          // Use GCD Chisel, connect Tilelink
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GCDTLRocketConfig
 
 // DOC include start: GCDAXI4BlackBoxRocketConfig
 class GCDAXI4BlackBoxRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++          // Use GCD blackboxed verilog, connect by AXI4->Tilelink
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GCDAXI4BlackBoxRocketConfig
 
 class LargeSPIFlashROMRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithSimSPIFlashModel(true) ++      // add the SPI flash model in the harness (read-only)
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
   new chipyard.config.WithSPIFlash ++                       // add the SPI flash controller
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class SmallSPIFlashRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithSimSPIFlashModel(false) ++     // add the SPI flash model in the harness (writeable)
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
   new chipyard.config.WithSPIFlash(0x100000) ++             // add the SPI flash controller (1 MiB)
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class SimAXIRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithSimAXIMem ++                   // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++                       // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class SimBlockDeviceRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithSimBlockDevice ++             // drive block-device IOs with SimBlockDevice
-  new testchipip.WithTSI ++
   new testchipip.WithBlockDevice ++                        // add block-device module to peripherybus
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class BlockDeviceModelRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithBlockDeviceModel ++           // drive block-device IOs with a BlockDeviceModel
-  new testchipip.WithTSI ++
   new testchipip.WithBlockDevice ++                        // add block-device module to periphery bus
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 // DOC include start: GPIORocketConfig
 class GPIORocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithGPIOTiedOff ++                // tie off GPIO inputs into the top
-  new testchipip.WithTSI ++
   new chipyard.config.WithGPIO ++                          // add GPIOs to the peripherybus
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GPIORocketConfig
 
 class QuadRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(4) ++   // quad-core (4 RocketTiles)
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class RV32RocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
   new freechips.rocketchip.subsystem.WithRV32 ++           // set RocketTiles to be 32-bit
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class GB1MemoryRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 // DOC include start: Sha3Rocket
 class Sha3RocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: Sha3Rocket
 
 // DOC include start: InitZeroRocketConfig
 class InitZeroRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++                // add InitZero
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: InitZeroRocketConfig
 
 class LoopbackNICRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithLoopbackNIC ++                        // drive NIC IOs with loopback
-  new testchipip.WithTSI ++
   new icenet.WithIceNIC ++                                         // add an IceNIC
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 // DOC include start: l1scratchpadrocket
-class L1ScratchpadSmallRocketConfig extends Config(
+class ScratchpadOnlyRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use rocket l1 DCache scratchpad as base phys mem
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use rocket l1 scratchpad
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: l1scratchpadrocket
 
+class L1ScratchpadRocketConfig extends Config(
+  new chipyard.config.WithRocketICacheScratchpad ++   // use rocket ICache scratchpad
+  new chipyard.config.WithRocketDCacheScratchpad ++   // use rocket DCache scratchpad
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
 // DOC include start: mbusscratchpadrocket
 class MbusScratchpadRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
   new testchipip.WithBackingScratchpad ++                   // add mbus backing scratchpad
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++       // remove offchip mem port
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: mbusscratchpadrocket
 
 // DOC include start: RingSystemBusRocket
 class RingSystemBusRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new testchipip.WithRingSystemBus ++ // Ring-topology system bus
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: RingSystemBusRocket
 
 class StreamingPassthroughRocketConfig extends Config(
   new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 // DOC include start: StreamingFIRRocketConfig
 class StreamingFIRRocketConfig extends Config (
   new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: StreamingFIRRocketConfig
 
 class SmallNVDLARocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class LargeNVDLARocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
+
+class MMIORocketConfig extends Config(
+  new chipyard.iobinders.WithTieOffL2FBusAXI ++ // Tie-off the incoming MMIO port
+  new chipyard.iobinders.WithSimAXIMMIO ++ // Attach a simulated memory to the outwards MMIO port
+  new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
+  new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala

@@ -15,14 +15,16 @@ import firrtl.options.Viewer.view
 import freechips.rocketchip.stage.RocketChipOptions
 import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
 import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
+import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem}
 import freechips.rocketchip.util.HasRocketChipStageUtils
 import freechips.rocketchip.tile.XLen
 
 import chipyard.TestSuiteHelper
+import chipyard.TestSuitesKey
 
 class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
   // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
-  // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). 
+  // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such).
   override val prerequisites = Seq(
     Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
     Dependency[freechips.rocketchip.stage.phases.AddDefaultTests])
@@ -33,25 +35,11 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
     val suiteHelper = new TestSuiteHelper
     // Use Xlen as a proxy for detecting if we are a processor-like target
     // The underlying test suites expect this field to be defined
-    if (p.lift(XLen).nonEmpty) {
+    val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams)
-      suiteHelper.addRocketTestSuites
+    if (p.lift(XLen).nonEmpty)
-      suiteHelper.addBoomTestSuites
+      // If a custom test suite is set up, use the custom test suite
-      suiteHelper.addArianeTestSuites
+      annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
-    }
 
-    // if hwacha parameter exists then generate its tests
-    // TODO: find a more elegant way to do this. either through
-    // trying to disambiguate BuildRoCC, having a AccelParamsKey,
-    // or having the Accelerator/Tile add its own tests
-    import hwacha.HwachaTestSuites._
-    if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
-      suiteHelper.addSuites(rv64uv.map(_("p")))
-      suiteHelper.addSuites(rv64uv.map(_("vp")))
-      suiteHelper.addSuite(rv64sv("p"))
-      suiteHelper.addSuite(hwachaBmarks)
-      annotations += CustomMakefragSnippet(
-        "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha")
-    }
     RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations
   }
 

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -26,7 +26,7 @@ import ariane.ArianeTile
 
 import boom.common.{BoomTile}
 
-import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
+import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters}
 import testchipip.{CanHaveTraceIOModuleImp}
 
 object MainMemoryConsts {
@@ -56,17 +56,20 @@ class WithBlockDeviceBridge extends OverrideIOBinder({
 
 
 class WithFASEDBridge extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
+  (system: CanHaveMasterAXI4MemPort) => {
-    implicit val p = system.p
+    implicit val p: Parameters = GetSystemParameters(system)
     (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) =>
       val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
                                      axi4.ar.bits.addr.getWidth,
                                      axi4.ar.bits.id.getWidth)
-      FASEDBridge(system.module.clock, axi4, system.module.reset.toBool,
+      system match {
-        CompleteConfig(p(firesim.configs.MemModelKey),
+        case s: BaseSubsystem => FASEDBridge(s.module.clock, axi4, s.module.reset.toBool,
-                       nastiKey,
+          CompleteConfig(p(firesim.configs.MemModelKey),
-                       Some(AXI4EdgeSummary(edge)),
+                         nastiKey,
-                       Some(MainMemoryConsts.globalName)))
+                         Some(AXI4EdgeSummary(edge)),
+                         Some(MainMemoryConsts.globalName)))
+        case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design")
+      }
     })
     Nil
   }

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -69,7 +69,8 @@ class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small")
 class WithFireSimConfigTweaks extends Config(
   // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
   new WithBootROM ++
-  // Optional*: Removing this will require target-software changes to properly capture UART output
+  // Optional*: Removing this will require adjusting the UART baud rate and
+  // potential target-software changes to properly capture UART output
   new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
   // Required: Existing FAME-1 transform cannot handle black-box clock gates
   new WithoutClockGating ++
@@ -85,8 +86,8 @@ class WithFireSimConfigTweaks extends Config(
   new testchipip.WithTSI ++
   // Optional: Removing this will require using an initramfs under linux
   new testchipip.WithBlockDevice ++
-  // Required*:
+  // Required*: Scale default baud rate with periphery bus frequency
-  new chipyard.config.WithUART
+  new chipyard.config.WithUART(BigInt(3686400L))
 )
 
 /*******************************************************************************
@@ -117,6 +118,21 @@ class FireSimQuadRocketConfig extends Config(
   new WithFireSimConfigTweaks ++
   new chipyard.QuadRocketConfig)
 
+// A stripped down configuration that should fit on all supported hosts.
+// Flat to avoid having to reorganize the config class hierarchy to remove certain features 
+class FireSimSmallSystemConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithBootROM ++
+  new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
+  new WithoutClockGating ++
+  new WithoutTLMonitors ++
+  new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
+  new testchipip.WithTSI ++
+  new testchipip.WithBlockDevice ++
+  new chipyard.config.WithUART ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
+  new chipyard.RocketConfig)
 
 //*****************************************************************
 // Boom config, base off chipyard's LargeBoomConfig

scripts/tutorial-patches/RocketConfigs.scala.patch

@@ -1,13 +1,13 @@
 diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
-index f29c580..0bd36ca 100644
+index 8e6e486..fc3a811 100644
 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
 +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
-@@ -333,7 +333,7 @@ class Sha3RocketConfig extends Config(
+@@ -105,7 +105,7 @@ class GB1MemoryRocketConfig extends Config(
-   new chipyard.config.WithBootROM ++
+ 
-   new chipyard.config.WithUART ++
+ // DOC include start: Sha3Rocket
-   new chipyard.config.WithL2TLBs(1024) ++
+ class Sha3RocketConfig extends Config(
 -  new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
 +//  new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
-   new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-   new freechips.rocketchip.subsystem.WithNoSlavePort ++
+   new chipyard.config.AbstractConfig)
-   new freechips.rocketchip.subsystem.WithInclusiveCache ++
+ // DOC include end: Sha3Rocket