From 9718ca91812d682780d076e3d434a12eb70142b7 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 27 Feb 2024 18:53:22 -0800 Subject: [PATCH] Fix configs to use updated SIMT params --- .../main/scala/config/CoalescerConfigs.scala | 34 +++++++++---------- .../main/scala/config/RadianceConfigs.scala | 14 ++++---- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala index 5403b8ec..58456bdd 100644 --- a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala +++ b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala @@ -10,7 +10,7 @@ class MemtraceCoreConfig extends Config( // new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", // traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++ - new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 8) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -29,7 +29,7 @@ class MemtraceCoreNV64B2IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=2) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -43,7 +43,7 @@ class MemtraceCoreNV128B2IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=2) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -57,7 +57,7 @@ class MemtraceCoreNV256B2IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=2) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -71,7 +71,7 @@ class MemtraceCoreNV512B2IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=2) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=2) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -85,7 +85,7 @@ class MemtraceCoreNV64B8IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -99,7 +99,7 @@ class MemtraceCoreNV128B8IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -113,7 +113,7 @@ class MemtraceCoreNV256B8IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -127,7 +127,7 @@ class MemtraceCoreNV512B8IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=8) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=8) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -141,7 +141,7 @@ class MemtraceCoreNV64B16IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=16) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -155,7 +155,7 @@ class MemtraceCoreNV128B16IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=16) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -169,7 +169,7 @@ class MemtraceCoreNV256B16IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=16) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -183,7 +183,7 @@ class MemtraceCoreNV512B16IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=16) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=16) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -197,7 +197,7 @@ class MemtraceCoreNV64B32IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=32) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -211,7 +211,7 @@ class MemtraceCoreNV128B32IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=32) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -225,7 +225,7 @@ class MemtraceCoreNV256B32IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=32) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ @@ -239,7 +239,7 @@ class MemtraceCoreNV512B32IdConfig extends Config( new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", traceHasSource = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++ - new radiance.subsystem.WithSimtLanes(nLanes=32, nSrcIds=32) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=32) ++ // L2 new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala index 36b95af3..f458b0cc 100644 --- a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala @@ -33,7 +33,7 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn // ---------------- class RadianceBaseConfig extends Config( - new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 4) ++ + new radiance.subsystem.WithSimtConfig(nWarps = 16, nCoreLanes = 8, nMemLanes = 4, nSrcIds = 8) ++ new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ new WithExtMemSize(BigInt("80000000", 16)) ++ new WithRadBootROM() ++ @@ -46,19 +46,19 @@ class RadianceBaseConfig extends Config( class RadianceConfig extends Config( new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new radiance.subsystem.WithCoalescer(nNewSrcIds = 4) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++ new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++ new RadianceBaseConfig) class RadianceGemminiConfig extends Config( new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new radiance.subsystem.WithCoalescer(nNewSrcIds = 4) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++ new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++ new RadianceBaseConfig) class RadianceNoCacheConfig extends Config( new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++ new RadianceBaseConfig) class RadianceNoCoalConfig extends Config( @@ -86,8 +86,8 @@ class RadianceNoROMConfig extends Config( class RadianceFuzzerConfig extends Config( new radiance.subsystem.WithFuzzerCores(1, useVxCache = false) ++ - new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 4) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 2) ++ new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ new chipyard.harness.WithCeaseSuccess ++ new chipyard.iobinders.WithCeasePunchThrough ++ @@ -111,7 +111,7 @@ class RadianceOldCacheConfig extends Config( class RocketDummyVortexConfig extends Config( new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new radiance.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 16) ++ new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ new WithExtMemSize(BigInt("80000000", 16)) ++ new testchipip.soc.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++