wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

[firechip] Set the cover property library in FireSim Harnesses

Browse Source
This commit is contained in:
David Biancolin
2020-05-17 00:18:54 +00:00
parent 99846c1ccb
commit 96e838c773
2 changed files with 2 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
generators/firechip/src/main/scala/FireSim.scala
View File

@@ -29,6 +29,7 @@ object NodeIdx {
} }
class FireSim(implicit val p: Parameters) extends RawModule { class FireSim(implicit val p: Parameters) extends RawModule {
freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary())
val clockBridge = Module(new RationalClockBridge) val clockBridge = Module(new RationalClockBridge)
val clock = clockBridge.io.clocks.head val clock = clockBridge.io.clocks.head
val reset = WireInit(false.B) val reset = WireInit(false.B)

1
generators/firechip/src/main/scala/FireSimMulticlockPOC.scala
View File

@@ -84,6 +84,7 @@ class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.Digita
// Harness Definition // Harness Definition
class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule {
freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary())
val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*))
val refClock = clockBridge.io.clocks.head val refClock = clockBridge.io.clocks.head
val reset = WireInit(false.B) val reset = WireInit(false.B)