Moved clkgen -> .clkgen and pads -> .pads
They no longer compile with the latest Chisel/FIRRTL, and may not be supported. However, future work will need them, so this keeps the files around but are ignored by sbt.
This commit is contained in:
Adam Izraelevitz
226
tapeout/src/test/scala/transforms/.pads/AddIOPadsSpec.scala
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226
tapeout/src/test/scala/transforms/.pads/AddIOPadsSpec.scala
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@@ -0,0 +1,226 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms.pads
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import chisel3._
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import firrtl._
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import org.scalatest.{FlatSpec, Matchers}
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import chisel3.experimental._
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import chisel3.util.HasBlackBoxInline
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import chisel3.iotesters._
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class BB extends BlackBox with HasBlackBoxInline {
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val io = IO(new Bundle {
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val c = Input(SInt(14.W))
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val z = Output(SInt(16.W))
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val analog1 = Analog(3.W)
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val analog2 = analog1.chiselCloneType
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})
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// Generates a "FakeBB.v" file with the following Verilog module
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setInline("FakeBB.v",
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s"""
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|module BB(
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| input [15:0] c,
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| output [15:0] z,
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| inout [2:0] analog1,
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| inout [2:0] analog2
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|);
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| always @* begin
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| z = 2 * c;
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| analog2 = analog1 + 1;
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| end
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|endmodule
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""".stripMargin)
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}
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// If no template file is provided, it'll use the default one (example) in the resource folder
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// Default pad side is Top if no side is specified for a given IO
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// You can designate the number of different supply pads on each chip side
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class ExampleTopModuleWithBB extends TopModule(
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supplyAnnos = Seq(
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SupplyAnnotation(padName = "vdd", leftSide = 3, bottomSide = 2),
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SupplyAnnotation(padName = "vss", rightSide = 1)
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)) {
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val io = IO(new Bundle {
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val a = Input(UInt(15.W))
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val b = a.chiselCloneType
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val c = Input(SInt(14.W))
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val x = Output(UInt(16.W))
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val y = x.chiselCloneType
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val z = Output(SInt(16.W))
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val analog1 = Analog(3.W)
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val analog2 = analog1.chiselCloneType
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val v = Output(Vec(3, UInt(5.W)))
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})
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// Can annotate aggregates with pad side location + pad name (should be a name in the yaml template)
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annotatePad(io.v, Right, "from_tristate_foundry")
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// Can annotate individual elements
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annotatePad(io.analog1, Left, "fast_custom")
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annotatePad(io.analog2, Bottom, "slow_foundry")
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// Looks for a pad that matches the IO type (digital in, digital out, analog) if no name is specified
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Seq(io.a, io.b, io.c, io.x) foreach { x => annotatePad(x, Left) }
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// Some signals might not want pads associated with them
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noPad(io.y)
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// Clk might come directly from bump
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noPad(clock)
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val bb = Module(new BB())
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bb.io.c := io.c
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io.z := bb.io.z
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bb.io.analog1 <> io.analog1
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bb.io.analog2 <> io.analog2
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io.x := io.a + 1.U
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io.y := io.b - 1.U
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io.v foreach { lhs => lhs := io.a }
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}
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class SimpleTopModuleTester(c: ExampleTopModuleWithBB) extends PeekPokeTester(c) {
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val ax = Seq(5, 3)
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val bx = Seq(8, 2)
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val cx = Seq(-11, -9)
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for (i <- 0 until ax.length) {
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poke(c.io.a, ax(i))
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poke(c.io.b, bx(i))
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poke(c.io.c, cx(i))
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expect(c.io.x, ax(i) + 1)
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expect(c.io.y, bx(i) - 1)
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expect(c.io.z, 2 * cx(i))
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c.io.v foreach { out => expect(out, ax(i)) }
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}
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// Analog can't be peeked + poked
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}
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// Notes: Annotations
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// a in 15: left, default digital
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// b in 15: left, default digital
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// c in 14: left, default digital ; signed
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// x out 16: left, default digital
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// y out: NOPAD
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// clk in: NOPAD
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// analog1 3: left, fast_custom
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// analog2 3: bottom, slow_foundry
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// v (vec of 3 with 5, out): right, from_tristate_foundry
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// reset in: UNSPECIFIED: top, default digital
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// z out 16: UNSPECIFIED: top, default digital ; signed
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// vdd, left: 3, group of 1
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// vdd, bottom: 2, group of 1
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// vss, right: 1, group of 2
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// Notes: Used pads
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// digital horizontal (from_tristate_foundry)
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// in + out
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// analog fast_custom horizontal
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// analog slow_foundry vertical
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// digital vertical (from_tristate_foundry)
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// in + out
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// vdd horizontal
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// vdd vertical
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// vss horizontal
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class IOPadSpec extends FlatSpec with Matchers {
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def readOutputFile(dir: String, f: String): String =
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scala.io.Source.fromFile(Seq(dir, f).mkString("/")).getLines.mkString("\n")
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def readResource(resource: String): String = {
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val stream = getClass.getResourceAsStream(resource)
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scala.io.Source.fromInputStream(stream).mkString
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}
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def checkOutputs(dir: String) = {
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// Show that black box source helper is run
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//readOutputFile(dir, "black_box_verilog_files.f") should include ("pad_supply_vdd_horizontal.v")
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val padBBEx = s"""// Digital Pad Example
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|// Signal Direction: Input
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|// Pad Orientation: Horizontal
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|// Call your instance PAD
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|module pad_digital_from_tristate_foundry_horizontal_input(
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| input in,
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| output reg out
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|);
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| // Where you would normally dump your pad instance
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| always @* begin
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| out = in;
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| end
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|endmodule
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|module pad_digital_from_tristate_foundry_horizontal_input_array #(
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| parameter int WIDTH=1
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|)(
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| input [WIDTH-1:0] in,
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| output reg [WIDTH-1:0] out
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|);
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| pad_digital_from_tristate_foundry_horizontal_input pad_digital_from_tristate_foundry_horizontal_input[WIDTH-1:0](
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| .in(in),
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| .out(out)
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| );""".stripMargin
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// Make sure black box templating is OK
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readOutputFile(dir, "pad_digital_from_tristate_foundry_horizontal_input_array.v") should include (padBBEx)
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val verilog = readOutputFile(dir, "ExampleTopModuleWithBB.v")
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// Pad frame + top should be exact
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verilog should include (readResource("/PadAnnotationVerilogPart.v"))
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// Pad Placement IO file should be exact
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val padIO = readOutputFile(dir, "pads.io")
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padIO should include(readResource("/PadPlacement.io"))
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}
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behavior of "top module with blackbox"
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import barstools.tapeout.transforms._
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it should "pass simple testbench" in {
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val optionsManager = new TesterOptionsManager {
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firrtlOptions = firrtlOptions.copy(
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compilerName = "verilog"
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// annotations = List(TechnologyLocation("./RealTech"))
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)
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testerOptions = testerOptions.copy(isVerbose = true, backendName = "verilator", displayBase = 10)
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commonOptions = commonOptions.copy(targetDirName = "test_run_dir/PadsTB")
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}
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iotesters.Driver.execute(() => new ExampleTopModuleWithBB, optionsManager) { c =>
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val dir = optionsManager.commonOptions.targetDirName
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checkOutputs(dir)
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new SimpleTopModuleTester(c)
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} should be (true)
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}
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/*
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it should "create proper IO pads + black box in low firrtl" in {
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val optionsManager = new ExecutionOptionsManager("barstools") with HasChiselExecutionOptions with HasFirrtlOptions {
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firrtlOptions = firrtlOptions.copy(compilerName = "low")
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commonOptions = commonOptions.copy(targetDirName = "test_run_dir/LoFirrtl")
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//commonOptions = commonOptions.copy(globalLogLevel = logger.LogLevel.Info)
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}
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val success = chisel3.Driver.execute(optionsManager, () => new ExampleTopModuleWithBB) match {
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case ChiselExecutionSuccess(_, chirrtl, Some(FirrtlExecutionSuccess(_, firrtl))) =>
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firrtl should include ("ExampleTopModuleWithBB_PadFrame")
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firrtl should include ("ExampleTopModuleWithBB_Internal")
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firrtl should not include ("FakeBBPlaceholder")
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true
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case _ => false
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}
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success should be (true)
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}
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*/
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it should "create proper IO pads + black box in verilog" in {
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val optionsManager = new ExecutionOptionsManager("barstools") with HasChiselExecutionOptions with HasFirrtlOptions {
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firrtlOptions = firrtlOptions.copy(
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compilerName = "verilog"
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)
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commonOptions = commonOptions.copy(targetDirName = "test_run_dir/PadsVerilog")
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//commonOptions = commonOptions.copy(globalLogLevel = logger.LogLevel.Info)
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}
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val success = chisel3.Driver.execute(optionsManager, () => new ExampleTopModuleWithBB) match {
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case ChiselExecutionSuccess(_, chirrtl, Some(FirrtlExecutionSuccess(_, verilog))) =>
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true
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case _ => false
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}
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success should be (true)
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val dir = optionsManager.commonOptions.targetDirName
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checkOutputs(dir)
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}
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}
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