Moved clkgen -> .clkgen and pads -> .pads
They no longer compile with the latest Chisel/FIRRTL, and may not be supported. However, future work will need them, so this keeps the files around but are ignored by sbt.
This commit is contained in:
Adam Izraelevitz
133
tapeout/src/main/scala/transforms/.pads/AddPadFrame.scala
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133
tapeout/src/main/scala/transforms/.pads/AddPadFrame.scala
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// See LICENSE for license details.
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package barstools.tapeout.transforms.pads
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import firrtl.annotations._
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import firrtl.ir._
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import firrtl._
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import firrtl.passes.Pass
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// Analog is like UInt, SInt; it's not a direction (which is kind of weird)
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// WARNING: Analog type is associated with Verilog InOut! i.e. even if digital pads are tri-statable, b/c tristate
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// requires an additional ctrl signal, digital pads must be operated in a single "static" condition here; Analog will
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// be paired with analog pads
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class AddPadFrame(
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topMod: String,
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padFrameName: String,
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topInternalName: String,
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ioPads: Seq[PortIOPad],
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supplyPads: Seq[TopSupplyPad]) extends Pass {
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def run(c: Circuit): Circuit = {
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// New modules consist of old modules (with top renamed to internal) + padFrame + newTop
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val newMods = c.modules.map {
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case mod: Module if mod.name == topMod =>
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// Original top module is now internal module
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mod.copy(name = topInternalName)
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case m => m
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} ++ Seq(buildPadFrame(), buildTopWrapper())
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// Reparent so circuit top is whatever uses pads!
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// TODO: Can the top level be a blackbox?
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c.copy(modules = newMods, main = topMod)
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}
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def intName(p: PortIOPad) = s"${p.portName}_Int"
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def extName(p: PortIOPad) = s"${p.portName}_Ext"
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def buildTopWrapper(): Module = {
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// outside -> padframe -> internal
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// Top (with same name) contains 1) padframe + 2) internal signals
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val padFrameInst = WDefInstance(padFrameName, padFrameName)
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val topInternalInst = WDefInstance(topInternalName, topInternalName)
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val padFrameRef = WRef(padFrameName)
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val topInternalRef = WRef(topInternalName)
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val connects = ioPads.map { p =>
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val io = WRef(p.portName)
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val intIo = WSubField(topInternalRef, p.portName)
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val padFrameIntIo = WSubField(padFrameRef, intName(p))
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val padFrameExtIo = WSubField(padFrameRef, extName(p))
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p.port.tpe match {
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case AnalogType(_) =>
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// Analog pads only have 1 port
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// If Analog port doesn't have associated pad, don't hook it up to the padframe
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val analogAttachInt = Seq(Attach(NoInfo, Seq(io, intIo)))
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if (p.pad.isEmpty) analogAttachInt
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else analogAttachInt :+ Attach(NoInfo, Seq(io, padFrameExtIo))
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case _ => p.portDirection match {
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case Input =>
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// input to padframe ; padframe to internal
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Seq(Connect(NoInfo, padFrameExtIo, io), Connect(NoInfo, intIo, padFrameIntIo))
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case Output =>
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// internal to padframe ; padframe to output
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Seq(Connect(NoInfo, padFrameIntIo, intIo), Connect(NoInfo, io, padFrameExtIo))
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}
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}
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}.flatten
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val stmts = Seq(padFrameInst, topInternalInst) ++ connects
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val ports = ioPads.map(p => p.port)
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Module(NoInfo, topMod, ports = ports, body = Block(stmts))
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}
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def buildPadFrame(): Module = {
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// Internal = connection to original RTL; External = connection to outside world
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// Note that for analog pads, since there's only 1 port, only _Ext is used
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val intPorts = ioPads.map(p => p.port.tpe match {
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case AnalogType(_) => None
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case _ => Some(p.port.copy(name = intName(p), direction = Utils.swap(p.portDirection)))
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}).flatten
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val extPorts = ioPads.map(p => p.port.tpe match {
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// If an analog port doesn't have a pad associated with it, don't add it to the padframe
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case AnalogType(_) if p.pad.isEmpty => None
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case _ => Some(p.port.copy(name = extName(p)))
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} ).flatten
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// Only create pad black boxes for ports that require them
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val ioPadInsts = ioPads.filter(x => !x.pad.isEmpty).map(p => WDefInstance(p.firrtlBBName, p.firrtlBBName))
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// Connect to pad only if used ; otherwise leave dangling for Analog
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// and just connect through for digital (assumes no supplies)
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val connects = ioPads.map { p =>
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val intRef = WRef(intName(p), p.port.tpe)
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val extRef = WRef(extName(p), p.port.tpe)
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p.pad match {
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// No pad needed -- just connect through
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case None => p.port.tpe match {
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case AnalogType(_) =>
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Seq(EmptyStmt)
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case _ =>
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val (lhs, rhs) = p.portDirection match {
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case Input => (intRef, extRef)
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case Output => (extRef, intRef)
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}
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Seq(Connect(NoInfo, lhs, rhs))
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}
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// Add pad
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case Some(x) =>
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val padRef = WRef(p.firrtlBBName)
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p.port.tpe match {
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// Analog type has 1:1 mapping to inout
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case AnalogType(_) =>
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val padIORef = WSubField(padRef, AnalogPad.ioName)
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Seq(Attach(NoInfo, Seq(padIORef, extRef)))
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// Normal verilog in/out can be mapped to uint, sint, or clocktype, so need cast
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case _ =>
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val padBBType = UIntType(getWidth(p.port.tpe))
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val padInRef = WSubField(padRef, DigitalPad.inName, padBBType, UNKNOWNGENDER)
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val padOutRef = WSubField(padRef, DigitalPad.outName, padBBType, UNKNOWNGENDER)
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val (rhsPadIn, lhsPadOut) = p.portDirection match {
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case Input => (extRef, intRef)
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case Output => (intRef, extRef)
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}
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// Pad inputs are treated as UInts, so need to do type conversion
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// from type to UInt pad input; from pad output to type
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Seq(
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Connect(NoInfo, padInRef, castRhs(padBBType, rhsPadIn)),
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Connect(NoInfo, lhsPadOut, castRhs(p.port.tpe, padOutRef)))
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}
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}
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}.flatten
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val supplyPadInsts = supplyPads.map(p => p.instNames.map(n => WDefInstance(n, p.firrtlBBName))).flatten
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Module(NoInfo, padFrameName, ports = intPorts ++ extPorts, body = Block(ioPadInsts ++ connects ++ supplyPadInsts))
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}
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}
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