Moved clkgen -> .clkgen and pads -> .pads
They no longer compile with the latest Chisel/FIRRTL, and may not be supported. However, future work will need them, so this keeps the files around but are ignored by sbt.
This commit is contained in:
Adam Izraelevitz
248
tapeout/src/main/scala/transforms/.clkgen/ClkAnnotations.scala
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248
tapeout/src/main/scala/transforms/.clkgen/ClkAnnotations.scala
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@@ -0,0 +1,248 @@
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package barstools.tapeout.transforms.clkgen
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import net.jcazevedo.moultingyaml._
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import firrtl.annotations._
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import chisel3.experimental._
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import chisel3._
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import firrtl._
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import firrtl.transforms.DedupModules
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object ClkAnnotationsYaml extends DefaultYamlProtocol {
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implicit val _clksrc = yamlFormat3(ClkSrc)
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implicit val _sink = yamlFormat1(Sink)
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implicit val _clkport = yamlFormat2(ClkPortAnnotation)
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implicit val _genclk = yamlFormat4(GeneratedClk)
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implicit val _clkmod = yamlFormat2(ClkModAnnotation)
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}
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case class ClkSrc(period: Double, waveform: Seq[Double] = Seq(), async: Seq[String] = Seq()) {
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def getWaveform = if (waveform == Seq.empty) Seq(0, period/2) else waveform
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// async = ids of top level clocks that are async with this clk
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// Default is 50% duty cycle, period units is default
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require(getWaveform.sorted == getWaveform, "Waveform edges must be in order")
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require(getWaveform.length == 2, "Must specify time for rising edge, then time for falling edge")
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}
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case class Sink(src: Option[ClkSrc] = None)
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case class ClkPortAnnotation(tag: Option[Sink] = None, id: String) {
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import ClkAnnotationsYaml._
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def serialize: String = this.toYaml.prettyPrint
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}
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abstract class ClkModType {
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def serialize: String
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}
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case object ClkMux extends ClkModType {
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def serialize: String = "mux"
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}
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case object ClkDiv extends ClkModType {
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def serialize: String = "div"
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}
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case object ClkGen extends ClkModType {
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def serialize: String = "gen"
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}
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// Unlike typical SDC, starts at 0.
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// Otherwise, see pg. 63 of "Constraining Designs for Synthesis and Timing Analysis"
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// by S. Gangadharan
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// original clk: |-----|_____|-----|_____|
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// edges: 0 1 2 3 4
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// div. by 4, 50% duty cycle --> edges = 0, 2, 4
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// ---> |-----------|___________|
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// sources = source id's
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case class GeneratedClk(
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id: String,
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sources: Seq[String] = Seq(),
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referenceEdges: Seq[Int] = Seq(),
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period: Option[Double] = None) {
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require(referenceEdges.sorted == referenceEdges, "Edges must be in order for generated clk")
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if (referenceEdges.nonEmpty) require(referenceEdges.length % 2 == 1, "# of reference edges must be odd!")
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}
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case class ClkModAnnotation(tpe: String, generatedClks: Seq[GeneratedClk]) {
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def modType: ClkModType = HasClkAnnotation.modType(tpe)
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modType match {
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case ClkDiv =>
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generatedClks foreach { c =>
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require(c.referenceEdges.nonEmpty, "Reference edges must be defined for clk divider!")
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require(c.sources.length == 1, "Clk divider output can only have 1 source")
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require(c.period.isEmpty, "No period should be specified for clk divider output")
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}
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case ClkMux =>
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generatedClks foreach { c =>
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require(c.referenceEdges.isEmpty, "Reference edges must not be defined for clk mux!")
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require(c.period.isEmpty, "No period should be specified for clk mux output")
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require(c.sources.nonEmpty, "Clk muxes must have sources!")
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}
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case ClkGen =>
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generatedClks foreach { c =>
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require(c.referenceEdges.isEmpty, "Reference edges must not be defined for clk gen!")
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require(c.sources.isEmpty, "Clk generators shouldn't have constrained sources")
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require(c.period.nonEmpty, "Clk generator output period should be specified!")
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}
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}
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import ClkAnnotationsYaml._
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def serialize: String = this.toYaml.prettyPrint
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}
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abstract class FirrtlClkTransformAnnotation {
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def targetName: String
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}
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// Firrtl version
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case class TargetClkModAnnoF(target: ModuleName, anno: ClkModAnnotation) extends FirrtlClkTransformAnnotation {
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def getAnno = Annotation(target, classOf[ClkSrcTransform], anno.serialize)
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def targetName = target.name
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def modType = anno.modType
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def generatedClks = anno.generatedClks
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def getAllClkPorts = anno.generatedClks.map(x =>
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List(List(x.id), x.sources).flatten).flatten.distinct.map(Seq(targetName, _).mkString("."))
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}
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// Chisel version
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case class TargetClkModAnnoC(target: Module, anno: ClkModAnnotation) {
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def getAnno = ChiselAnnotation(target, classOf[ClkSrcTransform], anno.serialize)
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}
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// Firrtl version
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case class TargetClkPortAnnoF(target: ComponentName, anno: ClkPortAnnotation) extends FirrtlClkTransformAnnotation {
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def getAnno = Annotation(target, classOf[ClkSrcTransform], anno.serialize)
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def targetName = Seq(target.module.name, target.name).mkString(".")
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def modId = Seq(target.module.name, anno.id).mkString(".")
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def sink = anno.tag
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}
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// Chisel version
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case class TargetClkPortAnnoC(target: Element, anno: ClkPortAnnotation) {
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def getAnno = ChiselAnnotation(target, classOf[ClkSrcTransform], anno.serialize)
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}
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object HasClkAnnotation {
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import ClkAnnotationsYaml._
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def modType(tpe: String): ClkModType = tpe match {
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case s: String if s == ClkMux.serialize => ClkMux
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case s: String if s == ClkDiv.serialize => ClkDiv
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case s: String if s == ClkGen.serialize => ClkGen
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case _ => throw new Exception("Clock module annotaiton type invalid")
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}
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def unapply(a: Annotation): Option[FirrtlClkTransformAnnotation] = a match {
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case Annotation(f, t, s) if t == classOf[ClkSrcTransform] => f match {
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case m: ModuleName =>
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Some(TargetClkModAnnoF(m, s.parseYaml.convertTo[ClkModAnnotation]))
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case c: ComponentName =>
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Some(TargetClkPortAnnoF(c, s.parseYaml.convertTo[ClkPortAnnotation]))
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case _ => throw new Exception("Clk source annotation only valid on module or component!")
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}
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case _ => None
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}
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def apply(annos: Seq[Annotation]): Option[(Seq[TargetClkModAnnoF],Seq[TargetClkPortAnnoF])] = {
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// Get all clk-related annotations
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val clkAnnos = annos.map(x => unapply(x)).flatten
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val targets = clkAnnos.map(x => x.targetName)
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require(targets.distinct.length == targets.length, "Only 1 clk related annotation is allowed per component/module")
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if (clkAnnos.length == 0) None
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else {
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val componentAnnos = clkAnnos.filter {
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case TargetClkPortAnnoF(ComponentName(_, ModuleName(_, _)), _) => true
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case _ => false
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}.map(x => x.asInstanceOf[TargetClkPortAnnoF])
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val associatedMods = componentAnnos.map(x => x.target.module.name)
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val moduleAnnos = clkAnnos.filter {
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case TargetClkModAnnoF(ModuleName(m, _), _) =>
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require(associatedMods contains m, "Clk modules should always have clk port annotations!")
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true
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case _ => false
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}.map(x => x.asInstanceOf[TargetClkModAnnoF])
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Some((moduleAnnos, componentAnnos))
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}
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}
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}
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// Applies to both black box + normal module
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trait IsClkModule {
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self: chisel3.Module =>
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private def doNotDedup(module: Module): Unit = {
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annotate(ChiselAnnotation(module, classOf[DedupModules], "nodedup!"))
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}
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doNotDedup(this)
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private def extractElementNames(signal: Data): Seq[String] = {
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val names = signal match {
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case elt: Record =>
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elt.elements.map { case (key, value) => extractElementNames(value).map(x => key + "_" + x) }.toSeq.flatten
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case elt: Vec[_] =>
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elt.zipWithIndex.map { case (elt, i) => extractElementNames(elt).map(x => i + "_" + x) }.toSeq.flatten
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case elt: Element => Seq("")
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case elt => throw new Exception(s"Cannot extractElementNames for type ${elt.getClass}")
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}
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names.map(s => s.stripSuffix("_"))
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}
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// TODO: Replace!
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def extractElements(signal: Data): Seq[Element] = {
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signal match {
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case elt: Record =>
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elt.elements.map { case (key, value) => extractElements(value) }.toSeq.flatten
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case elt: Vec[_] =>
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elt.map { elt => extractElements(elt) }.toSeq.flatten
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case elt: Element => Seq(elt)
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case elt => throw new Exception(s"Cannot extractElements for type ${elt.getClass}")
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}
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}
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def getIOName(signal: Element): String = {
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val possibleNames = extractElements(io).zip(extractElementNames(io)).map {
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case (sig, name) if sig == signal => Some(name)
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case _ => None
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}.flatten
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if (possibleNames.length == 1) possibleNames.head
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else throw new Exception("You can only get the name of an io port!")
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}
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def annotateDerivedClks(tpe: ClkModType, generatedClks: Seq[GeneratedClk]): Unit =
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annotateDerivedClks(ClkModAnnotation(tpe.serialize, generatedClks))
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def annotateDerivedClks(anno: ClkModAnnotation): Unit = annotateDerivedClks(this, anno)
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def annotateDerivedClks(m: Module, anno: ClkModAnnotation): Unit =
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annotate(TargetClkModAnnoC(m, anno).getAnno)
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def annotateClkPort(p: Element): Unit = annotateClkPort(p, None, "")
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def annotateClkPort(p: Element, sink: Sink): Unit = annotateClkPort(p, Some(sink), "")
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def annotateClkPort(p: Element, id: String): Unit = annotateClkPort(p, None, id)
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def annotateClkPort(p: Element, sink: Sink, id: String): Unit = annotateClkPort(p, Some(sink), id)
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def annotateClkPort(p: Element, sink: Option[Sink], id: String): Unit = {
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// If no id is specified, it'll try to figure out a name, assuming p is an io port
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val newId = id match {
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case "" =>
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getIOName(p)
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case _ => id
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}
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annotateClkPort(p, ClkPortAnnotation(sink, newId))
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}
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def annotateClkPort(p: Element, anno: ClkPortAnnotation): Unit = {
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p.dir match {
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case chisel3.core.Direction.Input =>
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require(anno.tag.nonEmpty, "Module inputs must be clk sinks")
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require(anno.tag.get.src.isEmpty,
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"Clock module (not top) input clks should not have clk period, etc. specified")
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case chisel3.core.Direction.Output =>
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require(anno.tag.isEmpty, "Module outputs must not be clk sinks (they're sources!)")
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case _ =>
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throw new Exception("Clk port direction must be specified!")
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}
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p match {
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case _: chisel3.core.Clock =>
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case _ => throw new Exception("Clock port must be of type Clock")
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}
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annotate(TargetClkPortAnnoC(p, anno).getAnno)
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}
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}
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