From 95666677674be38f32390628154eba83b9af4f08 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 18:31:47 -0700 Subject: [PATCH] Remove bus-to-bus crossings --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 6 ------ 1 file changed, 6 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 3643c66e..56280649 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -34,11 +34,5 @@ class ChipLikeQuadRocketConfig extends Config( // Create the uncore clock group new chipyard.clocking.WithClockGroupsCombinedByName("uncore", "implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus") ++ - // Set up the crossings - new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between SBUS and FBUS - new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS - new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS - new chipyard.config.AbstractConfig)